[PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Chris Wilson]

Our callers fall into two categories, those passing timeout=0 who just
want to flush request retirements and those passing a timeout that need
to wait for submission completion (e.g. intel_gt_wait_for_idle()).
Currently, we only wait for a snapshot of timelines at the start of the
wait (but there was an expection that new requests would cause timelines
to appear at the end). However, our callers, such as
intel_gt_wait_for_idle() before suspend, do require us to wait for the
power management requests emitted by retirement as well. If we don't,
then it takes an extra second or two for the background worker to flush
the queue and mark the GT as idle.

Fixes: 7e8057626640 ("drm/i915: Drop struct_mutex from around i915_retire_requests()")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_requests.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index b73229a84d85..ccbddddbbd52 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -33,7 +33,6 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 {
 	struct intel_gt_timelines *timelines = &gt->timelines;
 	struct intel_timeline *tl, *tn;
-	unsigned long active_count = 0;
 	unsigned long flags;
 	bool interruptible;
 	LIST_HEAD(free);
@@ -46,10 +45,8 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 
 	spin_lock_irqsave(&timelines->lock, flags);
 	list_for_each_entry_safe(tl, tn, &timelines->active_list, link) {
-		if (!mutex_trylock(&tl->mutex)) {
-			active_count++; /* report busy to caller, try again? */
+		if (!mutex_trylock(&tl->mutex))
 			continue;
-		}
 
 		intel_timeline_get(tl);
 		GEM_BUG_ON(!tl->active_count);
@@ -74,9 +71,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 
 		/* Resume iteration after dropping lock */
 		list_safe_reset_next(tl, tn, link);
-		if (--tl->active_count)
-			active_count += !!rcu_access_pointer(tl->last_request.fence);
-		else
+		if (!--tl->active_count)
 			list_del(&tl->link);
 
 		mutex_unlock(&tl->mutex);
@@ -92,7 +87,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 	list_for_each_entry_safe(tl, tn, &free, link)
 		__intel_timeline_free(&tl->kref);
 
-	return active_count ? timeout : 0;
+	return list_empty(&timelines->active_list) ? 0 : timeout;
 }
 
 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
-- 
2.24.0

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[Intel-gfx] [PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Chris Wilson]

Our callers fall into two categories, those passing timeout=0 who just
want to flush request retirements and those passing a timeout that need
to wait for submission completion (e.g. intel_gt_wait_for_idle()).
Currently, we only wait for a snapshot of timelines at the start of the
wait (but there was an expection that new requests would cause timelines
to appear at the end). However, our callers, such as
intel_gt_wait_for_idle() before suspend, do require us to wait for the
power management requests emitted by retirement as well. If we don't,
then it takes an extra second or two for the background worker to flush
the queue and mark the GT as idle.

Fixes: 7e8057626640 ("drm/i915: Drop struct_mutex from around i915_retire_requests()")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_requests.c | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
index b73229a84d85..ccbddddbbd52 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
@@ -33,7 +33,6 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 {
 	struct intel_gt_timelines *timelines = &gt->timelines;
 	struct intel_timeline *tl, *tn;
-	unsigned long active_count = 0;
 	unsigned long flags;
 	bool interruptible;
 	LIST_HEAD(free);
@@ -46,10 +45,8 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 
 	spin_lock_irqsave(&timelines->lock, flags);
 	list_for_each_entry_safe(tl, tn, &timelines->active_list, link) {
-		if (!mutex_trylock(&tl->mutex)) {
-			active_count++; /* report busy to caller, try again? */
+		if (!mutex_trylock(&tl->mutex))
 			continue;
-		}
 
 		intel_timeline_get(tl);
 		GEM_BUG_ON(!tl->active_count);
@@ -74,9 +71,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 
 		/* Resume iteration after dropping lock */
 		list_safe_reset_next(tl, tn, link);
-		if (--tl->active_count)
-			active_count += !!rcu_access_pointer(tl->last_request.fence);
-		else
+		if (!--tl->active_count)
 			list_del(&tl->link);
 
 		mutex_unlock(&tl->mutex);
@@ -92,7 +87,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
 	list_for_each_entry_safe(tl, tn, &free, link)
 		__intel_timeline_free(&tl->kref);
 
-	return active_count ? timeout : 0;
+	return list_empty(&timelines->active_list) ? 0 : timeout;
 }
 
 int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
-- 
2.24.0

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[PATCH 2/5] drm/i915/selftests: Exercise rc6 handling

[Chris Wilson]

Reading from CTX_INFO upsets rc6, requiring us to detect and prevent
possible rc6 context corruption. Poke at the bear!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c           |   4 +
 drivers/gpu/drm/i915/gt/selftest_gt_pm.c      |  13 ++
 drivers/gpu/drm/i915/gt/selftest_rc6.c        | 139 ++++++++++++++++++
 drivers/gpu/drm/i915/gt/selftest_rc6.h        |  12 ++
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 5 files changed, 169 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.c
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.h

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 602a02d01850..abcf6bbb71ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -782,3 +782,7 @@ u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
 {
 	return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
 }
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_rc6.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index d1752f15702a..1d5bf93d1258 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -6,6 +6,7 @@
  */
 
 #include "selftest_llc.h"
+#include "selftest_rc6.h"
 
 static int live_gt_resume(void *arg)
 {
@@ -58,3 +59,15 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
 
 	return intel_gt_live_subtests(tests, &i915->gt);
 }
+
+int intel_gt_pm_late_selftests(struct drm_i915_private *i915)
+{
+	static const struct i915_subtest tests[] = {
+		SUBTEST(live_rc6_ctx),
+	};
+
+	if (intel_gt_is_wedged(&i915->gt))
+		return 0;
+
+	return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
new file mode 100644
index 000000000000..6b4cb5c7d446
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -0,0 +1,139 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_context.h"
+#include "intel_engine_pm.h"
+#include "intel_gt_requests.h"
+#include "intel_ring.h"
+#include "selftest_rc6.h"
+
+#include "selftests/i915_random.h"
+
+static const u32 *__live_rc6_ctx(struct intel_context *ce)
+{
+	struct i915_request *rq;
+	u32 const *result;
+	u32 cmd;
+	u32 *cs;
+
+	rq = intel_context_create_request(ce);
+	if (IS_ERR(rq))
+		return ERR_CAST(rq);
+
+	cs = intel_ring_begin(rq, 4);
+	if (IS_ERR(cs)) {
+		i915_request_add(rq);
+		return cs;
+	}
+
+	cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+	if (INTEL_GEN(rq->i915) >= 8)
+		cmd++;
+
+	*cs++ = cmd;
+	*cs++ = 0xA300; /* CTX_INFO */
+	*cs++ = ce->timeline->hwsp_offset + 8;
+	*cs++ = 0;
+	intel_ring_advance(rq, cs);
+
+	result = rq->hwsp_seqno + 2;
+	i915_request_add(rq);
+
+	return result;
+}
+
+static struct intel_engine_cs **
+randomised_engines(struct intel_gt *gt,
+		   struct rnd_state *prng,
+		   unsigned int *count)
+{
+	struct intel_engine_cs *engine, **engines;
+	enum intel_engine_id id;
+	int n;
+
+	n = 0;
+	for_each_engine(engine, gt, id)
+		n++;
+	if (!n)
+		return NULL;
+
+	engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL);
+	if (!engines)
+		return NULL;
+
+	n = 0;
+	for_each_engine(engine, gt, id)
+		engines[n++] = engine;
+
+	i915_prandom_shuffle(engines, sizeof(*engines), n, prng);
+
+	*count = n;
+	return engines;
+}
+
+int live_rc6_ctx(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs **engines;
+	unsigned int n, count;
+	I915_RND_STATE(prng);
+	int err = 0;
+
+	/* A read of CTX_INFO upsets rc6. Poke the bear! */
+
+	engines = randomised_engines(gt, &prng, &count);
+	if (!engines)
+		return 0;
+
+	for (n = 0; n < count; n++) {
+		struct intel_engine_cs *engine = engines[n];
+		int pass;
+
+		for (pass = 0; pass < 2; pass++) {
+			struct intel_context *ce;
+			unsigned int resets =
+				i915_reset_engine_count(&gt->i915->gpu_error,
+							engine);
+			const u32 *res;
+
+			/* Use a sacrifical context */
+			ce = intel_context_create(engine->kernel_context->gem_context,
+						  engine);
+			if (IS_ERR(ce)) {
+				err = PTR_ERR(ce);
+				goto out;
+			}
+
+			intel_engine_pm_get(engine);
+			res = __live_rc6_ctx(ce);
+			intel_engine_pm_put(engine);
+			intel_context_put(ce);
+			if (IS_ERR(res)) {
+				err = PTR_ERR(res);
+				goto out;
+			}
+
+			intel_gt_retire_requests(gt);
+			intel_gt_pm_wait_for_idle(gt);
+
+			pr_debug("%s: CTX_INFO=%0x\n",
+				 engine->name, READ_ONCE(*res));
+			if (resets !=
+			    i915_reset_engine_count(&gt->i915->gpu_error,
+						    engine)) {
+				pr_err("%s: GPU reset required\n",
+				       engine->name);
+				add_taint_for_CI(TAINT_WARN);
+				err = -EIO;
+				goto out;
+			}
+		}
+	}
+
+out:
+	kfree(engines);
+	return err;
+}
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.h b/drivers/gpu/drm/i915/gt/selftest_rc6.h
new file mode 100644
index 000000000000..230c6b4c7dc0
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.h
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef SELFTEST_RC6_H
+#define SELFTEST_RC6_H
+
+int live_rc6_ctx(void *arg);
+
+#endif /* SELFTEST_RC6_H */
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 11b40bc58e6d..beff59ee9f6f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -39,3 +39,4 @@ selftest(hangcheck, intel_hangcheck_live_selftests)
 selftest(execlists, intel_execlists_live_selftests)
 selftest(guc, intel_guc_live_selftest)
 selftest(perf, i915_perf_live_selftests)
+selftest(late_gt_pm, intel_gt_pm_late_selftests)
-- 
2.24.0

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[Intel-gfx] [PATCH 2/5] drm/i915/selftests: Exercise rc6 handling

[Chris Wilson]

Reading from CTX_INFO upsets rc6, requiring us to detect and prevent
possible rc6 context corruption. Poke at the bear!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c           |   4 +
 drivers/gpu/drm/i915/gt/selftest_gt_pm.c      |  13 ++
 drivers/gpu/drm/i915/gt/selftest_rc6.c        | 139 ++++++++++++++++++
 drivers/gpu/drm/i915/gt/selftest_rc6.h        |  12 ++
 .../drm/i915/selftests/i915_live_selftests.h  |   1 +
 5 files changed, 169 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.c
 create mode 100644 drivers/gpu/drm/i915/gt/selftest_rc6.h

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 602a02d01850..abcf6bbb71ea 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -782,3 +782,7 @@ u64 intel_rc6_residency_us(struct intel_rc6 *rc6, i915_reg_t reg)
 {
 	return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, reg), 1000);
 }
+
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+#include "selftest_rc6.c"
+#endif
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index d1752f15702a..1d5bf93d1258 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -6,6 +6,7 @@
  */
 
 #include "selftest_llc.h"
+#include "selftest_rc6.h"
 
 static int live_gt_resume(void *arg)
 {
@@ -58,3 +59,15 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
 
 	return intel_gt_live_subtests(tests, &i915->gt);
 }
+
+int intel_gt_pm_late_selftests(struct drm_i915_private *i915)
+{
+	static const struct i915_subtest tests[] = {
+		SUBTEST(live_rc6_ctx),
+	};
+
+	if (intel_gt_is_wedged(&i915->gt))
+		return 0;
+
+	return intel_gt_live_subtests(tests, &i915->gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
new file mode 100644
index 000000000000..6b4cb5c7d446
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -0,0 +1,139 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "intel_context.h"
+#include "intel_engine_pm.h"
+#include "intel_gt_requests.h"
+#include "intel_ring.h"
+#include "selftest_rc6.h"
+
+#include "selftests/i915_random.h"
+
+static const u32 *__live_rc6_ctx(struct intel_context *ce)
+{
+	struct i915_request *rq;
+	u32 const *result;
+	u32 cmd;
+	u32 *cs;
+
+	rq = intel_context_create_request(ce);
+	if (IS_ERR(rq))
+		return ERR_CAST(rq);
+
+	cs = intel_ring_begin(rq, 4);
+	if (IS_ERR(cs)) {
+		i915_request_add(rq);
+		return cs;
+	}
+
+	cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
+	if (INTEL_GEN(rq->i915) >= 8)
+		cmd++;
+
+	*cs++ = cmd;
+	*cs++ = 0xA300; /* CTX_INFO */
+	*cs++ = ce->timeline->hwsp_offset + 8;
+	*cs++ = 0;
+	intel_ring_advance(rq, cs);
+
+	result = rq->hwsp_seqno + 2;
+	i915_request_add(rq);
+
+	return result;
+}
+
+static struct intel_engine_cs **
+randomised_engines(struct intel_gt *gt,
+		   struct rnd_state *prng,
+		   unsigned int *count)
+{
+	struct intel_engine_cs *engine, **engines;
+	enum intel_engine_id id;
+	int n;
+
+	n = 0;
+	for_each_engine(engine, gt, id)
+		n++;
+	if (!n)
+		return NULL;
+
+	engines = kmalloc_array(n, sizeof(*engines), GFP_KERNEL);
+	if (!engines)
+		return NULL;
+
+	n = 0;
+	for_each_engine(engine, gt, id)
+		engines[n++] = engine;
+
+	i915_prandom_shuffle(engines, sizeof(*engines), n, prng);
+
+	*count = n;
+	return engines;
+}
+
+int live_rc6_ctx(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs **engines;
+	unsigned int n, count;
+	I915_RND_STATE(prng);
+	int err = 0;
+
+	/* A read of CTX_INFO upsets rc6. Poke the bear! */
+
+	engines = randomised_engines(gt, &prng, &count);
+	if (!engines)
+		return 0;
+
+	for (n = 0; n < count; n++) {
+		struct intel_engine_cs *engine = engines[n];
+		int pass;
+
+		for (pass = 0; pass < 2; pass++) {
+			struct intel_context *ce;
+			unsigned int resets =
+				i915_reset_engine_count(&gt->i915->gpu_error,
+							engine);
+			const u32 *res;
+
+			/* Use a sacrifical context */
+			ce = intel_context_create(engine->kernel_context->gem_context,
+						  engine);
+			if (IS_ERR(ce)) {
+				err = PTR_ERR(ce);
+				goto out;
+			}
+
+			intel_engine_pm_get(engine);
+			res = __live_rc6_ctx(ce);
+			intel_engine_pm_put(engine);
+			intel_context_put(ce);
+			if (IS_ERR(res)) {
+				err = PTR_ERR(res);
+				goto out;
+			}
+
+			intel_gt_retire_requests(gt);
+			intel_gt_pm_wait_for_idle(gt);
+
+			pr_debug("%s: CTX_INFO=%0x\n",
+				 engine->name, READ_ONCE(*res));
+			if (resets !=
+			    i915_reset_engine_count(&gt->i915->gpu_error,
+						    engine)) {
+				pr_err("%s: GPU reset required\n",
+				       engine->name);
+				add_taint_for_CI(TAINT_WARN);
+				err = -EIO;
+				goto out;
+			}
+		}
+	}
+
+out:
+	kfree(engines);
+	return err;
+}
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.h b/drivers/gpu/drm/i915/gt/selftest_rc6.h
new file mode 100644
index 000000000000..230c6b4c7dc0
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.h
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef SELFTEST_RC6_H
+#define SELFTEST_RC6_H
+
+int live_rc6_ctx(void *arg);
+
+#endif /* SELFTEST_RC6_H */
diff --git a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
index 11b40bc58e6d..beff59ee9f6f 100644
--- a/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_live_selftests.h
@@ -39,3 +39,4 @@ selftest(hangcheck, intel_hangcheck_live_selftests)
 selftest(execlists, intel_execlists_live_selftests)
 selftest(guc, intel_guc_live_selftest)
 selftest(perf, i915_perf_live_selftests)
+selftest(late_gt_pm, intel_gt_pm_late_selftests)
-- 
2.24.0

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[PATCH 3/5] drm/i915/selftests: Be explicit in ERR_PTR handling

[Chris Wilson]

When setting up a full GGTT, we expect the next insert to fail with
-ENOSPC. Simplify the use of ERR_PTR to not confuse either the reader or
smatch.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/selftest_rc6.c          | 9 +++++++--
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 4 ++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 6b4cb5c7d446..35516d4699d2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -116,11 +116,16 @@ int live_rc6_ctx(void *arg)
 				goto out;
 			}
 
-			intel_gt_retire_requests(gt);
-			intel_gt_pm_wait_for_idle(gt);
+			if (intel_gt_wait_for_idle(gt, HZ / 5) == -ETIME) {
+				intel_gt_set_wedged(gt);
+				err = -ETIME;
+				goto out;
+			}
 
+			intel_gt_pm_wait_for_idle(gt);
 			pr_debug("%s: CTX_INFO=%0x\n",
 				 engine->name, READ_ONCE(*res));
+
 			if (resets !=
 			    i915_reset_engine_count(&gt->i915->gpu_error,
 						    engine)) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 5f133d177212..06ef88510209 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -198,8 +198,8 @@ static int igt_overcommit(void *arg)
 	quirk_add(obj, &objects);
 
 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
-	if (!IS_ERR(vma) || PTR_ERR(vma) != -ENOSPC) {
-		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR(vma));
+	if (vma != ERR_PTR(-ENOSPC)) {
+		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));
 		err = -EINVAL;
 		goto cleanup;
 	}
-- 
2.24.0

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[Intel-gfx] [PATCH 3/5] drm/i915/selftests: Be explicit in ERR_PTR handling

[Chris Wilson]

When setting up a full GGTT, we expect the next insert to fail with
-ENOSPC. Simplify the use of ERR_PTR to not confuse either the reader or
smatch.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/selftest_rc6.c          | 9 +++++++--
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 4 ++--
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 6b4cb5c7d446..35516d4699d2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -116,11 +116,16 @@ int live_rc6_ctx(void *arg)
 				goto out;
 			}
 
-			intel_gt_retire_requests(gt);
-			intel_gt_pm_wait_for_idle(gt);
+			if (intel_gt_wait_for_idle(gt, HZ / 5) == -ETIME) {
+				intel_gt_set_wedged(gt);
+				err = -ETIME;
+				goto out;
+			}
 
+			intel_gt_pm_wait_for_idle(gt);
 			pr_debug("%s: CTX_INFO=%0x\n",
 				 engine->name, READ_ONCE(*res));
+
 			if (resets !=
 			    i915_reset_engine_count(&gt->i915->gpu_error,
 						    engine)) {
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 5f133d177212..06ef88510209 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -198,8 +198,8 @@ static int igt_overcommit(void *arg)
 	quirk_add(obj, &objects);
 
 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
-	if (!IS_ERR(vma) || PTR_ERR(vma) != -ENOSPC) {
-		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR(vma));
+	if (vma != ERR_PTR(-ENOSPC)) {
+		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));
 		err = -EINVAL;
 		goto cleanup;
 	}
-- 
2.24.0

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[PATCH 4/5] drm/i915/selftests: Exercise long preemption chains

[Chris Wilson]

Verify that we can execute a long chain of dependent requests from
userspace, each one slightly more important than the last.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_lrc.c | 196 +++++++++++++++++++++++++
 1 file changed, 196 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d1ed3c0f851c..2ef03a8efa28 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1915,6 +1915,201 @@ static int live_chain_preempt(void *arg)
 	goto err_client_lo;
 }
 
+static int create_gang(struct intel_engine_cs *engine,
+		       struct i915_request **prev)
+{
+	struct drm_i915_gem_object *obj;
+	struct intel_context *ce;
+	struct i915_request *rq;
+	struct i915_vma *vma;
+	u32 *cs;
+	int err;
+
+	ce = intel_context_create(engine->kernel_context->gem_context, engine);
+	if (IS_ERR(ce))
+		return PTR_ERR(ce);
+
+	obj = i915_gem_object_create_internal(engine->i915, 4096);
+	if (IS_ERR(obj)) {
+		err = PTR_ERR(obj);
+		goto err_ce;
+	}
+
+	vma = i915_vma_instance(obj, ce->vm, NULL);
+	if (IS_ERR(vma)) {
+		err = PTR_ERR(vma);
+		goto err_obj;
+	}
+
+	err = i915_vma_pin(vma, 0, 0, PIN_USER);
+	if (err)
+		goto err_obj;
+
+	cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
+	if (IS_ERR(cs))
+		goto err_obj;
+
+	/* Semaphore target: spin until zero */
+	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+
+	*cs++ = MI_SEMAPHORE_WAIT |
+		MI_SEMAPHORE_POLL |
+		MI_SEMAPHORE_SAD_EQ_SDD;
+	*cs++ = 0;
+	*cs++ = lower_32_bits(vma->node.start);
+	*cs++ = upper_32_bits(vma->node.start);
+
+	if (*prev) {
+		u64 offset = (*prev)->batch->node.start;
+
+		/* Terminate the spinner in the next lower priority batch. */
+		*cs++ = MI_STORE_DWORD_IMM_GEN4;
+		*cs++ = lower_32_bits(offset);
+		*cs++ = upper_32_bits(offset);
+		*cs++ = 0;
+	}
+
+	*cs++ = MI_BATCH_BUFFER_END;
+	i915_gem_object_flush_map(obj);
+	i915_gem_object_unpin_map(obj);
+
+	rq = intel_context_create_request(ce);
+	if (IS_ERR(rq))
+		goto err_obj;
+
+	rq->batch = vma;
+	i915_request_get(rq);
+
+	i915_vma_lock(vma);
+	err = i915_request_await_object(rq, vma->obj, false);
+	if (!err)
+		err = i915_vma_move_to_active(vma, rq, 0);
+	if (!err)
+		err = rq->engine->emit_bb_start(rq,
+						vma->node.start,
+						PAGE_SIZE, 0);
+	i915_vma_unlock(vma);
+	i915_request_add(rq);
+	if (err)
+		goto err_rq;
+
+	i915_gem_object_put(obj);
+	intel_context_put(ce);
+
+	rq->client_link.next = &(*prev)->client_link;
+	*prev = rq;
+	return 0;
+
+err_rq:
+	i915_request_put(rq);
+err_obj:
+	i915_gem_object_put(obj);
+err_ce:
+	intel_context_put(ce);
+	return err;
+}
+
+static int live_preempt_gang(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
+		return 0;
+
+	/*
+	 * Build as long a chain of preempters as we can, with each
+	 * request higher priority than the last. Once we are ready, we release
+	 * the last batch which then precolates down the chain, each releasing
+	 * the next oldest in turn. The intent is to simply push as hard as we
+	 * can with the number of preemptions, trying to exceed narrow HW
+	 * limits. At a minimum, we insist that we can sort all the user
+	 * high priority levels into execution order.
+	 */
+
+	for_each_engine(engine, gt, id) {
+		struct i915_request *rq = NULL;
+		struct igt_live_test t;
+		IGT_TIMEOUT(end_time);
+		int prio = 0;
+		int err = 0;
+		u32 *cs;
+
+		if (!intel_engine_has_preemption(engine))
+			continue;
+
+		if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))
+			return -EIO;
+
+		do {
+			struct i915_sched_attr attr = {
+				.priority = I915_USER_PRIORITY(prio++),
+			};
+
+			err = create_gang(engine, &rq);
+			if (err)
+				break;
+
+			/* Submit each spinner at increasing priority */
+			engine->schedule(rq, &attr);
+
+			if (prio <= I915_PRIORITY_MAX)
+				continue;
+
+			if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT))
+				break;
+
+			if (__igt_timeout(end_time, NULL))
+				break;
+		} while (1);
+		pr_debug("%s: Preempt chain of %d requests\n",
+			 engine->name, prio);
+
+		/*
+		 * Such that the last spinner is the higher priority and
+		 * should execute first. When that spinner completes,
+		 * it will terminate the next lowest spinner until there
+		 * are no more spinners and the gang is complete.
+		 */
+		cs = i915_gem_object_pin_map(rq->batch->obj, I915_MAP_WC);
+		if (!IS_ERR(cs)) {
+			*cs = 0;
+			i915_gem_object_unpin_map(rq->batch->obj);
+		} else {
+			err = PTR_ERR(cs);
+			intel_gt_set_wedged(gt);
+		}
+
+		while (rq) { /* wait for each rq from highest to lowest prio */
+			struct i915_request *n =
+				list_next_entry(rq, client_link);
+
+			if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0) {
+				struct drm_printer p =
+					drm_info_printer(engine->i915->drm.dev);
+
+				pr_err("Failed to flush chain of %d requests, at %d\n",
+				       prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT);
+				intel_engine_dump(engine, &p,
+						  "%s\n", engine->name);
+
+				err = -ETIME;
+			}
+
+			i915_request_put(rq);
+			rq = n;
+		}
+
+		if (igt_live_test_end(&t))
+			err = -EIO;
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 static int live_preempt_hang(void *arg)
 {
 	struct intel_gt *gt = arg;
@@ -3028,6 +3223,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
 		SUBTEST(live_suppress_self_preempt),
 		SUBTEST(live_suppress_wait_preempt),
 		SUBTEST(live_chain_preempt),
+		SUBTEST(live_preempt_gang),
 		SUBTEST(live_preempt_hang),
 		SUBTEST(live_preempt_timeout),
 		SUBTEST(live_preempt_smoke),
-- 
2.24.0

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[Intel-gfx] [PATCH 4/5] drm/i915/selftests: Exercise long preemption chains

[Chris Wilson]

Verify that we can execute a long chain of dependent requests from
userspace, each one slightly more important than the last.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gt/selftest_lrc.c | 196 +++++++++++++++++++++++++
 1 file changed, 196 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d1ed3c0f851c..2ef03a8efa28 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1915,6 +1915,201 @@ static int live_chain_preempt(void *arg)
 	goto err_client_lo;
 }
 
+static int create_gang(struct intel_engine_cs *engine,
+		       struct i915_request **prev)
+{
+	struct drm_i915_gem_object *obj;
+	struct intel_context *ce;
+	struct i915_request *rq;
+	struct i915_vma *vma;
+	u32 *cs;
+	int err;
+
+	ce = intel_context_create(engine->kernel_context->gem_context, engine);
+	if (IS_ERR(ce))
+		return PTR_ERR(ce);
+
+	obj = i915_gem_object_create_internal(engine->i915, 4096);
+	if (IS_ERR(obj)) {
+		err = PTR_ERR(obj);
+		goto err_ce;
+	}
+
+	vma = i915_vma_instance(obj, ce->vm, NULL);
+	if (IS_ERR(vma)) {
+		err = PTR_ERR(vma);
+		goto err_obj;
+	}
+
+	err = i915_vma_pin(vma, 0, 0, PIN_USER);
+	if (err)
+		goto err_obj;
+
+	cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
+	if (IS_ERR(cs))
+		goto err_obj;
+
+	/* Semaphore target: spin until zero */
+	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+
+	*cs++ = MI_SEMAPHORE_WAIT |
+		MI_SEMAPHORE_POLL |
+		MI_SEMAPHORE_SAD_EQ_SDD;
+	*cs++ = 0;
+	*cs++ = lower_32_bits(vma->node.start);
+	*cs++ = upper_32_bits(vma->node.start);
+
+	if (*prev) {
+		u64 offset = (*prev)->batch->node.start;
+
+		/* Terminate the spinner in the next lower priority batch. */
+		*cs++ = MI_STORE_DWORD_IMM_GEN4;
+		*cs++ = lower_32_bits(offset);
+		*cs++ = upper_32_bits(offset);
+		*cs++ = 0;
+	}
+
+	*cs++ = MI_BATCH_BUFFER_END;
+	i915_gem_object_flush_map(obj);
+	i915_gem_object_unpin_map(obj);
+
+	rq = intel_context_create_request(ce);
+	if (IS_ERR(rq))
+		goto err_obj;
+
+	rq->batch = vma;
+	i915_request_get(rq);
+
+	i915_vma_lock(vma);
+	err = i915_request_await_object(rq, vma->obj, false);
+	if (!err)
+		err = i915_vma_move_to_active(vma, rq, 0);
+	if (!err)
+		err = rq->engine->emit_bb_start(rq,
+						vma->node.start,
+						PAGE_SIZE, 0);
+	i915_vma_unlock(vma);
+	i915_request_add(rq);
+	if (err)
+		goto err_rq;
+
+	i915_gem_object_put(obj);
+	intel_context_put(ce);
+
+	rq->client_link.next = &(*prev)->client_link;
+	*prev = rq;
+	return 0;
+
+err_rq:
+	i915_request_put(rq);
+err_obj:
+	i915_gem_object_put(obj);
+err_ce:
+	intel_context_put(ce);
+	return err;
+}
+
+static int live_preempt_gang(void *arg)
+{
+	struct intel_gt *gt = arg;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+
+	if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
+		return 0;
+
+	/*
+	 * Build as long a chain of preempters as we can, with each
+	 * request higher priority than the last. Once we are ready, we release
+	 * the last batch which then precolates down the chain, each releasing
+	 * the next oldest in turn. The intent is to simply push as hard as we
+	 * can with the number of preemptions, trying to exceed narrow HW
+	 * limits. At a minimum, we insist that we can sort all the user
+	 * high priority levels into execution order.
+	 */
+
+	for_each_engine(engine, gt, id) {
+		struct i915_request *rq = NULL;
+		struct igt_live_test t;
+		IGT_TIMEOUT(end_time);
+		int prio = 0;
+		int err = 0;
+		u32 *cs;
+
+		if (!intel_engine_has_preemption(engine))
+			continue;
+
+		if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))
+			return -EIO;
+
+		do {
+			struct i915_sched_attr attr = {
+				.priority = I915_USER_PRIORITY(prio++),
+			};
+
+			err = create_gang(engine, &rq);
+			if (err)
+				break;
+
+			/* Submit each spinner at increasing priority */
+			engine->schedule(rq, &attr);
+
+			if (prio <= I915_PRIORITY_MAX)
+				continue;
+
+			if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT))
+				break;
+
+			if (__igt_timeout(end_time, NULL))
+				break;
+		} while (1);
+		pr_debug("%s: Preempt chain of %d requests\n",
+			 engine->name, prio);
+
+		/*
+		 * Such that the last spinner is the higher priority and
+		 * should execute first. When that spinner completes,
+		 * it will terminate the next lowest spinner until there
+		 * are no more spinners and the gang is complete.
+		 */
+		cs = i915_gem_object_pin_map(rq->batch->obj, I915_MAP_WC);
+		if (!IS_ERR(cs)) {
+			*cs = 0;
+			i915_gem_object_unpin_map(rq->batch->obj);
+		} else {
+			err = PTR_ERR(cs);
+			intel_gt_set_wedged(gt);
+		}
+
+		while (rq) { /* wait for each rq from highest to lowest prio */
+			struct i915_request *n =
+				list_next_entry(rq, client_link);
+
+			if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0) {
+				struct drm_printer p =
+					drm_info_printer(engine->i915->drm.dev);
+
+				pr_err("Failed to flush chain of %d requests, at %d\n",
+				       prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT);
+				intel_engine_dump(engine, &p,
+						  "%s\n", engine->name);
+
+				err = -ETIME;
+			}
+
+			i915_request_put(rq);
+			rq = n;
+		}
+
+		if (igt_live_test_end(&t))
+			err = -EIO;
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 static int live_preempt_hang(void *arg)
 {
 	struct intel_gt *gt = arg;
@@ -3028,6 +3223,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
 		SUBTEST(live_suppress_self_preempt),
 		SUBTEST(live_suppress_wait_preempt),
 		SUBTEST(live_chain_preempt),
+		SUBTEST(live_preempt_gang),
 		SUBTEST(live_preempt_hang),
 		SUBTEST(live_preempt_timeout),
 		SUBTEST(live_preempt_smoke),
-- 
2.24.0

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[PATCH 5/5] drm/i915/gem: Silence sparse for RCU protection inside the constructor

[Chris Wilson]

Inside the constructor, while cloning, we need to replace the
dst->engines. Having forgotten that dst->engines is marked as RCU
protected, we need to add the appropriate annotations to make sparse
happy.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 1284f47303fa..6f1e6181f67a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2009,7 +2009,8 @@ static int clone_engines(struct i915_gem_context *dst,
 	user_engines = i915_gem_context_user_engines(src);
 	i915_gem_context_unlock_engines(src);
 
-	free_engines(dst->engines);
+	/* Serialised by constructor */
+	free_engines(__context_engines_static(dst));
 	RCU_INIT_POINTER(dst->engines, clone);
 	if (user_engines)
 		i915_gem_context_set_user_engines(dst);
@@ -2044,7 +2045,8 @@ static int clone_sseu(struct i915_gem_context *dst,
 	unsigned long n;
 	int err;
 
-	clone = dst->engines; /* no locking required; sole access */
+	/* no locking required; sole access under constructor*/
+	clone = __context_engines_static(dst);
 	if (e->num_engines != clone->num_engines) {
 		err = -EINVAL;
 		goto unlock;
-- 
2.24.0

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[Intel-gfx] [PATCH 5/5] drm/i915/gem: Silence sparse for RCU protection inside the constructor

[Chris Wilson]

Inside the constructor, while cloning, we need to replace the
dst->engines. Having forgotten that dst->engines is marked as RCU
protected, we need to add the appropriate annotations to make sparse
happy.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 1284f47303fa..6f1e6181f67a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -2009,7 +2009,8 @@ static int clone_engines(struct i915_gem_context *dst,
 	user_engines = i915_gem_context_user_engines(src);
 	i915_gem_context_unlock_engines(src);
 
-	free_engines(dst->engines);
+	/* Serialised by constructor */
+	free_engines(__context_engines_static(dst));
 	RCU_INIT_POINTER(dst->engines, clone);
 	if (user_engines)
 		i915_gem_context_set_user_engines(dst);
@@ -2044,7 +2045,8 @@ static int clone_sseu(struct i915_gem_context *dst,
 	unsigned long n;
 	int err;
 
-	clone = dst->engines; /* no locking required; sole access */
+	/* no locking required; sole access under constructor*/
+	clone = __context_engines_static(dst);
 	if (e->num_engines != clone->num_engines) {
 		err = -EINVAL;
 		goto unlock;
-- 
2.24.0

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
URL   : https://patchwork.freedesktop.org/series/69497/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5de2752aebd8 drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
bce7ebcaceb6 drm/i915/selftests: Exercise rc6 handling
-:54: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

-:59: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#59: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:1:
+/*

-:60: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#60: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:2:
+ * SPDX-License-Identifier: MIT

-:140: WARNING:LINE_SPACING: Missing a blank line after declarations
#140: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:82:
+	unsigned int n, count;
+	I915_RND_STATE(prng);

-:204: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#204: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.h:1:
+/*

-:205: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#205: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.h:2:
+ * SPDX-License-Identifier: MIT

total: 0 errors, 6 warnings, 0 checks, 184 lines checked
c24fd23d495d drm/i915/selftests: Be explicit in ERR_PTR handling
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")

-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")'
#11: 
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")

-:48: WARNING:LONG_LINE: line over 100 characters
#48: FILE: drivers/gpu/drm/i915/selftests/i915_gem_evict.c:202:
+		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));

total: 1 errors, 2 warnings, 0 checks, 28 lines checked
597216b663ff drm/i915/selftests: Exercise long preemption chains
-:136: WARNING:LINE_SPACING: Missing a blank line after declarations
#136: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:2034:
+		struct igt_live_test t;
+		IGT_TIMEOUT(end_time);

total: 0 errors, 1 warnings, 0 checks, 208 lines checked
c4925741da30 drm/i915/gem: Silence sparse for RCU protection inside the constructor
-:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not the tool that found it
#4: 
Subject: [PATCH] drm/i915/gem: Silence sparse for RCU protection inside the

total: 0 errors, 1 warnings, 0 checks, 18 lines checked

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
URL   : https://patchwork.freedesktop.org/series/69497/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5de2752aebd8 drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
bce7ebcaceb6 drm/i915/selftests: Exercise rc6 handling
-:54: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#54: 
new file mode 100644

-:59: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#59: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:1:
+/*

-:60: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#60: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:2:
+ * SPDX-License-Identifier: MIT

-:140: WARNING:LINE_SPACING: Missing a blank line after declarations
#140: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.c:82:
+	unsigned int n, count;
+	I915_RND_STATE(prng);

-:204: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#204: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.h:1:
+/*

-:205: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#205: FILE: drivers/gpu/drm/i915/gt/selftest_rc6.h:2:
+ * SPDX-License-Identifier: MIT

total: 0 errors, 6 warnings, 0 checks, 184 lines checked
c24fd23d495d drm/i915/selftests: Be explicit in ERR_PTR handling
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")

-:11: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")'
#11: 
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")

-:48: WARNING:LONG_LINE: line over 100 characters
#48: FILE: drivers/gpu/drm/i915/selftests/i915_gem_evict.c:202:
+		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));

total: 1 errors, 2 warnings, 0 checks, 28 lines checked
597216b663ff drm/i915/selftests: Exercise long preemption chains
-:136: WARNING:LINE_SPACING: Missing a blank line after declarations
#136: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:2034:
+		struct igt_live_test t;
+		IGT_TIMEOUT(end_time);

total: 0 errors, 1 warnings, 0 checks, 208 lines checked
c4925741da30 drm/i915/gem: Silence sparse for RCU protection inside the constructor
-:4: WARNING:EMAIL_SUBJECT: A patch subject line should describe the change not the tool that found it
#4: 
Subject: [PATCH] drm/i915/gem: Silence sparse for RCU protection inside the

total: 0 errors, 1 warnings, 0 checks, 18 lines checked

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✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
URL   : https://patchwork.freedesktop.org/series/69497/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7347 -> Patchwork_15270
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15270:

### IGT changes ###

#### Possible regressions ####

  * {igt@i915_selftest@live_late_gt_pm} (NEW):
    - fi-hsw-4770r:       NOTRUN -> [DMESG-FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-hsw-4770r/igt@i915_selftest@live_late_gt_pm.html
    - fi-hsw-4770:        NOTRUN -> [DMESG-FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-hsw-4770/igt@i915_selftest@live_late_gt_pm.html
    - fi-ilk-650:         NOTRUN -> [DMESG-FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-ilk-650/igt@i915_selftest@live_late_gt_pm.html
    - fi-elk-e7500:       NOTRUN -> [DMESG-FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-elk-e7500/igt@i915_selftest@live_late_gt_pm.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7347 and Patchwork_15270:

### New IGT tests (1) ###

  * igt@i915_selftest@live_late_gt_pm:
    - Statuses : 4 dmesg-fail(s) 34 pass(s)
    - Exec time: [0.41, 1.99] s

  

Known issues
------------

  Here are the changes found in Patchwork_15270 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [PASS][5] -> [DMESG-WARN][6] ([fdo#106107])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-icl-u3/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-icl-u3/igt@i915_module_load@reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [DMESG-WARN][9] ([fdo#112261]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@kms_flip@basic-plain-flip:
    - fi-skl-6770hq:      [DMESG-WARN][11] ([fdo#105541]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-skl-6770hq/igt@kms_flip@basic-plain-flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-skl-6770hq/igt@kms_flip@basic-plain-flip.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-guc:         [FAIL][13] ([fdo#103167]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-skl-6770hq:      [WARN][15] ([fdo#112252]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [SKIP][17] ([fdo#109271]) -> [FAIL][18] ([fdo#112223])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112223]: https://bugs.freedesktop.org/show_bug.cgi?id=112223
  [fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (49 -> 43)
------------------------------

  Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-byt-clapper fi-skl-6700k2 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7347 -> Patchwork_15270

  CI-20190529: 20190529
  CI_DRM_7347: 3855b3a1d547a91408fe3d0f6b69a4cae0b04ed7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5286: 5343ca6ad8fac39fe4d468f771af72c968404bea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15270: c4925741da30f6a7b7ef09e225a10764c05dc451 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c4925741da30 drm/i915/gem: Silence sparse for RCU protection inside the constructor
597216b663ff drm/i915/selftests: Exercise long preemption chains
c24fd23d495d drm/i915/selftests: Be explicit in ERR_PTR handling
bce7ebcaceb6 drm/i915/selftests: Exercise rc6 handling
5de2752aebd8 drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/index.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
URL   : https://patchwork.freedesktop.org/series/69497/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7347 -> Patchwork_15270
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15270:

### IGT changes ###

#### Possible regressions ####

  * {igt@i915_selftest@live_late_gt_pm} (NEW):
    - fi-hsw-4770r:       NOTRUN -> [DMESG-FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-hsw-4770r/igt@i915_selftest@live_late_gt_pm.html
    - fi-hsw-4770:        NOTRUN -> [DMESG-FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-hsw-4770/igt@i915_selftest@live_late_gt_pm.html
    - fi-ilk-650:         NOTRUN -> [DMESG-FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-ilk-650/igt@i915_selftest@live_late_gt_pm.html
    - fi-elk-e7500:       NOTRUN -> [DMESG-FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-elk-e7500/igt@i915_selftest@live_late_gt_pm.html

  
New tests
---------

  New tests have been introduced between CI_DRM_7347 and Patchwork_15270:

### New IGT tests (1) ###

  * igt@i915_selftest@live_late_gt_pm:
    - Statuses : 4 dmesg-fail(s) 34 pass(s)
    - Exec time: [0.41, 1.99] s

  

Known issues
------------

  Here are the changes found in Patchwork_15270 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [PASS][5] -> [DMESG-WARN][6] ([fdo#106107])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-icl-u3/igt@i915_module_load@reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-icl-u3/igt@i915_module_load@reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-no-display:
    - fi-skl-lmem:        [DMESG-WARN][9] ([fdo#112261]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-skl-lmem/igt@i915_module_load@reload-no-display.html

  * igt@kms_flip@basic-plain-flip:
    - fi-skl-6770hq:      [DMESG-WARN][11] ([fdo#105541]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-skl-6770hq/igt@kms_flip@basic-plain-flip.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-skl-6770hq/igt@kms_flip@basic-plain-flip.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-guc:         [FAIL][13] ([fdo#103167]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-skl-6770hq:      [WARN][15] ([fdo#112252]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [SKIP][17] ([fdo#109271]) -> [FAIL][18] ([fdo#112223])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7347/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112223]: https://bugs.freedesktop.org/show_bug.cgi?id=112223
  [fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261


Participating hosts (49 -> 43)
------------------------------

  Missing    (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-bsw-kefka fi-byt-clapper fi-skl-6700k2 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7347 -> Patchwork_15270

  CI-20190529: 20190529
  CI_DRM_7347: 3855b3a1d547a91408fe3d0f6b69a4cae0b04ed7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5286: 5343ca6ad8fac39fe4d468f771af72c968404bea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15270: c4925741da30f6a7b7ef09e225a10764c05dc451 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

c4925741da30 drm/i915/gem: Silence sparse for RCU protection inside the constructor
597216b663ff drm/i915/selftests: Exercise long preemption chains
c24fd23d495d drm/i915/selftests: Be explicit in ERR_PTR handling
bce7ebcaceb6 drm/i915/selftests: Exercise rc6 handling
5de2752aebd8 drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15270/index.html
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Re: [PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> Our callers fall into two categories, those passing timeout=0 who just
> want to flush request retirements and those passing a timeout that need
> to wait for submission completion (e.g. intel_gt_wait_for_idle()).
> Currently, we only wait for a snapshot of timelines at the start of the
> wait (but there was an expection that new requests would cause timelines

expectation? exception?

> to appear at the end). However, our callers, such as
> intel_gt_wait_for_idle() before suspend, do require us to wait for the
> power management requests emitted by retirement as well. If we don't,
> then it takes an extra second or two for the background worker to flush
> the queue and mark the GT as idle.

So with this change wait_for_idle waits for the kernel context to get 
retired as well. And you say that's faster by a second or two? Which 
flush gets so much slower, I mean from where, if we don't wait here?

Regards,

Tvrtko

> 
> Fixes: 7e8057626640 ("drm/i915: Drop struct_mutex from around i915_retire_requests()")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt_requests.c | 11 +++--------
>   1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> index b73229a84d85..ccbddddbbd52 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> @@ -33,7 +33,6 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   {
>   	struct intel_gt_timelines *timelines = &gt->timelines;
>   	struct intel_timeline *tl, *tn;
> -	unsigned long active_count = 0;
>   	unsigned long flags;
>   	bool interruptible;
>   	LIST_HEAD(free);
> @@ -46,10 +45,8 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   
>   	spin_lock_irqsave(&timelines->lock, flags);
>   	list_for_each_entry_safe(tl, tn, &timelines->active_list, link) {
> -		if (!mutex_trylock(&tl->mutex)) {
> -			active_count++; /* report busy to caller, try again? */
> +		if (!mutex_trylock(&tl->mutex))
>   			continue;
> -		}
>   
>   		intel_timeline_get(tl);
>   		GEM_BUG_ON(!tl->active_count);
> @@ -74,9 +71,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   
>   		/* Resume iteration after dropping lock */
>   		list_safe_reset_next(tl, tn, link);
> -		if (--tl->active_count)
> -			active_count += !!rcu_access_pointer(tl->last_request.fence);
> -		else
> +		if (!--tl->active_count)
>   			list_del(&tl->link);
>   
>   		mutex_unlock(&tl->mutex);
> @@ -92,7 +87,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   	list_for_each_entry_safe(tl, tn, &free, link)
>   		__intel_timeline_free(&tl->kref);
>   
> -	return active_count ? timeout : 0;
> +	return list_empty(&timelines->active_list) ? 0 : timeout;
>   }
>   
>   int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
> 
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> Our callers fall into two categories, those passing timeout=0 who just
> want to flush request retirements and those passing a timeout that need
> to wait for submission completion (e.g. intel_gt_wait_for_idle()).
> Currently, we only wait for a snapshot of timelines at the start of the
> wait (but there was an expection that new requests would cause timelines

expectation? exception?

> to appear at the end). However, our callers, such as
> intel_gt_wait_for_idle() before suspend, do require us to wait for the
> power management requests emitted by retirement as well. If we don't,
> then it takes an extra second or two for the background worker to flush
> the queue and mark the GT as idle.

So with this change wait_for_idle waits for the kernel context to get 
retired as well. And you say that's faster by a second or two? Which 
flush gets so much slower, I mean from where, if we don't wait here?

Regards,

Tvrtko

> 
> Fixes: 7e8057626640 ("drm/i915: Drop struct_mutex from around i915_retire_requests()")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_gt_requests.c | 11 +++--------
>   1 file changed, 3 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> index b73229a84d85..ccbddddbbd52 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> @@ -33,7 +33,6 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   {
>   	struct intel_gt_timelines *timelines = &gt->timelines;
>   	struct intel_timeline *tl, *tn;
> -	unsigned long active_count = 0;
>   	unsigned long flags;
>   	bool interruptible;
>   	LIST_HEAD(free);
> @@ -46,10 +45,8 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   
>   	spin_lock_irqsave(&timelines->lock, flags);
>   	list_for_each_entry_safe(tl, tn, &timelines->active_list, link) {
> -		if (!mutex_trylock(&tl->mutex)) {
> -			active_count++; /* report busy to caller, try again? */
> +		if (!mutex_trylock(&tl->mutex))
>   			continue;
> -		}
>   
>   		intel_timeline_get(tl);
>   		GEM_BUG_ON(!tl->active_count);
> @@ -74,9 +71,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   
>   		/* Resume iteration after dropping lock */
>   		list_safe_reset_next(tl, tn, link);
> -		if (--tl->active_count)
> -			active_count += !!rcu_access_pointer(tl->last_request.fence);
> -		else
> +		if (!--tl->active_count)
>   			list_del(&tl->link);
>   
>   		mutex_unlock(&tl->mutex);
> @@ -92,7 +87,7 @@ long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
>   	list_for_each_entry_safe(tl, tn, &free, link)
>   		__intel_timeline_free(&tl->kref);
>   
> -	return active_count ? timeout : 0;
> +	return list_empty(&timelines->active_list) ? 0 : timeout;
>   }
>   
>   int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
> 
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Re: [PATCH 3/5] drm/i915/selftests: Be explicit in ERR_PTR handling

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> When setting up a full GGTT, we expect the next insert to fail with
> -ENOSPC. Simplify the use of ERR_PTR to not confuse either the reader or
> smatch.
> 
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/selftest_rc6.c          | 9 +++++++--
>   drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 4 ++--
>   2 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 6b4cb5c7d446..35516d4699d2 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -116,11 +116,16 @@ int live_rc6_ctx(void *arg)
>   				goto out;
>   			}
>   
> -			intel_gt_retire_requests(gt);
> -			intel_gt_pm_wait_for_idle(gt);
> +			if (intel_gt_wait_for_idle(gt, HZ / 5) == -ETIME) {
> +				intel_gt_set_wedged(gt);
> +				err = -ETIME;
> +				goto out;
> +			}
>   
> +			intel_gt_pm_wait_for_idle(gt);
>   			pr_debug("%s: CTX_INFO=%0x\n",
>   				 engine->name, READ_ONCE(*res));
> +

This hunk does not relate to the fix.

Regards,

Tvrtko

>   			if (resets !=
>   			    i915_reset_engine_count(&gt->i915->gpu_error,
>   						    engine)) {
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> index 5f133d177212..06ef88510209 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> @@ -198,8 +198,8 @@ static int igt_overcommit(void *arg)
>   	quirk_add(obj, &objects);
>   
>   	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> -	if (!IS_ERR(vma) || PTR_ERR(vma) != -ENOSPC) {
> -		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR(vma));
> +	if (vma != ERR_PTR(-ENOSPC)) {
> +		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));
>   		err = -EINVAL;
>   		goto cleanup;
>   	}
> 
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Re: [Intel-gfx] [PATCH 3/5] drm/i915/selftests: Be explicit in ERR_PTR handling

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> When setting up a full GGTT, we expect the next insert to fail with
> -ENOSPC. Simplify the use of ERR_PTR to not confuse either the reader or
> smatch.
> 
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/selftest_rc6.c          | 9 +++++++--
>   drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 4 ++--
>   2 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 6b4cb5c7d446..35516d4699d2 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -116,11 +116,16 @@ int live_rc6_ctx(void *arg)
>   				goto out;
>   			}
>   
> -			intel_gt_retire_requests(gt);
> -			intel_gt_pm_wait_for_idle(gt);
> +			if (intel_gt_wait_for_idle(gt, HZ / 5) == -ETIME) {
> +				intel_gt_set_wedged(gt);
> +				err = -ETIME;
> +				goto out;
> +			}
>   
> +			intel_gt_pm_wait_for_idle(gt);
>   			pr_debug("%s: CTX_INFO=%0x\n",
>   				 engine->name, READ_ONCE(*res));
> +

This hunk does not relate to the fix.

Regards,

Tvrtko

>   			if (resets !=
>   			    i915_reset_engine_count(&gt->i915->gpu_error,
>   						    engine)) {
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> index 5f133d177212..06ef88510209 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
> @@ -198,8 +198,8 @@ static int igt_overcommit(void *arg)
>   	quirk_add(obj, &objects);
>   
>   	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
> -	if (!IS_ERR(vma) || PTR_ERR(vma) != -ENOSPC) {
> -		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR(vma));
> +	if (vma != ERR_PTR(-ENOSPC)) {
> +		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));
>   		err = -EINVAL;
>   		goto cleanup;
>   	}
> 
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Re: [PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-11-15 12:45:52)
> 
> On 14/11/2019 22:57, Chris Wilson wrote:
> > Our callers fall into two categories, those passing timeout=0 who just
> > want to flush request retirements and those passing a timeout that need
> > to wait for submission completion (e.g. intel_gt_wait_for_idle()).
> > Currently, we only wait for a snapshot of timelines at the start of the
> > wait (but there was an expection that new requests would cause timelines
> 
> expectation? exception?
expectation

> > to appear at the end). However, our callers, such as
> > intel_gt_wait_for_idle() before suspend, do require us to wait for the
> > power management requests emitted by retirement as well. If we don't,
> > then it takes an extra second or two for the background worker to flush
> > the queue and mark the GT as idle.
> 
> So with this change wait_for_idle waits for the kernel context to get 
> retired as well. And you say that's faster by a second or two? Which 
> flush gets so much slower, I mean from where, if we don't wait here?

intel_gt_pm_wait_for_idle() (so i915_gem_suspend, and selftests that
exercise those same paths) then has to wait for the background retire
worker to flush the final requests and drop the wakeref.
-Chris
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Re: [Intel-gfx] [PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-11-15 12:45:52)
> 
> On 14/11/2019 22:57, Chris Wilson wrote:
> > Our callers fall into two categories, those passing timeout=0 who just
> > want to flush request retirements and those passing a timeout that need
> > to wait for submission completion (e.g. intel_gt_wait_for_idle()).
> > Currently, we only wait for a snapshot of timelines at the start of the
> > wait (but there was an expection that new requests would cause timelines
> 
> expectation? exception?
expectation

> > to appear at the end). However, our callers, such as
> > intel_gt_wait_for_idle() before suspend, do require us to wait for the
> > power management requests emitted by retirement as well. If we don't,
> > then it takes an extra second or two for the background worker to flush
> > the queue and mark the GT as idle.
> 
> So with this change wait_for_idle waits for the kernel context to get 
> retired as well. And you say that's faster by a second or two? Which 
> flush gets so much slower, I mean from where, if we don't wait here?

intel_gt_pm_wait_for_idle() (so i915_gem_suspend, and selftests that
exercise those same paths) then has to wait for the background retire
worker to flush the final requests and drop the wakeref.
-Chris
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Re: [PATCH 4/5] drm/i915/selftests: Exercise long preemption chains

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> Verify that we can execute a long chain of dependent requests from
> userspace, each one slightly more important than the last.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/selftest_lrc.c | 196 +++++++++++++++++++++++++
>   1 file changed, 196 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index d1ed3c0f851c..2ef03a8efa28 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -1915,6 +1915,201 @@ static int live_chain_preempt(void *arg)
>   	goto err_client_lo;
>   }
>   
> +static int create_gang(struct intel_engine_cs *engine,
> +		       struct i915_request **prev)
> +{
> +	struct drm_i915_gem_object *obj;
> +	struct intel_context *ce;
> +	struct i915_request *rq;
> +	struct i915_vma *vma;
> +	u32 *cs;
> +	int err;
> +
> +	ce = intel_context_create(engine->kernel_context->gem_context, engine);
> +	if (IS_ERR(ce))
> +		return PTR_ERR(ce);
> +
> +	obj = i915_gem_object_create_internal(engine->i915, 4096);
> +	if (IS_ERR(obj)) {
> +		err = PTR_ERR(obj);
> +		goto err_ce;
> +	}
> +
> +	vma = i915_vma_instance(obj, ce->vm, NULL);
> +	if (IS_ERR(vma)) {
> +		err = PTR_ERR(vma);
> +		goto err_obj;
> +	}
> +
> +	err = i915_vma_pin(vma, 0, 0, PIN_USER);
> +	if (err)
> +		goto err_obj;
> +
> +	cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
> +	if (IS_ERR(cs))
> +		goto err_obj;
> +
> +	/* Semaphore target: spin until zero */
> +	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> +
> +	*cs++ = MI_SEMAPHORE_WAIT |
> +		MI_SEMAPHORE_POLL |
> +		MI_SEMAPHORE_SAD_EQ_SDD;
> +	*cs++ = 0;
> +	*cs++ = lower_32_bits(vma->node.start);
> +	*cs++ = upper_32_bits(vma->node.start);
> +
> +	if (*prev) {
> +		u64 offset = (*prev)->batch->node.start;
> +
> +		/* Terminate the spinner in the next lower priority batch. */
> +		*cs++ = MI_STORE_DWORD_IMM_GEN4;
> +		*cs++ = lower_32_bits(offset);
> +		*cs++ = upper_32_bits(offset);
> +		*cs++ = 0;
> +	}
> +
> +	*cs++ = MI_BATCH_BUFFER_END;
> +	i915_gem_object_flush_map(obj);
> +	i915_gem_object_unpin_map(obj);
> +
> +	rq = intel_context_create_request(ce);
> +	if (IS_ERR(rq))
> +		goto err_obj;
> +
> +	rq->batch = vma;
> +	i915_request_get(rq);
> +
> +	i915_vma_lock(vma);
> +	err = i915_request_await_object(rq, vma->obj, false);
> +	if (!err)
> +		err = i915_vma_move_to_active(vma, rq, 0);
> +	if (!err)
> +		err = rq->engine->emit_bb_start(rq,
> +						vma->node.start,
> +						PAGE_SIZE, 0);
> +	i915_vma_unlock(vma);
> +	i915_request_add(rq);
> +	if (err)
> +		goto err_rq;
> +
> +	i915_gem_object_put(obj);
> +	intel_context_put(ce);
> +
> +	rq->client_link.next = &(*prev)->client_link;
> +	*prev = rq;
> +	return 0;
> +
> +err_rq:
> +	i915_request_put(rq);
> +err_obj:
> +	i915_gem_object_put(obj);
> +err_ce:
> +	intel_context_put(ce);
> +	return err;
> +}
> +
> +static int live_preempt_gang(void *arg)
> +{
> +	struct intel_gt *gt = arg;
> +	struct intel_engine_cs *engine;
> +	enum intel_engine_id id;
> +
> +	if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
> +		return 0;
> +
> +	/*
> +	 * Build as long a chain of preempters as we can, with each
> +	 * request higher priority than the last. Once we are ready, we release
> +	 * the last batch which then precolates down the chain, each releasing
> +	 * the next oldest in turn. The intent is to simply push as hard as we
> +	 * can with the number of preemptions, trying to exceed narrow HW
> +	 * limits. At a minimum, we insist that we can sort all the user
> +	 * high priority levels into execution order.
> +	 */
> +
> +	for_each_engine(engine, gt, id) {
> +		struct i915_request *rq = NULL;
> +		struct igt_live_test t;
> +		IGT_TIMEOUT(end_time);
> +		int prio = 0;
> +		int err = 0;
> +		u32 *cs;
> +
> +		if (!intel_engine_has_preemption(engine))
> +			continue;
> +
> +		if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))
> +			return -EIO;
> +
> +		do {
> +			struct i915_sched_attr attr = {
> +				.priority = I915_USER_PRIORITY(prio++),
> +			};
> +
> +			err = create_gang(engine, &rq);
> +			if (err)
> +				break;
> +
> +			/* Submit each spinner at increasing priority */
> +			engine->schedule(rq, &attr);
> +
> +			if (prio <= I915_PRIORITY_MAX)
> +				continue;
> +
> +			if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT))
> +				break;
> +
> +			if (__igt_timeout(end_time, NULL))
> +				break;
> +		} while (1);
> +		pr_debug("%s: Preempt chain of %d requests\n",
> +			 engine->name, prio);
> +
> +		/*
> +		 * Such that the last spinner is the higher priority and
> +		 * should execute first. When that spinner completes,
> +		 * it will terminate the next lowest spinner until there
> +		 * are no more spinners and the gang is complete.
> +		 */
> +		cs = i915_gem_object_pin_map(rq->batch->obj, I915_MAP_WC);
> +		if (!IS_ERR(cs)) {
> +			*cs = 0;
> +			i915_gem_object_unpin_map(rq->batch->obj);
> +		} else {
> +			err = PTR_ERR(cs);
> +			intel_gt_set_wedged(gt);
> +		}
> +
> +		while (rq) { /* wait for each rq from highest to lowest prio */
> +			struct i915_request *n =
> +				list_next_entry(rq, client_link);
> +
> +			if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0) {
> +				struct drm_printer p =
> +					drm_info_printer(engine->i915->drm.dev);
> +
> +				pr_err("Failed to flush chain of %d requests, at %d\n",
> +				       prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT);
> +				intel_engine_dump(engine, &p,
> +						  "%s\n", engine->name);
> +
> +				err = -ETIME;
> +			}
> +
> +			i915_request_put(rq);
> +			rq = n;
> +		}
> +
> +		if (igt_live_test_end(&t))
> +			err = -EIO;
> +		if (err)
> +			return err;
> +	}
> +
> +	return 0;
> +}
> +
>   static int live_preempt_hang(void *arg)
>   {
>   	struct intel_gt *gt = arg;
> @@ -3028,6 +3223,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
>   		SUBTEST(live_suppress_self_preempt),
>   		SUBTEST(live_suppress_wait_preempt),
>   		SUBTEST(live_chain_preempt),
> +		SUBTEST(live_preempt_gang),
>   		SUBTEST(live_preempt_hang),
>   		SUBTEST(live_preempt_timeout),
>   		SUBTEST(live_preempt_smoke),
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH 4/5] drm/i915/selftests: Exercise long preemption chains

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> Verify that we can execute a long chain of dependent requests from
> userspace, each one slightly more important than the last.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/selftest_lrc.c | 196 +++++++++++++++++++++++++
>   1 file changed, 196 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index d1ed3c0f851c..2ef03a8efa28 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -1915,6 +1915,201 @@ static int live_chain_preempt(void *arg)
>   	goto err_client_lo;
>   }
>   
> +static int create_gang(struct intel_engine_cs *engine,
> +		       struct i915_request **prev)
> +{
> +	struct drm_i915_gem_object *obj;
> +	struct intel_context *ce;
> +	struct i915_request *rq;
> +	struct i915_vma *vma;
> +	u32 *cs;
> +	int err;
> +
> +	ce = intel_context_create(engine->kernel_context->gem_context, engine);
> +	if (IS_ERR(ce))
> +		return PTR_ERR(ce);
> +
> +	obj = i915_gem_object_create_internal(engine->i915, 4096);
> +	if (IS_ERR(obj)) {
> +		err = PTR_ERR(obj);
> +		goto err_ce;
> +	}
> +
> +	vma = i915_vma_instance(obj, ce->vm, NULL);
> +	if (IS_ERR(vma)) {
> +		err = PTR_ERR(vma);
> +		goto err_obj;
> +	}
> +
> +	err = i915_vma_pin(vma, 0, 0, PIN_USER);
> +	if (err)
> +		goto err_obj;
> +
> +	cs = i915_gem_object_pin_map(obj, I915_MAP_WC);
> +	if (IS_ERR(cs))
> +		goto err_obj;
> +
> +	/* Semaphore target: spin until zero */
> +	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> +
> +	*cs++ = MI_SEMAPHORE_WAIT |
> +		MI_SEMAPHORE_POLL |
> +		MI_SEMAPHORE_SAD_EQ_SDD;
> +	*cs++ = 0;
> +	*cs++ = lower_32_bits(vma->node.start);
> +	*cs++ = upper_32_bits(vma->node.start);
> +
> +	if (*prev) {
> +		u64 offset = (*prev)->batch->node.start;
> +
> +		/* Terminate the spinner in the next lower priority batch. */
> +		*cs++ = MI_STORE_DWORD_IMM_GEN4;
> +		*cs++ = lower_32_bits(offset);
> +		*cs++ = upper_32_bits(offset);
> +		*cs++ = 0;
> +	}
> +
> +	*cs++ = MI_BATCH_BUFFER_END;
> +	i915_gem_object_flush_map(obj);
> +	i915_gem_object_unpin_map(obj);
> +
> +	rq = intel_context_create_request(ce);
> +	if (IS_ERR(rq))
> +		goto err_obj;
> +
> +	rq->batch = vma;
> +	i915_request_get(rq);
> +
> +	i915_vma_lock(vma);
> +	err = i915_request_await_object(rq, vma->obj, false);
> +	if (!err)
> +		err = i915_vma_move_to_active(vma, rq, 0);
> +	if (!err)
> +		err = rq->engine->emit_bb_start(rq,
> +						vma->node.start,
> +						PAGE_SIZE, 0);
> +	i915_vma_unlock(vma);
> +	i915_request_add(rq);
> +	if (err)
> +		goto err_rq;
> +
> +	i915_gem_object_put(obj);
> +	intel_context_put(ce);
> +
> +	rq->client_link.next = &(*prev)->client_link;
> +	*prev = rq;
> +	return 0;
> +
> +err_rq:
> +	i915_request_put(rq);
> +err_obj:
> +	i915_gem_object_put(obj);
> +err_ce:
> +	intel_context_put(ce);
> +	return err;
> +}
> +
> +static int live_preempt_gang(void *arg)
> +{
> +	struct intel_gt *gt = arg;
> +	struct intel_engine_cs *engine;
> +	enum intel_engine_id id;
> +
> +	if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
> +		return 0;
> +
> +	/*
> +	 * Build as long a chain of preempters as we can, with each
> +	 * request higher priority than the last. Once we are ready, we release
> +	 * the last batch which then precolates down the chain, each releasing
> +	 * the next oldest in turn. The intent is to simply push as hard as we
> +	 * can with the number of preemptions, trying to exceed narrow HW
> +	 * limits. At a minimum, we insist that we can sort all the user
> +	 * high priority levels into execution order.
> +	 */
> +
> +	for_each_engine(engine, gt, id) {
> +		struct i915_request *rq = NULL;
> +		struct igt_live_test t;
> +		IGT_TIMEOUT(end_time);
> +		int prio = 0;
> +		int err = 0;
> +		u32 *cs;
> +
> +		if (!intel_engine_has_preemption(engine))
> +			continue;
> +
> +		if (igt_live_test_begin(&t, gt->i915, __func__, engine->name))
> +			return -EIO;
> +
> +		do {
> +			struct i915_sched_attr attr = {
> +				.priority = I915_USER_PRIORITY(prio++),
> +			};
> +
> +			err = create_gang(engine, &rq);
> +			if (err)
> +				break;
> +
> +			/* Submit each spinner at increasing priority */
> +			engine->schedule(rq, &attr);
> +
> +			if (prio <= I915_PRIORITY_MAX)
> +				continue;
> +
> +			if (prio > (INT_MAX >> I915_USER_PRIORITY_SHIFT))
> +				break;
> +
> +			if (__igt_timeout(end_time, NULL))
> +				break;
> +		} while (1);
> +		pr_debug("%s: Preempt chain of %d requests\n",
> +			 engine->name, prio);
> +
> +		/*
> +		 * Such that the last spinner is the higher priority and
> +		 * should execute first. When that spinner completes,
> +		 * it will terminate the next lowest spinner until there
> +		 * are no more spinners and the gang is complete.
> +		 */
> +		cs = i915_gem_object_pin_map(rq->batch->obj, I915_MAP_WC);
> +		if (!IS_ERR(cs)) {
> +			*cs = 0;
> +			i915_gem_object_unpin_map(rq->batch->obj);
> +		} else {
> +			err = PTR_ERR(cs);
> +			intel_gt_set_wedged(gt);
> +		}
> +
> +		while (rq) { /* wait for each rq from highest to lowest prio */
> +			struct i915_request *n =
> +				list_next_entry(rq, client_link);
> +
> +			if (err == 0 && i915_request_wait(rq, 0, HZ / 5) < 0) {
> +				struct drm_printer p =
> +					drm_info_printer(engine->i915->drm.dev);
> +
> +				pr_err("Failed to flush chain of %d requests, at %d\n",
> +				       prio, rq_prio(rq) >> I915_USER_PRIORITY_SHIFT);
> +				intel_engine_dump(engine, &p,
> +						  "%s\n", engine->name);
> +
> +				err = -ETIME;
> +			}
> +
> +			i915_request_put(rq);
> +			rq = n;
> +		}
> +
> +		if (igt_live_test_end(&t))
> +			err = -EIO;
> +		if (err)
> +			return err;
> +	}
> +
> +	return 0;
> +}
> +
>   static int live_preempt_hang(void *arg)
>   {
>   	struct intel_gt *gt = arg;
> @@ -3028,6 +3223,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
>   		SUBTEST(live_suppress_self_preempt),
>   		SUBTEST(live_suppress_wait_preempt),
>   		SUBTEST(live_chain_preempt),
> +		SUBTEST(live_preempt_gang),
>   		SUBTEST(live_preempt_hang),
>   		SUBTEST(live_preempt_timeout),
>   		SUBTEST(live_preempt_smoke),
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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Re: [PATCH 5/5] drm/i915/gem: Silence sparse for RCU protection inside the constructor

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> Inside the constructor, while cloning, we need to replace the
> dst->engines. Having forgotten that dst->engines is marked as RCU
> protected, we need to add the appropriate annotations to make sparse
> happy.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 1284f47303fa..6f1e6181f67a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -2009,7 +2009,8 @@ static int clone_engines(struct i915_gem_context *dst,
>   	user_engines = i915_gem_context_user_engines(src);
>   	i915_gem_context_unlock_engines(src);
>   
> -	free_engines(dst->engines);
> +	/* Serialised by constructor */
> +	free_engines(__context_engines_static(dst));
>   	RCU_INIT_POINTER(dst->engines, clone);
>   	if (user_engines)
>   		i915_gem_context_set_user_engines(dst);
> @@ -2044,7 +2045,8 @@ static int clone_sseu(struct i915_gem_context *dst,
>   	unsigned long n;
>   	int err;
>   
> -	clone = dst->engines; /* no locking required; sole access */
> +	/* no locking required; sole access under constructor*/
> +	clone = __context_engines_static(dst);
>   	if (e->num_engines != clone->num_engines) {
>   		err = -EINVAL;
>   		goto unlock;
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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Re: [Intel-gfx] [PATCH 5/5] drm/i915/gem: Silence sparse for RCU protection inside the constructor

[Tvrtko Ursulin]

On 14/11/2019 22:57, Chris Wilson wrote:
> Inside the constructor, while cloning, we need to replace the
> dst->engines. Having forgotten that dst->engines is marked as RCU
> protected, we need to add the appropriate annotations to make sparse
> happy.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 1284f47303fa..6f1e6181f67a 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -2009,7 +2009,8 @@ static int clone_engines(struct i915_gem_context *dst,
>   	user_engines = i915_gem_context_user_engines(src);
>   	i915_gem_context_unlock_engines(src);
>   
> -	free_engines(dst->engines);
> +	/* Serialised by constructor */
> +	free_engines(__context_engines_static(dst));
>   	RCU_INIT_POINTER(dst->engines, clone);
>   	if (user_engines)
>   		i915_gem_context_set_user_engines(dst);
> @@ -2044,7 +2045,8 @@ static int clone_sseu(struct i915_gem_context *dst,
>   	unsigned long n;
>   	int err;
>   
> -	clone = dst->engines; /* no locking required; sole access */
> +	/* no locking required; sole access under constructor*/
> +	clone = __context_engines_static(dst);
>   	if (e->num_engines != clone->num_engines) {
>   		err = -EINVAL;
>   		goto unlock;
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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[PATCH] drm/i915/selftests: Be explicit in ERR_PTR handling

[Chris Wilson]

When setting up a full GGTT, we expect the next insert to fail with
-ENOSPC. Simplify the use of ERR_PTR to not confuse either the reader or
smatch.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 5f133d177212..06ef88510209 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -198,8 +198,8 @@ static int igt_overcommit(void *arg)
 	quirk_add(obj, &objects);
 
 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
-	if (!IS_ERR(vma) || PTR_ERR(vma) != -ENOSPC) {
-		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR(vma));
+	if (vma != ERR_PTR(-ENOSPC)) {
+		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));
 		err = -EINVAL;
 		goto cleanup;
 	}
-- 
2.24.0

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[Intel-gfx] [PATCH] drm/i915/selftests: Be explicit in ERR_PTR handling

[Chris Wilson]

When setting up a full GGTT, we expect the next insert to fail with
-ENOSPC. Simplify the use of ERR_PTR to not confuse either the reader or
smatch.

Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
References: f40a7b7558ef ("drm/i915: Initial selftests for exercising eviction")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/selftests/i915_gem_evict.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
index 5f133d177212..06ef88510209 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_evict.c
@@ -198,8 +198,8 @@ static int igt_overcommit(void *arg)
 	quirk_add(obj, &objects);
 
 	vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0);
-	if (!IS_ERR(vma) || PTR_ERR(vma) != -ENOSPC) {
-		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR(vma));
+	if (vma != ERR_PTR(-ENOSPC)) {
+		pr_err("Failed to evict+insert, i915_gem_object_ggtt_pin returned err=%d\n", (int)PTR_ERR_OR_ZERO(vma));
 		err = -EINVAL;
 		goto cleanup;
 	}
-- 
2.24.0

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Re: [PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Tvrtko Ursulin]

On 15/11/2019 12:49, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-15 12:45:52)
>>
>> On 14/11/2019 22:57, Chris Wilson wrote:
>>> Our callers fall into two categories, those passing timeout=0 who just
>>> want to flush request retirements and those passing a timeout that need
>>> to wait for submission completion (e.g. intel_gt_wait_for_idle()).
>>> Currently, we only wait for a snapshot of timelines at the start of the
>>> wait (but there was an expection that new requests would cause timelines
>>
>> expectation? exception?
> expectation
> 
>>> to appear at the end). However, our callers, such as
>>> intel_gt_wait_for_idle() before suspend, do require us to wait for the
>>> power management requests emitted by retirement as well. If we don't,
>>> then it takes an extra second or two for the background worker to flush
>>> the queue and mark the GT as idle.
>>
>> So with this change wait_for_idle waits for the kernel context to get
>> retired as well. And you say that's faster by a second or two? Which
>> flush gets so much slower, I mean from where, if we don't wait here?
> 
> intel_gt_pm_wait_for_idle() (so i915_gem_suspend, and selftests that
> exercise those same paths) then has to wait for the background retire
> worker to flush the final requests and drop the wakeref.

Ack.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

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Re: [Intel-gfx] [PATCH 1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests()

[Tvrtko Ursulin]

On 15/11/2019 12:49, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-15 12:45:52)
>>
>> On 14/11/2019 22:57, Chris Wilson wrote:
>>> Our callers fall into two categories, those passing timeout=0 who just
>>> want to flush request retirements and those passing a timeout that need
>>> to wait for submission completion (e.g. intel_gt_wait_for_idle()).
>>> Currently, we only wait for a snapshot of timelines at the start of the
>>> wait (but there was an expection that new requests would cause timelines
>>
>> expectation? exception?
> expectation
> 
>>> to appear at the end). However, our callers, such as
>>> intel_gt_wait_for_idle() before suspend, do require us to wait for the
>>> power management requests emitted by retirement as well. If we don't,
>>> then it takes an extra second or two for the background worker to flush
>>> the queue and mark the GT as idle.
>>
>> So with this change wait_for_idle waits for the kernel context to get
>> retired as well. And you say that's faster by a second or two? Which
>> flush gets so much slower, I mean from where, if we don't wait here?
> 
> intel_gt_pm_wait_for_idle() (so i915_gem_suspend, and selftests that
> exercise those same paths) then has to wait for the background retire
> worker to flush the final requests and drop the wakeref.

Ack.

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko

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✗ Fi.CI.BUILD: failure for series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests() (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests() (rev2)
URL   : https://patchwork.freedesktop.org/series/69497/
State : failure

== Summary ==

Applying: drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/intel_gt_requests.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_gt_requests.c
No changes -- Patch already applied.
Applying: drm/i915/selftests: Exercise rc6 handling
Applying: drm/i915/selftests: Be explicit in ERR_PTR handling
Applying: drm/i915/selftests: Exercise long preemption chains
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/selftest_lrc.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/selftest_lrc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/selftest_lrc.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0004 drm/i915/selftests: Exercise long preemption chains
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests() (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915/gt: Wait for new requests in intel_gt_retire_requests() (rev2)
URL   : https://patchwork.freedesktop.org/series/69497/
State : failure

== Summary ==

Applying: drm/i915/gt: Wait for new requests in intel_gt_retire_requests()
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/intel_gt_requests.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/intel_gt_requests.c
No changes -- Patch already applied.
Applying: drm/i915/selftests: Exercise rc6 handling
Applying: drm/i915/selftests: Be explicit in ERR_PTR handling
Applying: drm/i915/selftests: Exercise long preemption chains
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/gt/selftest_lrc.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/gt/selftest_lrc.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gt/selftest_lrc.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0004 drm/i915/selftests: Exercise long preemption chains
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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