* [PATCH] Restore the DDI translation tables after enabling PG1
@ 2015-03-02 18:20 Damien Lespiau
2015-03-02 18:20 ` [PATCH] drm/i915/skl: Restore the DDI translation tables when enabling PW1 Damien Lespiau
0 siblings, 1 reply; 4+ messages in thread
From: Damien Lespiau @ 2015-03-02 18:20 UTC (permalink / raw)
To: intel-gfx
The commit message explains it all, but this cover letter can be made somewhat
useful by saying this patch is on top of:
http://lists.freedesktop.org/archives/intel-gfx/2015-February/060079.html
--
Damien
Damien Lespiau (1):
drm/i915/skl: Restore the DDI translation tables when enabling PW1
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
--
1.8.3.1
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] drm/i915/skl: Restore the DDI translation tables when enabling PW1
2015-03-02 18:20 [PATCH] Restore the DDI translation tables after enabling PG1 Damien Lespiau
@ 2015-03-02 18:20 ` Damien Lespiau
2015-03-02 18:45 ` Paulo Zanoni
2015-03-03 22:47 ` shuang.he
0 siblings, 2 replies; 4+ messages in thread
From: Damien Lespiau @ 2015-03-02 18:20 UTC (permalink / raw)
To: intel-gfx
I was dumping the DDI translation tables to make sure my patch updating
the HDMI entry was doing the right thing when I noticed that the table
was showing reset values after DPMS.
And indeed, the DDI translation registers are in power well 1 on SKL,
and so we're losing their values when shutting down eDP.
Calling intel_prepare_ddi() on PW1 enabling re-programs the table.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 0898550..0ed1287 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -223,8 +223,10 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
1 << PIPE_C | 1 << PIPE_B);
}
- if (power_well->data == SKL_DISP_PW_1)
+ if (power_well->data == SKL_DISP_PW_1) {
+ intel_prepare_ddi(dev);
gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
+ }
}
static void hsw_set_power_well(struct drm_i915_private *dev_priv,
--
1.8.3.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/skl: Restore the DDI translation tables when enabling PW1
2015-03-02 18:20 ` [PATCH] drm/i915/skl: Restore the DDI translation tables when enabling PW1 Damien Lespiau
@ 2015-03-02 18:45 ` Paulo Zanoni
2015-03-03 22:47 ` shuang.he
1 sibling, 0 replies; 4+ messages in thread
From: Paulo Zanoni @ 2015-03-02 18:45 UTC (permalink / raw)
To: Damien Lespiau; +Cc: Intel Graphics Development
2015-03-02 15:20 GMT-03:00 Damien Lespiau <damien.lespiau@intel.com>:
> I was dumping the DDI translation tables to make sure my patch updating
> the HDMI entry was doing the right thing when I noticed that the table
> was showing reset values after DPMS.
>
> And indeed, the DDI translation registers are in power well 1 on SKL,
> and so we're losing their values when shutting down eDP.
>
> Calling intel_prepare_ddi() on PW1 enabling re-programs the table.
>
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0898550..0ed1287 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -223,8 +223,10 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
> 1 << PIPE_C | 1 << PIPE_B);
> }
>
> - if (power_well->data == SKL_DISP_PW_1)
> + if (power_well->data == SKL_DISP_PW_1) {
> + intel_prepare_ddi(dev);
> gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A);
> + }
> }
>
> static void hsw_set_power_well(struct drm_i915_private *dev_priv,
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915/skl: Restore the DDI translation tables when enabling PW1
2015-03-02 18:20 ` [PATCH] drm/i915/skl: Restore the DDI translation tables when enabling PW1 Damien Lespiau
2015-03-02 18:45 ` Paulo Zanoni
@ 2015-03-03 22:47 ` shuang.he
1 sibling, 0 replies; 4+ messages in thread
From: shuang.he @ 2015-03-03 22:47 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, damien.lespiau
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5873
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -5 278/278 273/278
ILK 308/308 308/308
SNB -1 284/284 283/284
IVB -1 380/380 379/380
BYT 294/294 294/294
HSW 387/387 387/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_coherency-sync NO_RESULT(1)CRASH(5)NRUN(1)PASS(7) CRASH(1)NRUN(1)
*PNV igt_gem_userptr_blits_coherency-unsync NO_RESULT(1)CRASH(4)PASS(6) CRASH(1)NRUN(1)
PNV igt_gen3_render_linear_blits FAIL(3)DMESG_WARN(1)PASS(7) FAIL(2)
PNV igt_gen3_render_mixed_blits FAIL(5)PASS(9) FAIL(2)
PNV igt_gem_fence_thrash_bo-write-verify-threaded-none FAIL(2)CRASH(3)PASS(4) CRASH(2)
*SNB igt_gem_flink_bad-flink PASS(2) DMESG_WARN(1)PASS(1)
IVB igt_gem_storedw_batches_loop_normal DMESG_WARN(1)PASS(2) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(17) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2015-03-02 18:20 [PATCH] Restore the DDI translation tables after enabling PG1 Damien Lespiau
2015-03-02 18:20 ` [PATCH] drm/i915/skl: Restore the DDI translation tables when enabling PW1 Damien Lespiau
2015-03-02 18:45 ` Paulo Zanoni
2015-03-03 22:47 ` shuang.he
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