[PATCH] drm/i915: Changes for calculating dsi clk for CHT

* [PATCH] drm/i915: Changes for calculating dsi clk for CHT
@ 2015-03-03 12:57 Gaurav K Singh
  2015-03-04  2:17 ` shuang.he
  0 siblings, 1 reply; 2+ messages in thread
From: Gaurav K Singh @ 2015-03-03 12:57 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula, Shobhit Kumar

Depending on the correct refclk, n ,p for CHT, calculate
the dsi clk during readout DSI HW state.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi_pll.c |   12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 5e44c9b..c7d55e8 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -357,9 +357,17 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 	u32 m = 0, p = 0;
 	int refclk = 25000;
 	int i;
+	u32 n = 1;
+	u32 m_start = 62;
 
 	DRM_DEBUG_KMS("\n");
 
+	if (IS_CHERRYVIEW(dev_priv->dev)) {
+		refclk = 100000;
+		n = 4;
+		m_start = 70;
+	}
+
 	mutex_lock(&dev_priv->dpio_lock);
 	pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
 	pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
@@ -394,9 +402,9 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 		return 0;
 	}
 
-	m = i + 62;
+	m = i + m_start;
 
-	dsi_clock = (m * refclk) / p;
+	dsi_clock = (m * refclk) / (p * n);
 
 	/* pixel_format and pipe_bpp should agree */
 	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
-- 
1.7.9.5

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