[PATCH 0/3] Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

[PATCH 0/3] Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

These patches enable packed format YUV422-Y210, Y212 and Y216
and YUV444-Y410, Y412, Y416 for 10, 12 and 16 bits for ICL+.

IGT needs libraries for Pixman and Cairo to support more than 8bpc.
Work going on from Maarten Lankhorst.

Initial review for Y2xx done https://patchwork.freedesktop.org/series/48729/
However, submitting new patch series consolidating Y2xx and Y4xx.

Swati Sharma (3):
  drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
  drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control
    definitions
  drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for
    universal planes

 drivers/gpu/drm/drm_fourcc.c         |  6 ++++
 drivers/gpu/drm/i915/i915_reg.h      |  6 ++++
 drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 61 ++++++++++++++++++++++++++++++++++--
 include/uapi/drm/drm_fourcc.h        | 18 ++++++++++-
 5 files changed, 118 insertions(+), 3 deletions(-)

-- 
1.9.1

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[PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

The following pixel formats are packed format that follows 4:2:2
chroma sampling. For memory represenation each component is
allocated 16 bits each. Thus each pixel occupies 32bit.

Y210:	For each component, valid data occupies MSB 10 bits.
	LSB 6 bits are filled with zeroes.
Y212:	For each component, valid data occupies MSB 12 bits.
	LSB 4 bits are filled with zeroes.
Y216:	For each component valid data occupies 16 bits,
	doesn't require any padding bits.

First 16 bits stores the Y value and the next 16 bits stores one
of the chroma samples alternatively. The first luma sample will
be accompanied by first U sample and second luma sample is
accompanied by the first V sample.

The following pixel formats are packed format that follows 4:4:4
chroma sampling. Channels are arranged in the order UYVA in
increasing memory order.

Y410:	Each color component occupies 10 bits and X component
	takes 2 bits, thus each pixel occupies 32 bits.
Y412:   Each color component is 16 bits where valid data
	occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
	Thus, each pixel occupies 64 bits.
Y416:   Each color component occupies 16 bits for valid data,
	doesn't require any padding bits. Thus, each pixel
	occupies 64 bits.

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/drm_fourcc.c  |  6 ++++++
 include/uapi/drm/drm_fourcc.h | 18 +++++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index d90ee03..639ab93 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
 		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_XYUV8888,	.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y410,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y412,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+		{ .format = DRM_FORMAT_Y416,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
 		{ .format = DRM_FORMAT_Y0L0,		.depth = 0,  .num_planes = 1,
 		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
 		  .hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 0b44260..97249a5 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -151,7 +151,23 @@
 #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
 
 #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
-#define DRM_FORMAT_XYUV8888		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+#define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
+
+/*
+ * packed Y2xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb
+ */
+#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
+#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
+
+/*
+ * packed Y4xx indicate for each component, xx valid data occupy msb
+ * 16-xx padding occupy lsb except Y410
+ */
+#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] X:V:Y:U 2:10:10:10 little endian */
+#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
+#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [64:0] X:V:Y:U 16:16:16:16 little endian */
 
 /*
  * packed YCbCr420 2x2 tiled formats
-- 
1.9.1

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[PATCH 2/3] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and
16 bits)

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 44958d9..7150bc5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6546,6 +6546,12 @@ enum {
 #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
 #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
 #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
+#define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
+#define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
+#define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
+#define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
+#define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
+#define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
 #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
 #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
-- 
1.9.1

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[PATCH 3/3] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

[swati2.sharma]

From: Swati Sharma <swati2.sharma@intel.com>

Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_sprite.c  | 61 ++++++++++++++++++++++++++++++++++--
 2 files changed, 89 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1cc441f..e7a86c6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2633,6 +2633,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 		return DRM_FORMAT_RGB565;
 	case PLANE_CTL_FORMAT_NV12:
 		return DRM_FORMAT_NV12;
+	case PLANE_CTL_FORMAT_Y210:
+		return DRM_FORMAT_Y210;
+	case PLANE_CTL_FORMAT_Y212:
+		return DRM_FORMAT_Y212;
+	case PLANE_CTL_FORMAT_Y216:
+		return DRM_FORMAT_Y216;
+	case PLANE_CTL_FORMAT_Y410:
+		return DRM_FORMAT_Y410;
+	case PLANE_CTL_FORMAT_Y412:
+		return DRM_FORMAT_Y412;
+	case PLANE_CTL_FORMAT_Y416:
+		return DRM_FORMAT_Y416;
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
@@ -3529,6 +3541,18 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
 	case DRM_FORMAT_NV12:
 		return PLANE_CTL_FORMAT_NV12;
+	case DRM_FORMAT_Y210:
+		return PLANE_CTL_FORMAT_Y210;
+	case DRM_FORMAT_Y212:
+		return PLANE_CTL_FORMAT_Y212;
+	case DRM_FORMAT_Y216:
+		return PLANE_CTL_FORMAT_Y216;
+	case DRM_FORMAT_Y410:
+		return PLANE_CTL_FORMAT_Y410;
+	case DRM_FORMAT_Y412:
+		return PLANE_CTL_FORMAT_Y412;
+	case DRM_FORMAT_Y416:
+		return PLANE_CTL_FORMAT_Y416;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -5022,6 +5046,12 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_NV12:
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
+	case DRM_FORMAT_Y410:
+	case DRM_FORMAT_Y412:
+	case DRM_FORMAT_Y416:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8f3982c..f1bc46d 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1750,6 +1750,27 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
 	DRM_FORMAT_VYUY,
 };
 
+static const uint32_t icl_plane_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+	DRM_FORMAT_Y410,
+	DRM_FORMAT_Y412,
+	DRM_FORMAT_Y416,
+};
+
 static const uint32_t skl_planar_formats[] = {
 	DRM_FORMAT_C8,
 	DRM_FORMAT_RGB565,
@@ -1766,6 +1787,28 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
 	DRM_FORMAT_NV12,
 };
 
+static const uint32_t icl_planar_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+	DRM_FORMAT_Y210,
+	DRM_FORMAT_Y212,
+	DRM_FORMAT_Y216,
+	DRM_FORMAT_Y410,
+	DRM_FORMAT_Y412,
+	DRM_FORMAT_Y416,
+};
+
 static const uint64_t skl_plane_format_modifiers_noccs[] = {
 	I915_FORMAT_MOD_Yf_TILED,
 	I915_FORMAT_MOD_Y_TILED,
@@ -1904,6 +1947,12 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+	case DRM_FORMAT_Y210:
+	case DRM_FORMAT_Y212:
+	case DRM_FORMAT_Y216:
+	case DRM_FORMAT_Y410:
+	case DRM_FORMAT_Y412:
+	case DRM_FORMAT_Y416:
 	case DRM_FORMAT_NV12:
 		if (modifier == I915_FORMAT_MOD_Yf_TILED)
 			return true;
@@ -2045,8 +2094,16 @@ struct intel_plane *
 		plane->update_slave = icl_update_slave;
 
 	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
-		formats = skl_planar_formats;
-		num_formats = ARRAY_SIZE(skl_planar_formats);
+		if (INTEL_GEN(dev_priv) >= 11) {
+			formats = icl_planar_formats;
+			num_formats = ARRAY_SIZE(icl_planar_formats);
+		} else {
+			formats = skl_planar_formats;
+			num_formats = ARRAY_SIZE(skl_planar_formats);
+		}
+	} else if (INTEL_GEN(dev_priv) >= 11) {
+		formats = icl_plane_formats;
+		num_formats = ARRAY_SIZE(icl_plane_formats);
 	} else {
 		formats = skl_plane_formats;
 		num_formats = ARRAY_SIZE(skl_plane_formats);
-- 
1.9.1

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✗ Fi.CI.CHECKPATCH: warning for Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

[Patchwork]

== Series Details ==

Series: Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL
URL   : https://patchwork.freedesktop.org/series/55035/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
74f4fde246cb drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc
-:46: WARNING:LONG_LINE: line over 100 characters
#46: FILE: drivers/gpu/drm/drm_fourcc.c:229:
+		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

-:47: WARNING:LONG_LINE: line over 100 characters
#47: FILE: drivers/gpu/drm/drm_fourcc.c:230:
+		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

-:48: WARNING:LONG_LINE: line over 100 characters
#48: FILE: drivers/gpu/drm/drm_fourcc.c:231:
+		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },

-:49: WARNING:LONG_LINE: line over 100 characters
#49: FILE: drivers/gpu/drm/drm_fourcc.c:232:
+		{ .format = DRM_FORMAT_Y410,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

-:50: WARNING:LONG_LINE: line over 100 characters
#50: FILE: drivers/gpu/drm/drm_fourcc.c:233:
+		{ .format = DRM_FORMAT_Y412,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

-:51: WARNING:LONG_LINE: line over 100 characters
#51: FILE: drivers/gpu/drm/drm_fourcc.c:234:
+		{ .format = DRM_FORMAT_Y416,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },

-:64: WARNING:LONG_LINE_COMMENT: line over 100 characters
#64: FILE: include/uapi/drm/drm_fourcc.h:154:
+#define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */

-:70: WARNING:LONG_LINE_COMMENT: line over 100 characters
#70: FILE: include/uapi/drm/drm_fourcc.h:160:
+#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */

-:71: WARNING:LONG_LINE_COMMENT: line over 100 characters
#71: FILE: include/uapi/drm/drm_fourcc.h:161:
+#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */

-:72: WARNING:LONG_LINE_COMMENT: line over 100 characters
#72: FILE: include/uapi/drm/drm_fourcc.h:162:
+#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */

-:78: WARNING:LONG_LINE_COMMENT: line over 100 characters
#78: FILE: include/uapi/drm/drm_fourcc.h:168:
+#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] X:V:Y:U 2:10:10:10 little endian */

-:79: WARNING:LONG_LINE_COMMENT: line over 100 characters
#79: FILE: include/uapi/drm/drm_fourcc.h:169:
+#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */

-:80: WARNING:LONG_LINE_COMMENT: line over 100 characters
#80: FILE: include/uapi/drm/drm_fourcc.h:170:
+#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [64:0] X:V:Y:U 16:16:16:16 little endian */

total: 0 errors, 13 warnings, 0 checks, 36 lines checked
288965e797ac drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions
3aee6165af4c drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 133 lines checked

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✓ Fi.CI.BAT: success for Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

[Patchwork]

== Series Details ==

Series: Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL
URL   : https://patchwork.freedesktop.org/series/55035/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5401 -> Patchwork_11279
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11279 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11279, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/55035/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11279:

### IGT changes ###

#### Warnings ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - fi-kbl-7567u:       PASS -> {SKIP} +33

  * igt@pm_rpm@basic-pci-d3-state:
    - fi-bsw-kefka:       {SKIP} -> PASS

  
Known issues
------------

  Here are the changes found in Patchwork_11279 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-byt-clapper:     PASS -> FAIL [fdo#107362]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-ivb-3520m:       NOTRUN -> FAIL [fdo#103375] +2

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362] +1

  
#### Possible fixes ####

  * igt@i915_selftest@live_execlists:
    - fi-apl-guc:         INCOMPLETE [fdo#103927] -> PASS

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       FAIL [fdo#108767] -> PASS

  * igt@kms_frontbuffer_tracking@basic:
    - fi-byt-clapper:     FAIL [fdo#103167] -> PASS

  * igt@pm_backlight@basic-brightness:
    - fi-glk-dsi:         INCOMPLETE [fdo#103359] / [k.org#198133] -> PASS

  * igt@pm_rpm@basic-rte:
    - fi-bsw-kefka:       FAIL [fdo#108800] -> PASS

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (46 -> 41)
------------------------------

  Additional (1): fi-ivb-3520m 
  Missing    (6): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-blb-e6850 


Build changes
-------------

    * Linux: CI_DRM_5401 -> Patchwork_11279

  CI_DRM_5401: e1ca1a2f27aa669c656fd6f53a0b77fd96e6ade6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4759: 478452fece3997dfacaa4d6babe6b8bf6fef784f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11279: 3aee6165af4caa29254efc855c00bdbf121d5db4 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3aee6165af4c drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes
288965e797ac drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions
74f4fde246cb drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11279/
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Re: [PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

[Juha-Pekka Heikkila]

On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> The following pixel formats are packed format that follows 4:2:2
> chroma sampling. For memory represenation each component is
> allocated 16 bits each. Thus each pixel occupies 32bit.
> 
> Y210:	For each component, valid data occupies MSB 10 bits.
> 	LSB 6 bits are filled with zeroes.
> Y212:	For each component, valid data occupies MSB 12 bits.
> 	LSB 4 bits are filled with zeroes.
> Y216:	For each component valid data occupies 16 bits,
> 	doesn't require any padding bits.
> 
> First 16 bits stores the Y value and the next 16 bits stores one
> of the chroma samples alternatively. The first luma sample will
> be accompanied by first U sample and second luma sample is
> accompanied by the first V sample.
> 
> The following pixel formats are packed format that follows 4:4:4
> chroma sampling. Channels are arranged in the order UYVA in
> increasing memory order.
> 
> Y410:	Each color component occupies 10 bits and X component
> 	takes 2 bits, thus each pixel occupies 32 bits.
> Y412:   Each color component is 16 bits where valid data
> 	occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
> 	Thus, each pixel occupies 64 bits.
> Y416:   Each color component occupies 16 bits for valid data,
> 	doesn't require any padding bits. Thus, each pixel
> 	occupies 64 bits.
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/drm_fourcc.c  |  6 ++++++
>   include/uapi/drm/drm_fourcc.h | 18 +++++++++++++++++-
>   2 files changed, 23 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
> index d90ee03..639ab93 100644
> --- a/drivers/gpu/drm/drm_fourcc.c
> +++ b/drivers/gpu/drm/drm_fourcc.c
> @@ -226,6 +226,12 @@ const struct drm_format_info *__drm_format_info(u32 format)
>   		{ .format = DRM_FORMAT_VYUY,		.depth = 0,  .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>   		{ .format = DRM_FORMAT_XYUV8888,	.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>   		{ .format = DRM_FORMAT_AYUV,		.depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y210,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y212,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y216,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y410,            .depth = 0,  .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y412,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
> +		{ .format = DRM_FORMAT_Y416,            .depth = 0,  .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>   		{ .format = DRM_FORMAT_Y0L0,		.depth = 0,  .num_planes = 1,
>   		  .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, .block_h = { 2, 0, 0 },
>   		  .hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 0b44260..97249a5 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -151,7 +151,23 @@
>   #define DRM_FORMAT_VYUY		fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>   
>   #define DRM_FORMAT_AYUV		fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
> -#define DRM_FORMAT_XYUV8888		fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
> +#define DRM_FORMAT_XYUV8888	fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
> +
> +/*
> + * packed Y2xx indicate for each component, xx valid data occupy msb
> + * 16-xx padding occupy lsb
> + */
> +#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
> +#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
> +#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
> +
> +/*
> + * packed Y4xx indicate for each component, xx valid data occupy msb
> + * 16-xx padding occupy lsb except Y410
> + */
> +#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* [31:0] X:V:Y:U 2:10:10:10 little endian */
> +#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* [64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
> +#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* [64:0] X:V:Y:U 16:16:16:16 little endian */
^^
[63:0] maybe?

/Juha-Pekka

>   
>   /*
>    * packed YCbCr420 2x2 tiled formats
> 

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Re: [PATCH 2/3] drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitions

[Juha-Pekka Heikkila]

On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> Added needed plane control flag definitions for Y2xx and Y4xx (10, 12 and
> 16 bits)
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 44958d9..7150bc5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6546,6 +6546,12 @@ enum {
>   #define   PLANE_CTL_FORMAT_RGB_565		(14 << 24)
>   #define   ICL_PLANE_CTL_FORMAT_MASK		(0x1f << 23)
>   #define   PLANE_CTL_PIPE_CSC_ENABLE		(1 << 23) /* Pre-GLK */
> +#define   PLANE_CTL_FORMAT_Y210                 (1 << 23)
> +#define   PLANE_CTL_FORMAT_Y212                 (3 << 23)
> +#define   PLANE_CTL_FORMAT_Y216                 (5 << 23)
> +#define   PLANE_CTL_FORMAT_Y410                 (7 << 23)
> +#define   PLANE_CTL_FORMAT_Y412                 (9 << 23)
> +#define   PLANE_CTL_FORMAT_Y416                 (0xb << 23)
>   #define   PLANE_CTL_KEY_ENABLE_MASK		(0x3 << 21)
>   #define   PLANE_CTL_KEY_ENABLE_SOURCE		(1 << 21)
>   #define   PLANE_CTL_KEY_ENABLE_DESTINATION	(2 << 21)
> 

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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Re: [PATCH 1/3] drm: Add Y2xx and Y4xx (xx:10/12/16) format definitions and fourcc

[Sharma, Swati2]

On 11-Jan-19 6:17 PM, Juha-Pekka Heikkila wrote:
> On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
>> From: Swati Sharma <swati2.sharma@intel.com>
>>
>> The following pixel formats are packed format that follows 4:2:2
>> chroma sampling. For memory represenation each component is
>> allocated 16 bits each. Thus each pixel occupies 32bit.
>>
>> Y210:    For each component, valid data occupies MSB 10 bits.
>>     LSB 6 bits are filled with zeroes.
>> Y212:    For each component, valid data occupies MSB 12 bits.
>>     LSB 4 bits are filled with zeroes.
>> Y216:    For each component valid data occupies 16 bits,
>>     doesn't require any padding bits.
>>
>> First 16 bits stores the Y value and the next 16 bits stores one
>> of the chroma samples alternatively. The first luma sample will
>> be accompanied by first U sample and second luma sample is
>> accompanied by the first V sample.
>>
>> The following pixel formats are packed format that follows 4:4:4
>> chroma sampling. Channels are arranged in the order UYVA in
>> increasing memory order.
>>
>> Y410:    Each color component occupies 10 bits and X component
>>     takes 2 bits, thus each pixel occupies 32 bits.
>> Y412:   Each color component is 16 bits where valid data
>>     occupies MSB 12 bits. LSB 4 bits are filled with zeroes.
>>     Thus, each pixel occupies 64 bits.
>> Y416:   Each color component occupies 16 bits for valid data,
>>     doesn't require any padding bits. Thus, each pixel
>>     occupies 64 bits.
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>>   drivers/gpu/drm/drm_fourcc.c  |  6 ++++++
>>   include/uapi/drm/drm_fourcc.h | 18 +++++++++++++++++-
>>   2 files changed, 23 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
>> index d90ee03..639ab93 100644
>> --- a/drivers/gpu/drm/drm_fourcc.c
>> +++ b/drivers/gpu/drm/drm_fourcc.c
>> @@ -226,6 +226,12 @@ const struct drm_format_info 
>> *__drm_format_info(u32 format)
>>           { .format = DRM_FORMAT_VYUY,        .depth = 0, .num_planes 
>> = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
>>           { .format = DRM_FORMAT_XYUV8888,    .depth = 0, .num_planes 
>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
>>           { .format = DRM_FORMAT_AYUV,        .depth = 0, .num_planes 
>> = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, 
>> .is_yuv = true },
>> +        { .format = DRM_FORMAT_Y210,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y212,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y216,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y410,            .depth = 0, 
>> .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y412,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = 
>> true },
>> +        { .format = DRM_FORMAT_Y416,            .depth = 0, 
>> .num_planes = 1, .cpp = { 8, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = 
>> true },
>>           { .format = DRM_FORMAT_Y0L0,        .depth = 0, .num_planes 
>> = 1,
>>             .char_per_block = { 8, 0, 0 }, .block_w = { 2, 0, 0 }, 
>> .block_h = { 2, 0, 0 },
>>             .hsub = 2, .vsub = 2, .has_alpha = true, .is_yuv = true },
>> diff --git a/include/uapi/drm/drm_fourcc.h 
>> b/include/uapi/drm/drm_fourcc.h
>> index 0b44260..97249a5 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -151,7 +151,23 @@
>>   #define DRM_FORMAT_VYUY        fourcc_code('V', 'Y', 'U', 'Y') /* 
>> [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
>>     #define DRM_FORMAT_AYUV        fourcc_code('A', 'Y', 'U', 'V') /* 
>> [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
>> -#define DRM_FORMAT_XYUV8888        fourcc_code('X', 'Y', 'U', 'V') 
>> /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
>> +#define DRM_FORMAT_XYUV8888    fourcc_code('X', 'Y', 'U', 'V') /* 
>> [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
>> +
>> +/*
>> + * packed Y2xx indicate for each component, xx valid data occupy msb
>> + * 16-xx padding occupy lsb
>> + */
>> +#define DRM_FORMAT_Y210         fourcc_code('Y', '2', '1', '0') /* 
>> [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 10:6:10:6:10:6:10:6 little endian */
>> +#define DRM_FORMAT_Y212         fourcc_code('Y', '2', '1', '2') /* 
>> [63:0] Y0:x:Cb0:x:Y1:x:Cr1:x 12:4:12:4:12:4:12:4 little endian */
>> +#define DRM_FORMAT_Y216         fourcc_code('Y', '2', '1', '6') /* 
>> [63:0] Y0:Cb0:Y1:Cr1 16:16:16:16 little endian */
>> +
>> +/*
>> + * packed Y4xx indicate for each component, xx valid data occupy msb
>> + * 16-xx padding occupy lsb except Y410
>> + */
>> +#define DRM_FORMAT_Y410         fourcc_code('Y', '4', '1', '0') /* 
>> [31:0] X:V:Y:U 2:10:10:10 little endian */
>> +#define DRM_FORMAT_Y412         fourcc_code('Y', '4', '1', '2') /* 
>> [64:0] X:x:V:x:Y:x:U:x 12:4:12:4:12:4:12:4 little endian */
>> +#define DRM_FORMAT_Y416         fourcc_code('Y', '4', '1', '6') /* 
>> [64:0] X:V:Y:U 16:16:16:16 little endian */
> ^^
> [63:0] maybe?
ohh sorry. Will correct in next patch series.
>
> /Juha-Pekka
>
>>     /*
>>    * packed YCbCr420 2x2 tiled formats
>>
>

-- 
Thanks and Regards,
Swati

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Re: [PATCH 3/3] drm/i915/icl: Enabling Y2xx and Y4xx (xx:10/12/16) formats for universal planes

[Juha-Pekka Heikkila]

On 11.1.2019 7.30, swati2.sharma@intel.com wrote:
> From: Swati Sharma <swati2.sharma@intel.com>
> 
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++
>   drivers/gpu/drm/i915/intel_sprite.c  | 61 ++++++++++++++++++++++++++++++++++--
>   2 files changed, 89 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1cc441f..e7a86c6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2633,6 +2633,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>   		return DRM_FORMAT_RGB565;
>   	case PLANE_CTL_FORMAT_NV12:
>   		return DRM_FORMAT_NV12;
> +	case PLANE_CTL_FORMAT_Y210:
> +		return DRM_FORMAT_Y210;
> +	case PLANE_CTL_FORMAT_Y212:
> +		return DRM_FORMAT_Y212;
> +	case PLANE_CTL_FORMAT_Y216:
> +		return DRM_FORMAT_Y216;
> +	case PLANE_CTL_FORMAT_Y410:
> +		return DRM_FORMAT_Y410;
> +	case PLANE_CTL_FORMAT_Y412:
> +		return DRM_FORMAT_Y412;
> +	case PLANE_CTL_FORMAT_Y416:
> +		return DRM_FORMAT_Y416;
>   	default:
>   	case PLANE_CTL_FORMAT_XRGB_8888:
>   		if (rgb_order) {
> @@ -3529,6 +3541,18 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
>   		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
>   	case DRM_FORMAT_NV12:
>   		return PLANE_CTL_FORMAT_NV12;
> +	case DRM_FORMAT_Y210:
> +		return PLANE_CTL_FORMAT_Y210;
> +	case DRM_FORMAT_Y212:
> +		return PLANE_CTL_FORMAT_Y212;
> +	case DRM_FORMAT_Y216:
> +		return PLANE_CTL_FORMAT_Y216;
> +	case DRM_FORMAT_Y410:
> +		return PLANE_CTL_FORMAT_Y410;
> +	case DRM_FORMAT_Y412:
> +		return PLANE_CTL_FORMAT_Y412;
> +	case DRM_FORMAT_Y416:
> +		return PLANE_CTL_FORMAT_Y416;
>   	default:
>   		MISSING_CASE(pixel_format);
>   	}
> @@ -5022,6 +5046,12 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
>   	case DRM_FORMAT_UYVY:
>   	case DRM_FORMAT_VYUY:
>   	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_Y210:
> +	case DRM_FORMAT_Y212:
> +	case DRM_FORMAT_Y216:
> +	case DRM_FORMAT_Y410:
> +	case DRM_FORMAT_Y412:
> +	case DRM_FORMAT_Y416:
>   		break;
>   	default:
>   		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8f3982c..f1bc46d 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1750,6 +1750,27 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
>   	DRM_FORMAT_VYUY,
>   };
>   
> +static const uint32_t icl_plane_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +	DRM_FORMAT_Y410,
> +	DRM_FORMAT_Y412,
> +	DRM_FORMAT_Y416,
> +};
> +
>   static const uint32_t skl_planar_formats[] = {
>   	DRM_FORMAT_C8,
>   	DRM_FORMAT_RGB565,
> @@ -1766,6 +1787,28 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
>   	DRM_FORMAT_NV12,
>   };
>   
> +static const uint32_t icl_planar_formats[] = {
> +	DRM_FORMAT_C8,
> +	DRM_FORMAT_RGB565,
> +	DRM_FORMAT_XRGB8888,
> +	DRM_FORMAT_XBGR8888,
> +	DRM_FORMAT_ARGB8888,
> +	DRM_FORMAT_ABGR8888,
> +	DRM_FORMAT_XRGB2101010,
> +	DRM_FORMAT_XBGR2101010,
> +	DRM_FORMAT_YUYV,
> +	DRM_FORMAT_YVYU,
> +	DRM_FORMAT_UYVY,
> +	DRM_FORMAT_VYUY,
> +	DRM_FORMAT_NV12,
> +	DRM_FORMAT_Y210,
> +	DRM_FORMAT_Y212,
> +	DRM_FORMAT_Y216,
> +	DRM_FORMAT_Y410,
> +	DRM_FORMAT_Y412,
> +	DRM_FORMAT_Y416,
> +};
> +
>   static const uint64_t skl_plane_format_modifiers_noccs[] = {
>   	I915_FORMAT_MOD_Yf_TILED,
>   	I915_FORMAT_MOD_Y_TILED,
> @@ -1904,6 +1947,12 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
>   	case DRM_FORMAT_YVYU:
>   	case DRM_FORMAT_UYVY:
>   	case DRM_FORMAT_VYUY:
> +	case DRM_FORMAT_Y210:
> +	case DRM_FORMAT_Y212:
> +	case DRM_FORMAT_Y216:
> +	case DRM_FORMAT_Y410:
> +	case DRM_FORMAT_Y412:
> +	case DRM_FORMAT_Y416:
>   	case DRM_FORMAT_NV12:
>   		if (modifier == I915_FORMAT_MOD_Yf_TILED)
>   			return true;
> @@ -2045,8 +2094,16 @@ struct intel_plane *
>   		plane->update_slave = icl_update_slave;
>   
>   	if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
> -		formats = skl_planar_formats;
> -		num_formats = ARRAY_SIZE(skl_planar_formats);
> +		if (INTEL_GEN(dev_priv) >= 11) {
> +			formats = icl_planar_formats;
> +			num_formats = ARRAY_SIZE(icl_planar_formats);
> +		} else {
> +			formats = skl_planar_formats;
> +			num_formats = ARRAY_SIZE(skl_planar_formats);
> +		}
> +	} else if (INTEL_GEN(dev_priv) >= 11) {
> +		formats = icl_plane_formats;
> +		num_formats = ARRAY_SIZE(icl_plane_formats);
>   	} else {
>   		formats = skl_plane_formats;
>   		num_formats = ARRAY_SIZE(skl_plane_formats);
> 

Look good to me. There will be collision with my Pxxx patches if those 
ever go upstream but it is issue of that time. I guess these patches 
will also wait for IGT support?

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
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✓ Fi.CI.IGT: success for Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL

[Patchwork]

== Series Details ==

Series: Enable Y2xx and Y4xx (xx:10/12/16 bits) packed formats for ICL
URL   : https://patchwork.freedesktop.org/series/55035/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5401_full -> Patchwork_11279_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_11279_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_11279_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_11279_full:

### IGT changes ###

#### Warnings ####

  * igt@pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          {SKIP} -> PASS

  
Known issues
------------

  Here are the changes found in Patchwork_11279_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_fence_thrash@bo-copy:
    - shard-apl:          PASS -> INCOMPLETE [fdo#103927]

  * igt@gem_pwrite_pread@uncached-copy-performance:
    - shard-glk:          PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]

  * igt@kms_busy@extended-modeset-hang-newfb-render-a:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_color@pipe-b-degamma:
    - shard-skl:          PASS -> FAIL [fdo#104782]

  * igt@kms_color@pipe-c-ctm-red-to-blue:
    - shard-skl:          PASS -> FAIL [fdo#107201]

  * igt@kms_cursor_crc@cursor-128x128-dpms:
    - shard-skl:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_crc@cursor-64x21-random:
    - shard-apl:          PASS -> FAIL [fdo#103232]

  * igt@kms_flip_tiling@flip-yf-tiled:
    - shard-skl:          PASS -> FAIL [fdo#108145]

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-apl:          PASS -> FAIL [fdo#103167] +1

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-skl:          NOTRUN -> FAIL [fdo#105683]

  * igt@kms_panel_fitting@legacy:
    - shard-skl:          NOTRUN -> FAIL [fdo#105456]

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-skl:          NOTRUN -> INCOMPLETE [fdo#104108] / [fdo#107773]

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-skl:          NOTRUN -> DMESG-WARN [fdo#106885] +1

  * igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
    - shard-iclb:         NOTRUN -> FAIL [fdo#108948]

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          PASS -> FAIL [fdo#107815]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-y:
    - shard-glk:          PASS -> FAIL [fdo#103166]

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-kbl:          PASS -> DMESG-FAIL [fdo#108950]
    - shard-apl:          PASS -> DMESG-FAIL [fdo#108950]

  * igt@kms_sysfs_edid_timing:
    - shard-skl:          NOTRUN -> FAIL [fdo#100047]

  * igt@pm_rpm@drm-resources-equal:
    - shard-skl:          PASS -> INCOMPLETE [fdo#107807]

  
#### Possible fixes ####

  * igt@kms_atomic_transition@plane-all-transition-fencing:
    - shard-apl:          DMESG-WARN [fdo#103558] / [fdo#105602] / [fdo#109225] -> PASS

  * igt@kms_available_modes_crc@available_mode_test_crc:
    - shard-apl:          FAIL [fdo#106641] -> PASS

  * igt@kms_color@pipe-c-legacy-gamma:
    - shard-apl:          FAIL [fdo#104782] -> PASS

  * igt@kms_cursor_crc@cursor-64x64-onscreen:
    - shard-apl:          FAIL [fdo#103232] -> PASS

  * igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
    - shard-apl:          DMESG-WARN [fdo#103558] / [fdo#105602] -> PASS +31

  * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
    - shard-skl:          FAIL [fdo#103184] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-apl:          FAIL [fdo#103167] -> PASS

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
    - shard-glk:          FAIL [fdo#103167] -> PASS +4

  * igt@kms_plane@pixel-format-pipe-a-planes:
    - shard-apl:          FAIL [fdo#103166] -> PASS

  * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
    - shard-apl:          FAIL [fdo#108948] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
    - shard-glk:          FAIL [fdo#103166] -> PASS +1

  
#### Warnings ####

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
    - shard-apl:          DMESG-WARN [fdo#103558] / [fdo#105602] -> FAIL [fdo#103166]

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
    - shard-apl:          DMESG-FAIL [fdo#103166] / [fdo#103558] / [fdo#105602] -> FAIL [fdo#103166]

  
  [fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105456]: https://bugs.freedesktop.org/show_bug.cgi?id=105456
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105683]: https://bugs.freedesktop.org/show_bug.cgi?id=105683
  [fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
  [fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
  [fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
  [fdo#107815]: https://bugs.freedesktop.org/show_bug.cgi?id=107815
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108948]: https://bugs.freedesktop.org/show_bug.cgi?id=108948
  [fdo#108950]: https://bugs.freedesktop.org/show_bug.cgi?id=108950
  [fdo#109225]: https://bugs.freedesktop.org/show_bug.cgi?id=109225
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133


Participating hosts (6 -> 7)
------------------------------

  Additional (1): shard-iclb 


Build changes
-------------

    * Linux: CI_DRM_5401 -> Patchwork_11279

  CI_DRM_5401: e1ca1a2f27aa669c656fd6f53a0b77fd96e6ade6 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4759: 478452fece3997dfacaa4d6babe6b8bf6fef784f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_11279: 3aee6165af4caa29254efc855c00bdbf121d5db4 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11279/
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