[PATCH] arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration

[PATCH] arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration

[Michal Simek]

From: Neal Frager <neal.frager@amd.com>

This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board.

The Linux DP driver expects the DP to be using the following PLL config:
  - DP video PLL should use the VPLL (0x0)
  - DP audio PLL should use the RPLL (0x3)

Register 0xFD1A0070 configures the DP video PLL.
Register 0xFD1A0074 configures the DP audio PLL.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

 board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
index 2ac4e035d887..3dc9bf8f3a83 100644
--- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
+++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
@@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void)
 	psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
 	psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
 	psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
-	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
-	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
+	psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
+	psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
 	psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
 	psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
 	psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
-- 
2.36.0

Re: [PATCH] arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration

[Michal Simek]

út 10. 5. 2022 v 16:18 odesílatel Michal Simek <monstr@monstr.eu> napsal:
>
> From: Neal Frager <neal.frager@amd.com>
>
> This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board.
>
> The Linux DP driver expects the DP to be using the following PLL config:
>   - DP video PLL should use the VPLL (0x0)
>   - DP audio PLL should use the RPLL (0x3)
>
> Register 0xFD1A0070 configures the DP video PLL.
> Register 0xFD1A0074 configures the DP audio PLL.
>
> Signed-off-by: Neal Frager <neal.frager@amd.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
>  board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
> index 2ac4e035d887..3dc9bf8f3a83 100644
> --- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
> +++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c
> @@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void)
>         psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
>         psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
>         psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
> -       psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U);
> -       psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U);
> +       psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U);
> +       psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U);
>         psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U);
>         psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
>         psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
> --
> 2.36.0
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs