[PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

[PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

[Joonas Lahtinen]

Configurations like virtualized environments may support only 48 bit
ppGTT without supporting 32 bit ppGTT. Support this by disconnecting
the relationship of the two feature bits.

Cc: Tina Zhang <tina.zhang@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 10aa776..a5eada1 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 		return 0;
 	}
 
-	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt)
-		return has_full_48bit_ppgtt ? 3 : 2;
-	else
-		return has_aliasing_ppgtt ? 1 : 0;
+	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
+		if (has_full_48bit_ppgtt)
+			return 3;
+
+		if (has_full_ppgtt)
+			return 2;
+	}
+
+	return has_aliasing_ppgtt ? 1 : 0;
 }
 
 static int ppgtt_bind_vma(struct i915_vma *vma,
-- 
2.7.5

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✓ Fi.CI.BAT: success for drm/i915: Disconnect 32 and 48 bit ppGTT support

[Patchwork]

== Series Details ==

Series: drm/i915: Disconnect 32 and 48 bit ppGTT support
URL   : https://patchwork.freedesktop.org/series/28676/
State : success

== Summary ==

Series 28676v1 drm/i915: Disconnect 32 and 48 bit ppGTT support
https://patchwork.freedesktop.org/api/1.0/series/28676/revisions/1/mbox/

Test kms_flip:
        Subgroup basic-flip-vs-modeset:
                skip       -> PASS       (fi-skl-x1585l) fdo#101781

fdo#101781 https://bugs.freedesktop.org/show_bug.cgi?id=101781

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:448s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:434s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:358s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:557s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:512s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:534s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:510s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:607s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:447s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:419s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:423s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:506s
fi-ivb-3770      total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:481s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:468s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:585s
fi-kbl-r         total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:590s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:526s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:459s
fi-skl-6700k     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:474s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:485s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:439s
fi-skl-x1585l    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:504s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:548s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:407s

fbb8288699ef622bbfc6e10bdca6773a16f93fac drm-tip: 2017y-08m-11d-09h-03m-47s UTC integration manifest
aa663dacd1d7 drm/i915: Disconnect 32 and 48 bit ppGTT support

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5377/
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Re: [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

[Chris Wilson]

Quoting Joonas Lahtinen (2017-08-11 10:51:26)
> Configurations like virtualized environments may support only 48 bit
> ppGTT without supporting 32 bit ppGTT. Support this by disconnecting
> the relationship of the two feature bits.

Did the gvt patches land in dinq? After that, I say we just kill the
module parameter, and so make the choice of GTT mode much easier to follow.

Have we ever asked a user to debug a problem by changing GTT modes in
the last 5 years?
-Chris
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Re: [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

[Zhenyu Wang]

[-- Attachment #1.1: Type: text/plain, Size: 2417 bytes --]

On 2017.08.14 20:34:48 +0800, Zhi Wang wrote:
> Looks has_full_48bit_ppgtt is tied to has_full_ppgtt now. Will that be
> disconnected also in future?
>

That's what this is for. So for gvt, we just set has_full_48bit_ppgtt but
not has_full_ppgtt.

> On 08/11/17 17:51, Joonas Lahtinen wrote:
> > Configurations like virtualized environments may support only 48 bit
> > ppGTT without supporting 32 bit ppGTT. Support this by disconnecting
> > the relationship of the two feature bits.
> > 
> > Cc: Tina Zhang <tina.zhang@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Zhi Wang <zhi.a.wang@intel.com>
> > Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++----
> >   1 file changed, 9 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 10aa776..a5eada1 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >   		return 0;
> >   	}
> > -	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt)
> > -		return has_full_48bit_ppgtt ? 3 : 2;
> > -	else
> > -		return has_aliasing_ppgtt ? 1 : 0;
> > +	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
> > +		if (has_full_48bit_ppgtt)
> > +			return 3;
> > +
> > +		if (has_full_ppgtt)
> > +			return 2;
> > +	}
> > +
> > +	return has_aliasing_ppgtt ? 1 : 0;
> >   }
> >   static int ppgtt_bind_vma(struct i915_vma *vma,
> > 
> ---------------------------------------------------------------------
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> 4 Domiciled in Helsinki
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> This e-mail and any attachments may contain confidential material for
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Re: [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

[Wang, Zhi A]

Thanks! LGTM. :)

-----Original Message-----
From: Zhenyu Wang [mailto:zhenyuw@linux.intel.com] 
Sent: Monday, August 14, 2017 3:01 PM
To: Wang, Zhi A <zhi.a.wang@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Intel graphics driver community testing & development <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

On 2017.08.14 20:34:48 +0800, Zhi Wang wrote:
> Looks has_full_48bit_ppgtt is tied to has_full_ppgtt now. Will that be 
> disconnected also in future?
>

That's what this is for. So for gvt, we just set has_full_48bit_ppgtt but not has_full_ppgtt.

> On 08/11/17 17:51, Joonas Lahtinen wrote:
> > Configurations like virtualized environments may support only 48 bit 
> > ppGTT without supporting 32 bit ppGTT. Support this by disconnecting 
> > the relationship of the two feature bits.
> > 
> > Cc: Tina Zhang <tina.zhang@intel.com>
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Zhi Wang <zhi.a.wang@intel.com>
> > Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++----
> >   1 file changed, 9 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> > b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 10aa776..a5eada1 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
> >   		return 0;
> >   	}
> > -	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt)
> > -		return has_full_48bit_ppgtt ? 3 : 2;
> > -	else
> > -		return has_aliasing_ppgtt ? 1 : 0;
> > +	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
> > +		if (has_full_48bit_ppgtt)
> > +			return 3;
> > +
> > +		if (has_full_ppgtt)
> > +			return 2;
> > +	}
> > +
> > +	return has_aliasing_ppgtt ? 1 : 0;
> >   }
> >   static int ppgtt_bind_vma(struct i915_vma *vma,
> > 
> ---------------------------------------------------------------------
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> 0357606 -
> 4 Domiciled in Helsinki
> 
> This e-mail and any attachments may contain confidential material for 
> the sole use of the intended recipient(s). Any review or distribution 
> by others is strictly prohibited. If you are not the intended 
> recipient, please contact the sender and delete all copies.
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Re: [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

[Zhi Wang]

Looks has_full_48bit_ppgtt is tied to has_full_ppgtt now. Will that be 
disconnected also in future?

On 08/11/17 17:51, Joonas Lahtinen wrote:
> Configurations like virtualized environments may support only 48 bit
> ppGTT without supporting 32 bit ppGTT. Support this by disconnecting
> the relationship of the two feature bits.
> 
> Cc: Tina Zhang <tina.zhang@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Zhi Wang <zhi.a.wang@intel.com>
> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++----
>   1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 10aa776..a5eada1 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
>   		return 0;
>   	}
>   
> -	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt)
> -		return has_full_48bit_ppgtt ? 3 : 2;
> -	else
> -		return has_aliasing_ppgtt ? 1 : 0;
> +	if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
> +		if (has_full_48bit_ppgtt)
> +			return 3;
> +
> +		if (has_full_ppgtt)
> +			return 2;
> +	}
> +
> +	return has_aliasing_ppgtt ? 1 : 0;
>   }
>   
>   static int ppgtt_bind_vma(struct i915_vma *vma,
> 
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Re: [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support

[Zhi Wang]

Glad to see this happen. :)

After this patch landed, some code pieces in i915 which are specifically 
for disabling dynamic PDP update via LRIs under 32 bit PPGTT could also 
be removed.

For example, gen8_preallocate_top_level_pdp() in i915_gem_gtt.c

Thanks,
Zhi.

On 08/11/17 18:30, Chris Wilson wrote:
> Quoting Joonas Lahtinen (2017-08-11 10:51:26)
>> Configurations like virtualized environments may support only 48 bit
>> ppGTT without supporting 32 bit ppGTT. Support this by disconnecting
>> the relationship of the two feature bits.
> 
> Did the gvt patches land in dinq? After that, I say we just kill the
> module parameter, and so make the choice of GTT mode much easier to follow.
> 
> Have we ever asked a user to debug a problem by changing GTT modes in
> the last 5 years?
> -Chris
> 
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