* [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device
@ 2016-06-24 4:58 Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit Andrew Jeffery
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Andrew Jeffery @ 2016-06-24 4:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, Joel Stanley, qemu-devel, qemu-arm,
Andrew Jeffery
Hi all,
These are three patches implementing minimal functionality for the ASPEED System
Control Unit device and integrating it into the AST2400 SoC model/palmetto-bmc
machine. The device is critical for initialisation of u-boot and the kernel as
it provides chip level control registers, influencing the configuration of the
software and the software's configuration of the SoC.
Since v2:
* Fix mixing of offsets and register indexes
* Sanity check device property values
* SoC actually initialises the silicon revision
Since v1:
* Select reset values based on silicon revision
* Expose hardware strapping values via properties
Andrew Jeffery (3):
hw/misc: Add a model for the ASPEED System Control Unit
ast2400: Integrate the SCU model and set silicon revision
palmetto-bmc: Configure the SCU's hardware strapping register
hw/arm/ast2400.c | 21 ++++
hw/arm/palmetto-bmc.c | 2 +
hw/misc/Makefile.objs | 1 +
hw/misc/aspeed_scu.c | 284 +++++++++++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 3 +
include/hw/arm/ast2400.h | 2 +
include/hw/misc/aspeed_scu.h | 34 ++++++
7 files changed, 347 insertions(+)
create mode 100644 hw/misc/aspeed_scu.c
create mode 100644 include/hw/misc/aspeed_scu.h
--
2.7.4
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit
2016-06-24 4:58 [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Andrew Jeffery
@ 2016-06-24 4:58 ` Andrew Jeffery
2016-06-27 13:42 ` Peter Maydell
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 2/3] ast2400: Integrate the SCU model and set silicon revision Andrew Jeffery
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Andrew Jeffery @ 2016-06-24 4:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, Joel Stanley, qemu-devel, qemu-arm,
Andrew Jeffery
The SCU is a collection of chip-level control registers that manage the
various functions supported by ASPEED SoCs. Typically the bits control
interactions with clocks, external hardware or reset behaviour, and we
can largly take a hands-off approach to reads and writes.
Firmware makes heavy use of the state to determine how to boot, but the
reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev
property is exposed so that the integrating SoC model can configure the
silicon revision, which in-turn selects the appropriate reset values.
Further qdev properties are exposed so the board model can configure the
board-dependent hardware strapping.
Almost all provided AST2400 reset values are specified by the datasheet.
The notable exception is SOC_SCRATCH1, where we mark the DRAM as
successfully initialised to avoid unnecessary dark corners in the SoC's
u-boot support.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Since v2:
* Fix mixing of offsets and register indexes
* Sanity check device property values
* Move trace event definition to hw/misc/trace-events
Since v1:
* Move reset values into SCU implementation (also make register defines private)
* Expose silicon-rev property which is used to select appropriate reset values
* Expose hw-strap1/hw-strap2 properties for board-specific SoC configuration
hw/misc/Makefile.objs | 1 +
hw/misc/aspeed_scu.c | 284 +++++++++++++++++++++++++++++++++++++++++++
hw/misc/trace-events | 3 +
include/hw/misc/aspeed_scu.h | 34 ++++++
4 files changed, 322 insertions(+)
create mode 100644 hw/misc/aspeed_scu.c
create mode 100644 include/hw/misc/aspeed_scu.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index ffb49c11aca6..54020aa06c00 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -52,3 +52,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_EDU) += edu.o
obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
obj-$(CONFIG_AUX) += aux.o
+obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
new file mode 100644
index 000000000000..ff231dbb3c17
--- /dev/null
+++ b/hw/misc/aspeed_scu.c
@@ -0,0 +1,284 @@
+/*
+ * ASPEED System Control Unit
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include <inttypes.h>
+#include "hw/misc/aspeed_scu.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "qemu/bitops.h"
+#include "trace.h"
+
+#define TO_REG(offset) ((offset) >> 2)
+
+#define PROT_KEY TO_REG(0x00)
+#define SYS_RST_CTRL TO_REG(0x04)
+#define CLK_SEL TO_REG(0x08)
+#define CLK_STOP_CTRL TO_REG(0x0C)
+#define FREQ_CNTR_CTRL TO_REG(0x10)
+#define FREQ_CNTR_EVAL TO_REG(0x14)
+#define IRQ_CTRL TO_REG(0x18)
+#define D2PLL_PARAM TO_REG(0x1C)
+#define MPLL_PARAM TO_REG(0x20)
+#define HPLL_PARAM TO_REG(0x24)
+#define FREQ_CNTR_RANGE TO_REG(0x28)
+#define MISC_CTRL1 TO_REG(0x2C)
+#define PCI_CTRL1 TO_REG(0x30)
+#define PCI_CTRL2 TO_REG(0x34)
+#define PCI_CTRL3 TO_REG(0x38)
+#define SYS_RST_STATUS TO_REG(0x3C)
+#define SOC_SCRATCH1 TO_REG(0x40)
+#define SOC_SCRATCH2 TO_REG(0x44)
+#define MAC_CLK_DELAY TO_REG(0x48)
+#define MISC_CTRL2 TO_REG(0x4C)
+#define VGA_SCRATCH1 TO_REG(0x50)
+#define VGA_SCRATCH2 TO_REG(0x54)
+#define VGA_SCRATCH3 TO_REG(0x58)
+#define VGA_SCRATCH4 TO_REG(0x5C)
+#define VGA_SCRATCH5 TO_REG(0x60)
+#define VGA_SCRATCH6 TO_REG(0x64)
+#define VGA_SCRATCH7 TO_REG(0x68)
+#define VGA_SCRATCH8 TO_REG(0x6C)
+#define HW_STRAP1 TO_REG(0x70)
+#define RNG_CTRL TO_REG(0x74)
+#define RNG_DATA TO_REG(0x78)
+#define SILICON_REV TO_REG(0x7C)
+#define PINMUX_CTRL1 TO_REG(0x80)
+#define PINMUX_CTRL2 TO_REG(0x84)
+#define PINMUX_CTRL3 TO_REG(0x88)
+#define PINMUX_CTRL4 TO_REG(0x8C)
+#define PINMUX_CTRL5 TO_REG(0x90)
+#define PINMUX_CTRL6 TO_REG(0x94)
+#define WDT_RST_CTRL TO_REG(0x9C)
+#define PINMUX_CTRL7 TO_REG(0xA0)
+#define PINMUX_CTRL8 TO_REG(0xA4)
+#define PINMUX_CTRL9 TO_REG(0xA8)
+#define WAKEUP_EN TO_REG(0xC0)
+#define WAKEUP_CTRL TO_REG(0xC4)
+#define HW_STRAP2 TO_REG(0xD0)
+#define FREE_CNTR4 TO_REG(0xE0)
+#define FREE_CNTR4_EXT TO_REG(0xE4)
+#define CPU2_CTRL TO_REG(0x100)
+#define CPU2_BASE_SEG1 TO_REG(0x104)
+#define CPU2_BASE_SEG2 TO_REG(0x108)
+#define CPU2_BASE_SEG3 TO_REG(0x10C)
+#define CPU2_BASE_SEG4 TO_REG(0x110)
+#define CPU2_BASE_SEG5 TO_REG(0x114)
+#define CPU2_CACHE_CTRL TO_REG(0x118)
+#define UART_HPLL_CLK TO_REG(0x160)
+#define PCIE_CTRL TO_REG(0x180)
+#define BMC_MMIO_CTRL TO_REG(0x184)
+#define RELOC_DECODE_BASE1 TO_REG(0x188)
+#define RELOC_DECODE_BASE2 TO_REG(0x18C)
+#define MAILBOX_DECODE_BASE TO_REG(0x190)
+#define SRAM_DECODE_BASE1 TO_REG(0x194)
+#define SRAM_DECODE_BASE2 TO_REG(0x198)
+#define BMC_REV TO_REG(0x19C)
+#define BMC_DEV_ID TO_REG(0x1A4)
+
+#define PROT_KEY_UNLOCK 0x1688A8A8
+#define SCU_IO_REGION_SIZE 0x20000
+
+#define AST2400_A0_SILICON_REV 0x02000303U
+
+static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
+ [SYS_RST_CTRL] = 0xFFCFFEDCU,
+ [CLK_SEL] = 0xF3F40000U,
+ [CLK_STOP_CTRL] = 0x19FC3E8BU,
+ [D2PLL_PARAM] = 0x00026108U,
+ [MPLL_PARAM] = 0x00030291U,
+ [HPLL_PARAM] = 0x00000291U,
+ [MISC_CTRL1] = 0x00000010U,
+ [PCI_CTRL1] = 0x20001A03U,
+ [PCI_CTRL2] = 0x20001A03U,
+ [PCI_CTRL3] = 0x04000030U,
+ [SYS_RST_STATUS] = 0x00000001U,
+ [SOC_SCRATCH1] = 0x000000C0U, /* SoC completed DRAM init */
+ [MISC_CTRL2] = 0x00000023U,
+ [RNG_CTRL] = 0x0000000EU,
+ [PINMUX_CTRL2] = 0x0000F000U,
+ [PINMUX_CTRL3] = 0x01000000U,
+ [PINMUX_CTRL4] = 0x000000FFU,
+ [PINMUX_CTRL5] = 0x0000A000U,
+ [WDT_RST_CTRL] = 0x003FFFF3U,
+ [PINMUX_CTRL8] = 0xFFFF0000U,
+ [PINMUX_CTRL9] = 0x000FFFFFU,
+ [FREE_CNTR4] = 0x000000FFU,
+ [FREE_CNTR4_EXT] = 0x000000FFU,
+ [CPU2_BASE_SEG1] = 0x80000000U,
+ [CPU2_BASE_SEG4] = 0x1E600000U,
+ [CPU2_BASE_SEG5] = 0xC0000000U,
+ [UART_HPLL_CLK] = 0x00001903U,
+ [PCIE_CTRL] = 0x0000007BU,
+ [BMC_DEV_ID] = 0x00002402U
+};
+
+static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AspeedSCUState *s = ASPEED_SCU(opaque);
+ int reg = TO_REG(offset);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return 0;
+ }
+
+ switch (reg) {
+ case WAKEUP_EN:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ break;
+ }
+
+ return s->regs[reg];
+}
+
+static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
+{
+ AspeedSCUState *s = ASPEED_SCU(opaque);
+ int reg = TO_REG(offset);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
+ s->regs[PROT_KEY] != PROT_KEY_UNLOCK) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
+ return;
+ }
+
+ trace_aspeed_scu_write(offset, size, data);
+
+ switch (reg) {
+ case FREQ_CNTR_EVAL:
+ case VGA_SCRATCH1 ... VGA_SCRATCH8:
+ case RNG_DATA:
+ case SILICON_REV:
+ case FREE_CNTR4:
+ case FREE_CNTR4_EXT:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+ s->regs[reg] = data;
+}
+
+static const MemoryRegionOps aspeed_scu_ops = {
+ .read = aspeed_scu_read,
+ .write = aspeed_scu_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 4,
+ .valid.unaligned = false,
+};
+
+static void aspeed_scu_reset(DeviceState *dev)
+{
+ AspeedSCUState *s = ASPEED_SCU(dev);
+ const uint32_t *reset;
+
+ switch (s->silicon_rev) {
+ case AST2400_A0_SILICON_REV:
+ reset = ast2400_a0_resets;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ memcpy(s->regs, reset, sizeof(s->regs));
+ s->regs[SILICON_REV] = s->silicon_rev;
+ s->regs[HW_STRAP1] = s->hw_strap1;
+ s->regs[HW_STRAP2] = s->hw_strap2;
+}
+
+static uint32_t aspeed_silicon_revs[] = { AST2400_A0_SILICON_REV, };
+
+static bool is_supported_silicon_rev(uint32_t silicon_rev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
+ if (silicon_rev == aspeed_silicon_revs[i]) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static void aspeed_scu_realize(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ AspeedSCUState *s = ASPEED_SCU(dev);
+
+ if (!is_supported_silicon_rev(s->silicon_rev)) {
+ error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
+ s->silicon_rev);
+ return;
+ }
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
+ TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription vmstate_aspeed_scu = {
+ .name = "aspeed.scu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property aspeed_scu_properties[] = {
+ DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
+ DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
+ DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap1, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_scu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = aspeed_scu_realize;
+ dc->reset = aspeed_scu_reset;
+ dc->desc = "ASPEED System Control Unit";
+ dc->vmsd = &vmstate_aspeed_scu;
+ dc->props = aspeed_scu_properties;
+}
+
+static const TypeInfo aspeed_scu_info = {
+ .name = TYPE_ASPEED_SCU,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedSCUState),
+ .class_init = aspeed_scu_class_init,
+};
+
+static void aspeed_scu_register_types(void)
+{
+ type_register_static(&aspeed_scu_info);
+}
+
+type_init(aspeed_scu_register_types);
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 16b6701cbf9a..ea52a14d787f 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -50,3 +50,6 @@ milkymist_pfpu_memory_read(uint32_t addr, uint32_t value) "addr %08x value %08x"
milkymist_pfpu_memory_write(uint32_t addr, uint32_t value) "addr %08x value %08x"
milkymist_pfpu_vectout(uint32_t a, uint32_t b, uint32_t dma_ptr) "a %08x b %08x dma_ptr %08x"
milkymist_pfpu_pulse_irq(void) "Pulse IRQ"
+
+# hw/misc/aspeed_scu.c
+aspeed_scu_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64 " of size %u: 0x%" PRIx32
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
new file mode 100644
index 000000000000..6b8e46f85fad
--- /dev/null
+++ b/include/hw/misc/aspeed_scu.h
@@ -0,0 +1,34 @@
+/*
+ * ASPEED System Control Unit
+ *
+ * Andrew Jeffery <andrew@aj.id.au>
+ *
+ * Copyright 2016 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+#ifndef ASPEED_SCU_H
+#define ASPEED_SCU_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_SCU "aspeed.scu"
+#define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU)
+
+#define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
+
+typedef struct AspeedSCUState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+
+ /*< public >*/
+ MemoryRegion iomem;
+
+ uint32_t regs[ASPEED_SCU_NR_REGS];
+ uint32_t silicon_rev;
+ uint32_t hw_strap1;
+ uint32_t hw_strap2;
+} AspeedSCUState;
+
+#endif /* ASPEED_SCU_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v3 2/3] ast2400: Integrate the SCU model and set silicon revision
2016-06-24 4:58 [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit Andrew Jeffery
@ 2016-06-24 4:58 ` Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 3/3] palmetto-bmc: Configure the SCU's hardware strapping register Andrew Jeffery
2016-06-27 13:47 ` [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Peter Maydell
3 siblings, 0 replies; 9+ messages in thread
From: Andrew Jeffery @ 2016-06-24 4:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, Joel Stanley, qemu-devel, qemu-arm,
Andrew Jeffery
By specifying the silicon revision we select the appropriate reset
values for the SoC.
Additionally, expose hardware strapping properties aliasing those
provided by the SCU for board-specific configuration.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
Since v2:
* Configure SoC silicon revision in the SCU via silicon-rev property
Since v1:
* Remove reset value configuration
* Alias the SCU's hardware strapping properties to expose them to boards
hw/arm/ast2400.c | 21 +++++++++++++++++++++
include/hw/arm/ast2400.h | 2 ++
2 files changed, 23 insertions(+)
diff --git a/hw/arm/ast2400.c b/hw/arm/ast2400.c
index 4a9de0e10cbc..b14a82fcdef1 100644
--- a/hw/arm/ast2400.c
+++ b/hw/arm/ast2400.c
@@ -24,9 +24,12 @@
#define AST2400_IOMEM_SIZE 0x00200000
#define AST2400_IOMEM_BASE 0x1E600000
#define AST2400_VIC_BASE 0x1E6C0000
+#define AST2400_SCU_BASE 0x1E6E2000
#define AST2400_TIMER_BASE 0x1E782000
#define AST2400_I2C_BASE 0x1E78A000
+#define AST2400_A0_SILICON_REV 0x02000303
+
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
static const int timer_irqs[] = { 16, 17, 18, 35, 36, 37, 38, 39, };
@@ -72,6 +75,16 @@ static void ast2400_init(Object *obj)
object_initialize(&s->i2c, sizeof(s->i2c), TYPE_ASPEED_I2C);
object_property_add_child(obj, "i2c", OBJECT(&s->i2c), NULL);
qdev_set_parent_bus(DEVICE(&s->i2c), sysbus_get_default());
+
+ object_initialize(&s->scu, sizeof(s->scu), TYPE_ASPEED_SCU);
+ object_property_add_child(obj, "scu", OBJECT(&s->scu), NULL);
+ qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
+ AST2400_A0_SILICON_REV);
+ object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
+ "hw-strap1", &error_abort);
+ object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
+ "hw-strap2", &error_abort);
}
static void ast2400_realize(DeviceState *dev, Error **errp)
@@ -110,6 +123,14 @@ static void ast2400_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
}
+ /* SCU */
+ object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, AST2400_SCU_BASE);
+
/* UART - attach an 8250 to the IO space as our UART5 */
if (serial_hds[0]) {
qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]);
diff --git a/include/hw/arm/ast2400.h b/include/hw/arm/ast2400.h
index c05ed5376736..f1a64fd3893d 100644
--- a/include/hw/arm/ast2400.h
+++ b/include/hw/arm/ast2400.h
@@ -14,6 +14,7 @@
#include "hw/arm/arm.h"
#include "hw/intc/aspeed_vic.h"
+#include "hw/misc/aspeed_scu.h"
#include "hw/timer/aspeed_timer.h"
#include "hw/i2c/aspeed_i2c.h"
@@ -27,6 +28,7 @@ typedef struct AST2400State {
AspeedVICState vic;
AspeedTimerCtrlState timerctrl;
AspeedI2CState i2c;
+ AspeedSCUState scu;
} AST2400State;
#define TYPE_AST2400 "ast2400"
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Qemu-devel] [PATCH v3 3/3] palmetto-bmc: Configure the SCU's hardware strapping register
2016-06-24 4:58 [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 2/3] ast2400: Integrate the SCU model and set silicon revision Andrew Jeffery
@ 2016-06-24 4:58 ` Andrew Jeffery
2016-06-24 10:53 ` Cédric Le Goater
2016-06-27 13:47 ` [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Peter Maydell
3 siblings, 1 reply; 9+ messages in thread
From: Andrew Jeffery @ 2016-06-24 4:58 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, Joel Stanley, qemu-devel, qemu-arm,
Andrew Jeffery
The magic constant configures the following options:
* 28:27: Configure DRAM size as 256MB
* 26:24: DDR3 SDRAM with CL = 6, CWL = 5
* 23: Configure 24/48MHz CLKIN
* 22: Disable GPIOE pass-through mode
* 21: Disable GPIOD pass-through mode
* 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses
* 19: Disable ACPI
* 18: Configure 48MHz CLKIN
* 17: Disable BMC 2nd boot watchdog timer
* 16: Decode SuperIO address 0x2E
* 15: VGA Class Code
* 14: Enable LPC dedicated reset pin
* 13:12: Enable SPI Master and SPI Slave to AHB Bridge
* 11:10: Select CPU:AHB ratio = 2:1
* 9:8: Select 384MHz H-PLL
* 7: Configure MAC#2 for RMII/NCSI
* 6: Configure MAC#1 for RMII/NCSI
* 5: No VGA BIOS ROM
* 4: Boot using 32bit SPI address mode
* 3:2: Select 16MB VGA memory
* 1:0: Boot from SPI flash memory
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/palmetto-bmc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
index a51d960510ee..b8eed21348d8 100644
--- a/hw/arm/palmetto-bmc.c
+++ b/hw/arm/palmetto-bmc.c
@@ -44,6 +44,8 @@ static void palmetto_bmc_init(MachineState *machine)
&bmc->ram);
object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
&error_abort);
+ object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
+ &error_abort);
object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
&error_abort);
--
2.7.4
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v3 3/3] palmetto-bmc: Configure the SCU's hardware strapping register
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 3/3] palmetto-bmc: Configure the SCU's hardware strapping register Andrew Jeffery
@ 2016-06-24 10:53 ` Cédric Le Goater
0 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2016-06-24 10:53 UTC (permalink / raw)
To: Andrew Jeffery, Peter Maydell; +Cc: Joel Stanley, qemu-devel, qemu-arm
On 06/24/2016 06:58 AM, Andrew Jeffery wrote:
> The magic constant configures the following options:
>
> * 28:27: Configure DRAM size as 256MB
> * 26:24: DDR3 SDRAM with CL = 6, CWL = 5
> * 23: Configure 24/48MHz CLKIN
> * 22: Disable GPIOE pass-through mode
> * 21: Disable GPIOD pass-through mode
> * 20: Enable LPC decode of SuperIO 0x2E/0x4E addresses
> * 19: Disable ACPI
> * 18: Configure 48MHz CLKIN
> * 17: Disable BMC 2nd boot watchdog timer
> * 16: Decode SuperIO address 0x2E
> * 15: VGA Class Code
> * 14: Enable LPC dedicated reset pin
> * 13:12: Enable SPI Master and SPI Slave to AHB Bridge
> * 11:10: Select CPU:AHB ratio = 2:1
> * 9:8: Select 384MHz H-PLL
> * 7: Configure MAC#2 for RMII/NCSI
> * 6: Configure MAC#1 for RMII/NCSI
> * 5: No VGA BIOS ROM
> * 4: Boot using 32bit SPI address mode
> * 3:2: Select 16MB VGA memory
> * 1:0: Boot from SPI flash memory
As the previous patchset was not setting the silicon version, we did not
see that should be skipping the SPI Flash checks in U-Boot. So, with this
little change :
- object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
+ object_property_set_int(OBJECT(&bmc->soc), 0x120CE414, "hw-strap1",
We reach a point where U-Boot is ready to load a kernel :
U-Boot 2013.07 (Jun 07 2016 - 01:33:14)
I2C: ready
DRAM: 256 MiB
WARNING: Caches not enabled
Flash: SPI Flash ID: 19ba20
32 MiB
In: serial
Out: serial
Err: serial
H/W: AST2400 series chip Rev. 00
Watchdog: 300s
Net: aspeednic#0
Warning: aspeednic#0 (eth0) using random MAC address - aa:36:26:50:30:9c
Hit any key to stop autoboot: 0
boot#
I will see if it is worth adding what is required in the SMC controller to
support this. Else, we have the quick solution above.
Tested-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/arm/palmetto-bmc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/arm/palmetto-bmc.c b/hw/arm/palmetto-bmc.c
> index a51d960510ee..b8eed21348d8 100644
> --- a/hw/arm/palmetto-bmc.c
> +++ b/hw/arm/palmetto-bmc.c
> @@ -44,6 +44,8 @@ static void palmetto_bmc_init(MachineState *machine)
> &bmc->ram);
> object_property_add_const_link(OBJECT(&bmc->soc), "ram", OBJECT(&bmc->ram),
> &error_abort);
> + object_property_set_int(OBJECT(&bmc->soc), 0x120CE416, "hw-strap1",
> + &error_abort);
> object_property_set_bool(OBJECT(&bmc->soc), true, "realized",
> &error_abort);
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit Andrew Jeffery
@ 2016-06-27 13:42 ` Peter Maydell
2016-06-27 14:01 ` Andrew Jeffery
0 siblings, 1 reply; 9+ messages in thread
From: Peter Maydell @ 2016-06-27 13:42 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Cédric Le Goater, Joel Stanley, QEMU Developers, qemu-arm
On 24 June 2016 at 05:58, Andrew Jeffery <andrew@aj.id.au> wrote:
> The SCU is a collection of chip-level control registers that manage the
> various functions supported by ASPEED SoCs. Typically the bits control
> interactions with clocks, external hardware or reset behaviour, and we
> can largly take a hands-off approach to reads and writes.
>
> Firmware makes heavy use of the state to determine how to boot, but the
> reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev
> property is exposed so that the integrating SoC model can configure the
> silicon revision, which in-turn selects the appropriate reset values.
> Further qdev properties are exposed so the board model can configure the
> board-dependent hardware strapping.
>
> Almost all provided AST2400 reset values are specified by the datasheet.
> The notable exception is SOC_SCRATCH1, where we mark the DRAM as
> successfully initialised to avoid unnecessary dark corners in the SoC's
> u-boot support.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> Since v2:
>
> * Fix mixing of offsets and register indexes
> * Sanity check device property values
> * Move trace event definition to hw/misc/trace-events
>
> Since v1:
>
> * Move reset values into SCU implementation (also make register defines private)
> * Expose silicon-rev property which is used to select appropriate reset values
> * Expose hw-strap1/hw-strap2 properties for board-specific SoC configuration
>
> hw/misc/Makefile.objs | 1 +
> hw/misc/aspeed_scu.c | 284 +++++++++++++++++++++++++++++++++++++++++++
> hw/misc/trace-events | 3 +
> include/hw/misc/aspeed_scu.h | 34 ++++++
> 4 files changed, 322 insertions(+)
> create mode 100644 hw/misc/aspeed_scu.c
> create mode 100644 include/hw/misc/aspeed_scu.h
>
> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> index ffb49c11aca6..54020aa06c00 100644
> --- a/hw/misc/Makefile.objs
> +++ b/hw/misc/Makefile.objs
> @@ -52,3 +52,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o
> obj-$(CONFIG_EDU) += edu.o
> obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
> obj-$(CONFIG_AUX) += aux.o
> +obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o
> diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> new file mode 100644
> index 000000000000..ff231dbb3c17
> --- /dev/null
> +++ b/hw/misc/aspeed_scu.c
> @@ -0,0 +1,284 @@
> +/*
> + * ASPEED System Control Unit
> + *
> + * Andrew Jeffery <andrew@aj.id.au>
> + *
> + * Copyright 2016 IBM Corp.
> + *
> + * This code is licensed under the GPL version 2 or later. See
> + * the COPYING file in the top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include <inttypes.h>
osdep.h provides this, you don't need to include it yourself.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
so if this is the only problem with the series I'll fix it up
when I put it in target-arm.next.
thanks
-- PMM
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device
2016-06-24 4:58 [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Andrew Jeffery
` (2 preceding siblings ...)
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 3/3] palmetto-bmc: Configure the SCU's hardware strapping register Andrew Jeffery
@ 2016-06-27 13:47 ` Peter Maydell
2016-06-27 14:13 ` Andrew Jeffery
3 siblings, 1 reply; 9+ messages in thread
From: Peter Maydell @ 2016-06-27 13:47 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Cédric Le Goater, Joel Stanley, QEMU Developers, qemu-arm
On 24 June 2016 at 05:58, Andrew Jeffery <andrew@aj.id.au> wrote:
> Hi all,
>
> These are three patches implementing minimal functionality for the ASPEED System
> Control Unit device and integrating it into the AST2400 SoC model/palmetto-bmc
> machine. The device is critical for initialisation of u-boot and the kernel as
> it provides chip level control registers, influencing the configuration of the
> software and the software's configuration of the SoC.
>
> Since v2:
>
> * Fix mixing of offsets and register indexes
> * Sanity check device property values
> * SoC actually initialises the silicon revision
>
> Since v1:
>
> * Select reset values based on silicon revision
> * Expose hardware strapping values via properties
>
> Andrew Jeffery (3):
> hw/misc: Add a model for the ASPEED System Control Unit
> ast2400: Integrate the SCU model and set silicon revision
> palmetto-bmc: Configure the SCU's hardware strapping register
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit
2016-06-27 13:42 ` Peter Maydell
@ 2016-06-27 14:01 ` Andrew Jeffery
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jeffery @ 2016-06-27 14:01 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, Joel Stanley, QEMU Developers, qemu-arm
[-- Attachment #1: Type: text/plain, Size: 3329 bytes --]
On Mon, 2016-06-27 at 14:42 +0100, Peter Maydell wrote:
> On 24 June 2016 at 05:58, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > The SCU is a collection of chip-level control registers that manage the
> > various functions supported by ASPEED SoCs. Typically the bits control
> > interactions with clocks, external hardware or reset behaviour, and we
> > can largly take a hands-off approach to reads and writes.
> >
> > Firmware makes heavy use of the state to determine how to boot, but the
> > reset values vary from SoC to SoC (eg AST2400 vs AST2500). A qdev
> > property is exposed so that the integrating SoC model can configure the
> > silicon revision, which in-turn selects the appropriate reset values.
> > Further qdev properties are exposed so the board model can configure the
> > board-dependent hardware strapping.
> >
> > Almost all provided AST2400 reset values are specified by the datasheet.
> > The notable exception is SOC_SCRATCH1, where we mark the DRAM as
> > successfully initialised to avoid unnecessary dark corners in the SoC's
> > u-boot support.
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > Since v2:
> >
> > * Fix mixing of offsets and register indexes
> > * Sanity check device property values
> > * Move trace event definition to hw/misc/trace-events
> >
> > Since v1:
> >
> > * Move reset values into SCU implementation (also make register defines private)
> > * Expose silicon-rev property which is used to select appropriate reset values
> > * Expose hw-strap1/hw-strap2 properties for board-specific SoC configuration
> >
> > hw/misc/Makefile.objs | 1 +
> > hw/misc/aspeed_scu.c | 284 +++++++++++++++++++++++++++++++++++++++++++
> > hw/misc/trace-events | 3 +
> > include/hw/misc/aspeed_scu.h | 34 ++++++
> > 4 files changed, 322 insertions(+)
> > create mode 100644 hw/misc/aspeed_scu.c
> > create mode 100644 include/hw/misc/aspeed_scu.h
> >
> > diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
> > index ffb49c11aca6..54020aa06c00 100644
> > --- a/hw/misc/Makefile.objs
> > +++ b/hw/misc/Makefile.objs
> > @@ -52,3 +52,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o
> > obj-$(CONFIG_EDU) += edu.o
> > obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
> > obj-$(CONFIG_AUX) += aux.o
> > +obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o
> > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
> > new file mode 100644
> > index 000000000000..ff231dbb3c17
> > --- /dev/null
> > +++ b/hw/misc/aspeed_scu.c
> > @@ -0,0 +1,284 @@
> > +/*
> > + * ASPEED System Control Unit
> > + *
> > + * Andrew Jeffery <andrew@aj.id.au>
> > + *
> > + * Copyright 2016 IBM Corp.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + */
> > +
> > +#include "qemu/osdep.h"
> > +#include
> osdep.h provides this, you don't need to include it yourself.
>
> Otherwise
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>
> so if this is the only problem with the series I'll fix it up
> when I put it in target-arm.next.
>
As far as I'm aware that's the only issue aside from the discussion on
patch 3/3.
Cheers,
Andrew
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device
2016-06-27 13:47 ` [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Peter Maydell
@ 2016-06-27 14:13 ` Andrew Jeffery
0 siblings, 0 replies; 9+ messages in thread
From: Andrew Jeffery @ 2016-06-27 14:13 UTC (permalink / raw)
To: Peter Maydell
Cc: Cédric Le Goater, Joel Stanley, QEMU Developers, qemu-arm
[-- Attachment #1: Type: text/plain, Size: 1364 bytes --]
On Mon, 2016-06-27 at 14:47 +0100, Peter Maydell wrote:
> On 24 June 2016 at 05:58, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > Hi all,
> >
> > These are three patches implementing minimal functionality for the ASPEED System
> > Control Unit device and integrating it into the AST2400 SoC model/palmetto-bmc
> > machine. The device is critical for initialisation of u-boot and the kernel as
> > it provides chip level control registers, influencing the configuration of the
> > software and the software's configuration of the SoC.
> >
> > Since v2:
> >
> > * Fix mixing of offsets and register indexes
> > * Sanity check device property values
> > * SoC actually initialises the silicon revision
> >
> > Since v1:
> >
> > * Select reset values based on silicon revision
> > * Expose hardware strapping values via properties
> >
> > Andrew Jeffery (3):
> > hw/misc: Add a model for the ASPEED System Control Unit
> > ast2400: Integrate the SCU model and set silicon revision
> > palmetto-bmc: Configure the SCU's hardware strapping register
>
>
> Applied to target-arm.next, thanks.
Thanks; I intend to send a follow-up patch addressing the discussion on
patch 3/3. I'm away for a week so it will miss soft-freeze, but given
the nature of the patch that might not be the end of the world?
Cheers,
Andrew
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2016-06-27 14:14 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-06-24 4:58 [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 1/3] hw/misc: Add a model for the ASPEED System Control Unit Andrew Jeffery
2016-06-27 13:42 ` Peter Maydell
2016-06-27 14:01 ` Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 2/3] ast2400: Integrate the SCU model and set silicon revision Andrew Jeffery
2016-06-24 4:58 ` [Qemu-devel] [PATCH v3 3/3] palmetto-bmc: Configure the SCU's hardware strapping register Andrew Jeffery
2016-06-24 10:53 ` Cédric Le Goater
2016-06-27 13:47 ` [Qemu-devel] [PATCH v3 0/3] Add ASPEED SCU device Peter Maydell
2016-06-27 14:13 ` Andrew Jeffery
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