[Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Maciej W. Rozycki]

Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit 
and the CP0.Config3.DSP bit for the artificial mips32r5-generic and 
mips64dspr2 processors.  They have the DSPr2 ASE enabled in `insn_flags' 
and CPUs that implement that ASE need to have both CP0.Config3.DSP and 
CP0.Config3.DSP2P set or software won't detect its presence.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
qemu-mips-config-dsp.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate_init.c	2014-11-04 03:32:21.408100354 +0000
+++ qemu-git-trunk/target-mips/translate_init.c	2014-11-04 03:39:48.458972962 +0000
@@ -330,7 +330,8 @@ static const mips_def_t mips_defs[] =
                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
                        (1 << CP0C1_CA),
         .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
+        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
+                       (0 << CP0C3_VInt),
         .CP0_LLAddr_rw_bitmask = 0,
         .CP0_LLAddr_shift = 4,
         .SYNCI_Step = 32,
@@ -396,7 +397,8 @@ static const mips_def_t mips_defs[] =
                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
                        (1 << CP0C1_CA),
         .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
+        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
+                       (1 << CP0C3_DSPP),
         .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
         .CP0_Config4_rw_bitmask = 0,
         .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
@@ -677,7 +679,8 @@ static const mips_def_t mips_defs[] =
                        (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
                        (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
         .CP0_Config2 = MIPS_CONFIG2,
-        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
+                       (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
         .CP0_LLAddr_rw_bitmask = 0,
         .CP0_LLAddr_shift = 0,
         .SYNCI_Step = 32,

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Leon Alrae]

On 04/11/2014 15:41, Maciej W. Rozycki wrote:
> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit 
> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and 
> mips64dspr2 processors.  They have the DSPr2 ASE enabled in `insn_flags' 
> and CPUs that implement that ASE need to have both CP0.Config3.DSP and 
> CP0.Config3.DSP2P set or software won't detect its presence.
> 
> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
> ---
> qemu-mips-config-dsp.diff
> Index: qemu-git-trunk/target-mips/translate_init.c
> ===================================================================
> --- qemu-git-trunk.orig/target-mips/translate_init.c	2014-11-04 03:32:21.408100354 +0000
> +++ qemu-git-trunk/target-mips/translate_init.c	2014-11-04 03:39:48.458972962 +0000
> @@ -330,7 +330,8 @@ static const mips_def_t mips_defs[] =
>                         (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>                         (1 << CP0C1_CA),
>          .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
> +                       (0 << CP0C3_VInt),
>          .CP0_LLAddr_rw_bitmask = 0,
>          .CP0_LLAddr_shift = 4,
>          .SYNCI_Step = 32,
> @@ -396,7 +397,8 @@ static const mips_def_t mips_defs[] =
>                         (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>                         (1 << CP0C1_CA),
>          .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
> +        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
> +                       (1 << CP0C3_DSPP),
>          .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
>          .CP0_Config4_rw_bitmask = 0,
>          .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
> @@ -677,7 +679,8 @@ static const mips_def_t mips_defs[] =
>                         (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>                         (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>          .CP0_Config2 = MIPS_CONFIG2,
> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
> +        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
> +                       (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
>          .CP0_LLAddr_rw_bitmask = 0,
>          .CP0_LLAddr_shift = 0,
>          .SYNCI_Step = 32,
> 

Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Leon Alrae]

On 05/11/2014 15:26, Leon Alrae wrote:
> On 04/11/2014 15:41, Maciej W. Rozycki wrote:
>> Set the CP0.Config3.DSP2P bit for the 74kf processor and both that bit 
>> and the CP0.Config3.DSP bit for the artificial mips32r5-generic and 
>> mips64dspr2 processors.  They have the DSPr2 ASE enabled in `insn_flags' 
>> and CPUs that implement that ASE need to have both CP0.Config3.DSP and 
>> CP0.Config3.DSP2P set or software won't detect its presence.
>>
>> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
>> ---
>> qemu-mips-config-dsp.diff
>> Index: qemu-git-trunk/target-mips/translate_init.c
>> ===================================================================
>> --- qemu-git-trunk.orig/target-mips/translate_init.c	2014-11-04 03:32:21.408100354 +0000
>> +++ qemu-git-trunk/target-mips/translate_init.c	2014-11-04 03:39:48.458972962 +0000
>> @@ -330,7 +330,8 @@ static const mips_def_t mips_defs[] =
>>                         (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>>                         (1 << CP0C1_CA),
>>          .CP0_Config2 = MIPS_CONFIG2,
>> -        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
>> +        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
>> +                       (0 << CP0C3_VInt),
>>          .CP0_LLAddr_rw_bitmask = 0,
>>          .CP0_LLAddr_shift = 4,
>>          .SYNCI_Step = 32,
>> @@ -396,7 +397,8 @@ static const mips_def_t mips_defs[] =
>>                         (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>>                         (1 << CP0C1_CA),
>>          .CP0_Config2 = MIPS_CONFIG2,
>> -        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M),
>> +        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
>> +                       (1 << CP0C3_DSPP),
>>          .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
>>          .CP0_Config4_rw_bitmask = 0,
>>          .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
>> @@ -677,7 +679,8 @@ static const mips_def_t mips_defs[] =
>>                         (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>>                         (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>>          .CP0_Config2 = MIPS_CONFIG2,
>> -        .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
>> +        .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
>> +                       (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
>>          .CP0_LLAddr_rw_bitmask = 0,
>>          .CP0_LLAddr_shift = 0,
>>          .SYNCI_Step = 32,
>>

When I've been applying this patch to my mips-next candidate branch for
2.2 I realized that you haven't rebased it onto the recent version where
MSA has been added to mips32r5-generic. Now I don't think that having
DSP and MSA on one CPU makes sense, therefore what I'm going to do is to
change mips32r5-generic part in your patch slightly: instead of setting
CP0.Config3.DSP/DSP2P the patch will remove ASE_DSP/DSPR2 insn_flags.

Regards,
Leon

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Maciej W. Rozycki]

On Fri, 7 Nov 2014, Leon Alrae wrote:

> When I've been applying this patch to my mips-next candidate branch for
> 2.2 I realized that you haven't rebased it onto the recent version where
> MSA has been added to mips32r5-generic. Now I don't think that having
> DSP and MSA on one CPU makes sense, therefore what I'm going to do is to
> change mips32r5-generic part in your patch slightly: instead of setting
> CP0.Config3.DSP/DSP2P the patch will remove ASE_DSP/DSPR2 insn_flags.

 I have been working with the current trunk, the change applies 
correctly there AFAICT.

 I have no objections to changing mips32r5-generic, it is artificial 
anyway.  But what do you mean by DSP and MSA on one CPU having no sense, 
is there a conflict between the two ASEs?

  Maciej

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Leon Alrae]

On 07/11/2014 12:33, Maciej W. Rozycki wrote:
> On Fri, 7 Nov 2014, Leon Alrae wrote:
> 
>> When I've been applying this patch to my mips-next candidate branch for
>> 2.2 I realized that you haven't rebased it onto the recent version where
>> MSA has been added to mips32r5-generic. Now I don't think that having
>> DSP and MSA on one CPU makes sense, therefore what I'm going to do is to
>> change mips32r5-generic part in your patch slightly: instead of setting
>> CP0.Config3.DSP/DSP2P the patch will remove ASE_DSP/DSPR2 insn_flags.
> 
>  I have been working with the current trunk, the change applies 
> correctly there AFAICT.

55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
mips32r5-generic which is not present on your patch.

> 
>  I have no objections to changing mips32r5-generic, it is artificial 
> anyway.  But what do you mean by DSP and MSA on one CPU having no sense, 
> is there a conflict between the two ASEs?

I was considering making mips32r5-generic less artificial and slowly
evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
supports MSA, but doesn't support DSP ASE). Furthermore, none from the
latest MIPS CPUs supports both ASEs.

Regards,
Leon

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Maciej W. Rozycki]

On Fri, 7 Nov 2014, Leon Alrae wrote:

> >  I have been working with the current trunk, the change applies 
> > correctly there AFAICT.
> 
> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
> mips32r5-generic which is not present on your patch.

 Indeed, my mistake for some reason.

> >  I have no objections to changing mips32r5-generic, it is artificial 
> > anyway.  But what do you mean by DSP and MSA on one CPU having no sense, 
> > is there a conflict between the two ASEs?
> 
> I was considering making mips32r5-generic less artificial and slowly
> evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
> supports MSA, but doesn't support DSP ASE). Furthermore, none from the
> latest MIPS CPUs supports both ASEs.

 Why not leave mips32r5-generic alone then and add a correct entry for 
the P5600 instead?

  Maciej

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Leon Alrae]

On 07/11/14 17:36, Maciej W. Rozycki wrote:
> On Fri, 7 Nov 2014, Leon Alrae wrote:
> 
>>>  I have been working with the current trunk, the change applies 
>>> correctly there AFAICT.
>>
>> 55a2201 commit added (1 << CP0C3_MSAP) to CP0_Config3 for
>> mips32r5-generic which is not present on your patch.
> 
>  Indeed, my mistake for some reason.
> 
>>>  I have no objections to changing mips32r5-generic, it is artificial 
>>> anyway.  But what do you mean by DSP and MSA on one CPU having no sense, 
>>> is there a conflict between the two ASEs?
>>
>> I was considering making mips32r5-generic less artificial and slowly
>> evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
>> supports MSA, but doesn't support DSP ASE). Furthermore, none from the
>> latest MIPS CPUs supports both ASEs.
> 
>  Why not leave mips32r5-generic alone then and add a correct entry for 
> the P5600 instead?

Because it is additional configuration which is not specified anywhere
that has to be maintain and tested. If a user wants to experiment with
configurations, then it is relatively easy to add new or modify existing
CPU definitions and this doesn't require any knowledge of QEMU. The only
clear benefit for me from having a generic core is when new
architectural feature is introduced and there is no actual CPU
available. In this case we use generic core to expose new feature to a
user. But in my opinion it eventually should be replaced by a real CPU
containing supporting feature.

Regards,
Leon

Re: [Qemu-devel] [PATCH] mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bits

[Maciej W. Rozycki]

On Fri, 7 Nov 2014, Leon Alrae wrote:

> >> I was considering making mips32r5-generic less artificial and slowly
> >> evolve it towards some existing MIPS32R5 CPU, for example P5600 (which
> >> supports MSA, but doesn't support DSP ASE). Furthermore, none from the
> >> latest MIPS CPUs supports both ASEs.
> > 
> >  Why not leave mips32r5-generic alone then and add a correct entry for 
> > the P5600 instead?
> 
> Because it is additional configuration which is not specified anywhere
> that has to be maintain and tested. If a user wants to experiment with
> configurations, then it is relatively easy to add new or modify existing
> CPU definitions and this doesn't require any knowledge of QEMU. The only
> clear benefit for me from having a generic core is when new
> architectural feature is introduced and there is no actual CPU
> available. In this case we use generic core to expose new feature to a
> user. But in my opinion it eventually should be replaced by a real CPU
> containing supporting feature.

 I see having generic entries as a way to verify architecture 
conformance, including but not limited to make it possible to validate 
portability of software for which there is no suitable hardware 
available.  This is actually one of the main purposes for processor 
emulators to exist in the first place.  Here for example one could check 
if context switching is implemented correctly in the Linux kernel for a 
processor that implements both the MSA and the DSP register set -- which 
is something that is best done beforehand, before lots of people get in 
trouble once such hardware is decided to be made.

 And I disagree with a claim that such configurations are not specified 
anywhere -- they are, in the architecture specifications that allows 
them.  A good example in the context of the MIPS architecture is the 
semantics of the CP0.Status.MX bit in hardware that has both the DSP and 
the MDMX ASE implemented -- it has been specified very precisely in the 
architecture even though to the best of my knowledge no such hardware 
has actually ever been made.

 Whether the maintenance burden to have these extra configurations 
(pretty low IMO, but it's not my call to decide here) is justified or 
not is another question of course.

  Maciej