* [Qemu-devel] [PATCH] mips: Enable vectored interrupt support for the 74Kf CPU
@ 2014-11-04 15:42 Maciej W. Rozycki
2014-11-17 11:17 ` Leon Alrae
0 siblings, 1 reply; 2+ messages in thread
From: Maciej W. Rozycki @ 2014-11-04 15:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Leon Alrae, Aurelien Jarno
Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
---
qemu-mips-config-74k-vint.diff
Index: qemu-git-trunk/target-mips/translate_init.c
===================================================================
--- qemu-git-trunk.orig/target-mips/translate_init.c 2014-11-04 03:39:48.458972962 +0000
+++ qemu-git-trunk/target-mips/translate_init.c 2014-11-04 03:43:15.479004225 +0000
@@ -331,7 +331,7 @@ static const mips_def_t mips_defs[] =
(1 << CP0C1_CA),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
- (0 << CP0C3_VInt),
+ (1 << CP0C3_VInt),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] mips: Enable vectored interrupt support for the 74Kf CPU
2014-11-04 15:42 [Qemu-devel] [PATCH] mips: Enable vectored interrupt support for the 74Kf CPU Maciej W. Rozycki
@ 2014-11-17 11:17 ` Leon Alrae
0 siblings, 0 replies; 2+ messages in thread
From: Leon Alrae @ 2014-11-17 11:17 UTC (permalink / raw)
To: Maciej W. Rozycki, qemu-devel; +Cc: Aurelien Jarno
On 04/11/2014 15:42, Maciej W. Rozycki wrote:
> Enable vectored interrupt support for the 74Kf CPU, reflecting hardware.
>
> Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
> ---
> qemu-mips-config-74k-vint.diff
> Index: qemu-git-trunk/target-mips/translate_init.c
> ===================================================================
> --- qemu-git-trunk.orig/target-mips/translate_init.c 2014-11-04 03:39:48.458972962 +0000
> +++ qemu-git-trunk/target-mips/translate_init.c 2014-11-04 03:43:15.479004225 +0000
> @@ -331,7 +331,7 @@ static const mips_def_t mips_defs[] =
> (1 << CP0C1_CA),
> .CP0_Config2 = MIPS_CONFIG2,
> .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
> - (0 << CP0C3_VInt),
> + (1 << CP0C3_VInt),
> .CP0_LLAddr_rw_bitmask = 0,
> .CP0_LLAddr_shift = 4,
> .SYNCI_Step = 32,
>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2014-11-04 15:42 [Qemu-devel] [PATCH] mips: Enable vectored interrupt support for the 74Kf CPU Maciej W. Rozycki
2014-11-17 11:17 ` Leon Alrae
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