[PATCH v2 0/7] clock/dpll autoidle support

[PATCH v2 0/7] clock/dpll autoidle support

[Rajendra Nayak]

OMAP has various clock nodes and dpll's
which support hardware level autoidle.
Enabling hardware level autoidle provides
better power savings without much software
intervention.

This series does the following to help enable
hardware level autoidling using clock framework
for some of these nodes on OMAP3 and OMAP4

-1- Adds support for providing function pointers
for enabling/disabling autoidle in clkops
-2- Populates these in clkops for all OMAP3/4 dplls
-3- Enables all dpll autoidle late in boot on OMAP3 and OMAP4
-4- Adds support for mx postdivider autoidle (present
only on OMAP4) and enables it late in OMAP4 boot

Some of the patches in this series were earlier posted
and discussed as part of another series here
http://marc.info/?l=linux-omap&m=129681356402594&w=2
They are now posted as a seperate series as discussed
here
http://marc.info/?l=linux-omap&m=129713867702170&w=2

The patches are boot tested on OMAP3430sdp and
OMAP4430sdp.

The following changes since commit 100b33c8bd8a3235fd0b7948338d6cbb3db3c63d:
  Linus Torvalds (1):
        Linux 2.6.38-rc4

are available in the git repository at:

 git://gitorious.org/omap-pm/linux.git dpll-autoidle-v2

Changes in v2:
-1- Added support for clkout_x2 autogating
-2- Populated dpll_usb_clkdcoldo_ck's missing
clksel register

Rajendra Nayak (7):
  omap: clock: Check for enable/disable ops support
  omap3: dpll: Populate clkops for dpll1_ck
  omap: clock: Add allow_idle/deny_idle support in clkops
  omap: dpll: Add allow_idle/deny_idle support for all DPLL's
  omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot
  omap4: dpll: Add dpll api to control GATE_CTRL
  omap4: dpll: Enable auto gate control for all MX postdividers

 arch/arm/mach-omap2/clock.c             |   25 +++++++++++---
 arch/arm/mach-omap2/clock.h             |    5 +++
 arch/arm/mach-omap2/clock3xxx_data.c    |    4 +-
 arch/arm/mach-omap2/clock44xx_data.c    |   54 +++++++++++++++++------------
 arch/arm/mach-omap2/dpll3xxx.c          |   57 +++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/pm34xx.c            |   18 ++-------
 arch/arm/mach-omap2/pm44xx.c            |    4 ++
 arch/arm/plat-omap/clock.c              |   26 ++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    7 ++++
 9 files changed, 156 insertions(+), 44 deletions(-)

[PATCH v2 0/7] clock/dpll autoidle support

[Rajendra Nayak]

OMAP has various clock nodes and dpll's
which support hardware level autoidle.
Enabling hardware level autoidle provides
better power savings without much software
intervention.

This series does the following to help enable
hardware level autoidling using clock framework
for some of these nodes on OMAP3 and OMAP4

-1- Adds support for providing function pointers
for enabling/disabling autoidle in clkops
-2- Populates these in clkops for all OMAP3/4 dplls
-3- Enables all dpll autoidle late in boot on OMAP3 and OMAP4
-4- Adds support for mx postdivider autoidle (present
only on OMAP4) and enables it late in OMAP4 boot

Some of the patches in this series were earlier posted
and discussed as part of another series here
http://marc.info/?l=linux-omap&m=129681356402594&w=2
They are now posted as a seperate series as discussed
here
http://marc.info/?l=linux-omap&m=129713867702170&w=2

The patches are boot tested on OMAP3430sdp and
OMAP4430sdp.

The following changes since commit 100b33c8bd8a3235fd0b7948338d6cbb3db3c63d:
  Linus Torvalds (1):
        Linux 2.6.38-rc4

are available in the git repository at:

 git://gitorious.org/omap-pm/linux.git dpll-autoidle-v2

Changes in v2:
-1- Added support for clkout_x2 autogating
-2- Populated dpll_usb_clkdcoldo_ck's missing
clksel register

Rajendra Nayak (7):
  omap: clock: Check for enable/disable ops support
  omap3: dpll: Populate clkops for dpll1_ck
  omap: clock: Add allow_idle/deny_idle support in clkops
  omap: dpll: Add allow_idle/deny_idle support for all DPLL's
  omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot
  omap4: dpll: Add dpll api to control GATE_CTRL
  omap4: dpll: Enable auto gate control for all MX postdividers

 arch/arm/mach-omap2/clock.c             |   25 +++++++++++---
 arch/arm/mach-omap2/clock.h             |    5 +++
 arch/arm/mach-omap2/clock3xxx_data.c    |    4 +-
 arch/arm/mach-omap2/clock44xx_data.c    |   54 +++++++++++++++++------------
 arch/arm/mach-omap2/dpll3xxx.c          |   57 +++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/pm34xx.c            |   18 ++-------
 arch/arm/mach-omap2/pm44xx.c            |    4 ++
 arch/arm/plat-omap/clock.c              |   26 ++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    7 ++++
 9 files changed, 156 insertions(+), 44 deletions(-)

[PATCH v2 1/7] omap: clock: Check for enable/disable ops support

[Rajendra Nayak]

Check if enable/disable operations are supported for a given
clock node before attempting to call them.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.c |   14 +++++++++-----
 1 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 2a2f152..e0f017d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -261,7 +261,8 @@ void omap2_clk_disable(struct clk *clk)
 
 	pr_debug("clock: %s: disabling in hardware\n", clk->name);
 
-	clk->ops->disable(clk);
+	if (clk->ops && clk->ops->disable)
+		clk->ops->disable(clk);
 
 	if (clk->clkdm)
 		omap2_clkdm_clk_disable(clk->clkdm, clk);
@@ -312,10 +313,13 @@ int omap2_clk_enable(struct clk *clk)
 		}
 	}
 
-	ret = clk->ops->enable(clk);
-	if (ret) {
-		WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
-		goto oce_err3;
+	if (clk->ops && clk->ops->enable) {
+		ret = clk->ops->enable(clk);
+		if (ret) {
+			WARN(1, "clock: %s: could not enable: %d\n",
+			     clk->name, ret);
+			goto oce_err3;
+		}
 	}
 
 	return 0;
-- 
1.7.0.4

[PATCH v2 1/7] omap: clock: Check for enable/disable ops support

[Rajendra Nayak]

Check if enable/disable operations are supported for a given
clock node before attempting to call them.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.c |   14 +++++++++-----
 1 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 2a2f152..e0f017d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -261,7 +261,8 @@ void omap2_clk_disable(struct clk *clk)
 
 	pr_debug("clock: %s: disabling in hardware\n", clk->name);
 
-	clk->ops->disable(clk);
+	if (clk->ops && clk->ops->disable)
+		clk->ops->disable(clk);
 
 	if (clk->clkdm)
 		omap2_clkdm_clk_disable(clk->clkdm, clk);
@@ -312,10 +313,13 @@ int omap2_clk_enable(struct clk *clk)
 		}
 	}
 
-	ret = clk->ops->enable(clk);
-	if (ret) {
-		WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
-		goto oce_err3;
+	if (clk->ops && clk->ops->enable) {
+		ret = clk->ops->enable(clk);
+		if (ret) {
+			WARN(1, "clock: %s: could not enable: %d\n",
+			     clk->name, ret);
+			goto oce_err3;
+		}
 	}
 
 	return 0;
-- 
1.7.0.4

[PATCH v2 2/7] omap3: dpll: Populate clkops for dpll1_ck

[Rajendra Nayak]

DPLL1 on omap3 is very similar to the rest of
the non-core dpll's.
Hence populate clkops_omap3_noncore_dpll_ops
as the clkops for it, instead of the
currently populated clkops_null.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock3xxx_data.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 403a4a1..3e9d721 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -296,7 +296,7 @@ static struct dpll_data dpll1_dd = {
 
 static struct clk dpll1_ck = {
 	.name		= "dpll1_ck",
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap3_noncore_dpll_ops,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll1_dd,
 	.round_rate	= &omap2_dpll_round_rate,
-- 
1.7.0.4

[PATCH v2 2/7] omap3: dpll: Populate clkops for dpll1_ck

[Rajendra Nayak]

DPLL1 on omap3 is very similar to the rest of
the non-core dpll's.
Hence populate clkops_omap3_noncore_dpll_ops
as the clkops for it, instead of the
currently populated clkops_null.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock3xxx_data.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 403a4a1..3e9d721 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -296,7 +296,7 @@ static struct dpll_data dpll1_dd = {
 
 static struct clk dpll1_ck = {
 	.name		= "dpll1_ck",
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap3_noncore_dpll_ops,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll1_dd,
 	.round_rate	= &omap2_dpll_round_rate,
-- 
1.7.0.4

[PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Rajendra Nayak]

On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.

These function pointers can be populated for any clock
node which supports hardware level autogating.

Also add 2 new functions (omap_clk_enable_auotidle and
omap_clk_disable_autoidle) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/plat-omap/clock.c              |   26 ++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    6 ++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..6889c5a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
 	return ret;
 }
 
+void omap_clk_enable_autoidle(void)
+{
+	struct clk *c;
+
+	mutex_lock(&clocks_mutex);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->allow_idle)
+			c->ops->allow_idle(c);
+
+	mutex_unlock(&clocks_mutex);
+}
+
+void omap_clk_disable_autoidle(void)
+{
+	struct clk *c;
+
+	mutex_lock(&clocks_mutex);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->deny_idle)
+			c->ops->deny_idle(c);
+
+	mutex_unlock(&clocks_mutex);
+}
+
 /*
  * Low level helpers
  */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..167f1e0 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
 					       u8 *, u8 *);
 	void			(*find_companion)(struct clk *, void __iomem **,
 						  u8 *);
+	void			(*allow_idle)(struct clk *);
+	void			(*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle(void);
+extern void omap_clk_disable_autoidle(void);
 
 extern const struct clkops clkops_null;
 
-- 
1.7.0.4

[PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Rajendra Nayak]

On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.

These function pointers can be populated for any clock
node which supports hardware level autogating.

Also add 2 new functions (omap_clk_enable_auotidle and
omap_clk_disable_autoidle) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/plat-omap/clock.c              |   26 ++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    6 ++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..6889c5a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
 	return ret;
 }
 
+void omap_clk_enable_autoidle(void)
+{
+	struct clk *c;
+
+	mutex_lock(&clocks_mutex);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->allow_idle)
+			c->ops->allow_idle(c);
+
+	mutex_unlock(&clocks_mutex);
+}
+
+void omap_clk_disable_autoidle(void)
+{
+	struct clk *c;
+
+	mutex_lock(&clocks_mutex);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->deny_idle)
+			c->ops->deny_idle(c);
+
+	mutex_unlock(&clocks_mutex);
+}
+
 /*
  * Low level helpers
  */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..167f1e0 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
 					       u8 *, u8 *);
 	void			(*find_companion)(struct clk *, void __iomem **,
 						  u8 *);
+	void			(*allow_idle)(struct clk *);
+	void			(*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle(void);
+extern void omap_clk_disable_autoidle(void);
 
 extern const struct clkops clkops_null;
 
-- 
1.7.0.4

[PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Rajendra Nayak]

All OMAP3/4 dpll's support hardware level autogating.
Populate allow_idle/deny_idle function pointers for all
DPLL's in clkops.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.c          |    8 +++++++-
 arch/arm/mach-omap2/clock.h          |    1 +
 arch/arm/mach-omap2/clock3xxx_data.c |    2 +-
 arch/arm/mach-omap2/clock44xx_data.c |    2 +-
 4 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e0f017d..909e3c5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -377,10 +377,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 const struct clkops clkops_omap3_noncore_dpll_ops = {
 	.enable		= omap3_noncore_dpll_enable,
 	.disable	= omap3_noncore_dpll_disable,
+	.allow_idle	= omap3_dpll_allow_idle,
+	.deny_idle	= omap3_dpll_deny_idle,
 };
 
-#endif
+const struct clkops clkops_omap3_core_dpll_ops = {
+	.allow_idle	= omap3_dpll_allow_idle,
+	.deny_idle	= omap3_dpll_deny_idle,
+};
 
+#endif
 
 /*
  * OMAP2+ clock reset and init functions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 896584e..2a939e5 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -146,5 +146,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 #endif
 
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
+extern const struct clkops clkops_omap3_core_dpll_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 3e9d721..7cf89f8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -429,7 +429,7 @@ static struct dpll_data dpll3_dd = {
 
 static struct clk dpll3_ck = {
 	.name		= "dpll3_ck",
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap3_core_dpll_ops,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll3_dd,
 	.round_rate	= &omap2_dpll_round_rate,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index de9ec8d..b843b6e 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -443,7 +443,7 @@ static struct clk dpll_core_ck = {
 	.parent		= &sys_clkin_ck,
 	.dpll_data	= &dpll_core_dd,
 	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap3_core_dpll_ops,
 	.recalc		= &omap3_dpll_recalc,
 };
 
-- 
1.7.0.4

[PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Rajendra Nayak]

All OMAP3/4 dpll's support hardware level autogating.
Populate allow_idle/deny_idle function pointers for all
DPLL's in clkops.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.c          |    8 +++++++-
 arch/arm/mach-omap2/clock.h          |    1 +
 arch/arm/mach-omap2/clock3xxx_data.c |    2 +-
 arch/arm/mach-omap2/clock44xx_data.c |    2 +-
 4 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e0f017d..909e3c5 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -377,10 +377,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 const struct clkops clkops_omap3_noncore_dpll_ops = {
 	.enable		= omap3_noncore_dpll_enable,
 	.disable	= omap3_noncore_dpll_disable,
+	.allow_idle	= omap3_dpll_allow_idle,
+	.deny_idle	= omap3_dpll_deny_idle,
 };
 
-#endif
+const struct clkops clkops_omap3_core_dpll_ops = {
+	.allow_idle	= omap3_dpll_allow_idle,
+	.deny_idle	= omap3_dpll_deny_idle,
+};
 
+#endif
 
 /*
  * OMAP2+ clock reset and init functions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 896584e..2a939e5 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -146,5 +146,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 #endif
 
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
+extern const struct clkops clkops_omap3_core_dpll_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 3e9d721..7cf89f8 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -429,7 +429,7 @@ static struct dpll_data dpll3_dd = {
 
 static struct clk dpll3_ck = {
 	.name		= "dpll3_ck",
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap3_core_dpll_ops,
 	.parent		= &sys_ck,
 	.dpll_data	= &dpll3_dd,
 	.round_rate	= &omap2_dpll_round_rate,
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index de9ec8d..b843b6e 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -443,7 +443,7 @@ static struct clk dpll_core_ck = {
 	.parent		= &sys_clkin_ck,
 	.dpll_data	= &dpll_core_dd,
 	.init		= &omap2_init_dpll_parent,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap3_core_dpll_ops,
 	.recalc		= &omap3_dpll_recalc,
 };
 
-- 
1.7.0.4

[PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Rajendra Nayak]

Enable all dpll autoidle for OMAP4 and OMAP3 (OMAP3
already had dpll autoidle turned on, but was done
using low level cm accessor apis).
On OMAP3, replace the cm accessor apis doing this
with the now available support for doing this in
clock framework, using omap_clk_enable_autoidle().

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |   18 ++++--------------
 arch/arm/mach-omap2/pm44xx.c |    4 ++++
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..5a101fa 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -38,6 +38,7 @@
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
+#include <plat/clock.h>
 
 #include <asm/tlbflush.h>
 
@@ -814,21 +815,10 @@ static void __init prcm_setup_regs(void)
 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
 	/*
-	 * Set all plls to autoidle. This is needed until autoidle is
-	 * enabled by clockfw
+	 * Set all plls to autoidle.
+	 * TODO: Add all the iclk autoidles in here as well.
 	 */
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-			 MPU_MOD,
-			 CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-			 PLL_MOD,
-			 CM_AUTOIDLE);
-	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-			 PLL_MOD,
-			 CM_AUTOIDLE2);
+	omap_clk_enable_autoidle();
 
 	/*
 	 * Enable control of expternal oscillator through
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 76cfff2..8431d41 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -15,6 +15,7 @@
 #include <linux/list.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <plat/clock.h>
 
 #include "powerdomain.h"
 #include <mach/omap4-common.h>
@@ -111,6 +112,9 @@ static int __init omap4_pm_init(void)
 		pr_err("Failed to setup powerdomains\n");
 		goto err2;
 	}
+
+	/* Enable autoidle for all clks which support it*/
+	omap_clk_enable_autoidle();
 #endif
 
 #ifdef CONFIG_SUSPEND
-- 
1.7.0.4

[PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Rajendra Nayak]

Enable all dpll autoidle for OMAP4 and OMAP3 (OMAP3
already had dpll autoidle turned on, but was done
using low level cm accessor apis).
On OMAP3, replace the cm accessor apis doing this
with the now available support for doing this in
clock framework, using omap_clk_enable_autoidle().

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |   18 ++++--------------
 arch/arm/mach-omap2/pm44xx.c |    4 ++++
 2 files changed, 8 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..5a101fa 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -38,6 +38,7 @@
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
+#include <plat/clock.h>
 
 #include <asm/tlbflush.h>
 
@@ -814,21 +815,10 @@ static void __init prcm_setup_regs(void)
 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
 	/*
-	 * Set all plls to autoidle. This is needed until autoidle is
-	 * enabled by clockfw
+	 * Set all plls to autoidle.
+	 * TODO: Add all the iclk autoidles in here as well.
 	 */
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-			 MPU_MOD,
-			 CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-			 PLL_MOD,
-			 CM_AUTOIDLE);
-	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-			 PLL_MOD,
-			 CM_AUTOIDLE2);
+	omap_clk_enable_autoidle();
 
 	/*
 	 * Enable control of expternal oscillator through
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 76cfff2..8431d41 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -15,6 +15,7 @@
 #include <linux/list.h>
 #include <linux/err.h>
 #include <linux/slab.h>
+#include <plat/clock.h>
 
 #include "powerdomain.h"
 #include <mach/omap4-common.h>
@@ -111,6 +112,9 @@ static int __init omap4_pm_init(void)
 		pr_err("Failed to setup powerdomains\n");
 		goto err2;
 	}
+
+	/* Enable autoidle for all clks which support it*/
+	omap_clk_enable_autoidle();
 #endif
 
 #ifdef CONFIG_SUSPEND
-- 
1.7.0.4

[PATCH v2 6/7] omap4: dpll: Add dpll api to control GATE_CTRL

[Rajendra Nayak]

On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.

Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.

NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.h             |    3 ++
 arch/arm/mach-omap2/dpll3xxx.c          |   57 +++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    1 +
 3 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2a939e5..c450d69 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 int omap3_noncore_dpll_enable(struct clk *clk);
 void omap3_noncore_dpll_disable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f77022b..18912cf 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -34,6 +34,7 @@
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 #define DPLL_AUTOIDLE_DISABLE			0x0
@@ -612,3 +613,59 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 		rate = clk->parent->rate * 2;
 	return rate;
 }
+
+/* Supported only on OMAP4 */
+int omap4_dpllmx_gatectrl_read(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return -EINVAL;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	v &= mask;
+	v >>= __ffs(mask);
+
+	return v;
+}
+
+void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Clear the bit to allow gatectrl */
+	v &= ~mask;
+	__raw_writel(v, clk->clksel_reg);
+}
+
+void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Set the bit to deny gatectrl */
+	v |= mask;
+	__raw_writel(v, clk->clksel_reg);
+}
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 167f1e0..f2807dc 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -181,6 +181,7 @@ struct dpll_data {
 #define CLOCK_NO_IDLE_PARENT	(1 << 2)
 #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2		(1 << 5)
 
 /**
  * struct clk - OMAP struct clk
-- 
1.7.0.4

[PATCH v2 6/7] omap4: dpll: Add dpll api to control GATE_CTRL

[Rajendra Nayak]

On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.

Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.

NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.h             |    3 ++
 arch/arm/mach-omap2/dpll3xxx.c          |   57 +++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    1 +
 3 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2a939e5..c450d69 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 int omap3_noncore_dpll_enable(struct clk *clk);
 void omap3_noncore_dpll_disable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f77022b..18912cf 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -34,6 +34,7 @@
 #include "clock.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
+#include "cm-regbits-44xx.h"
 
 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
 #define DPLL_AUTOIDLE_DISABLE			0x0
@@ -612,3 +613,59 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 		rate = clk->parent->rate * 2;
 	return rate;
 }
+
+/* Supported only on OMAP4 */
+int omap4_dpllmx_gatectrl_read(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return -EINVAL;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	v &= mask;
+	v >>= __ffs(mask);
+
+	return v;
+}
+
+void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Clear the bit to allow gatectrl */
+	v &= ~mask;
+	__raw_writel(v, clk->clksel_reg);
+}
+
+void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Set the bit to deny gatectrl */
+	v |= mask;
+	__raw_writel(v, clk->clksel_reg);
+}
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 167f1e0..f2807dc 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -181,6 +181,7 @@ struct dpll_data {
 #define CLOCK_NO_IDLE_PARENT	(1 << 2)
 #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2		(1 << 5)
 
 /**
  * struct clk - OMAP struct clk
-- 
1.7.0.4

[PATCH v2 7/7] omap4: dpll: Enable auto gate control for all MX postdividers

[Rajendra Nayak]

Enable hardware gate control for all dpll MX and X2 postdividers.
This requires the allow_idle/deny_idle functions to be
populated for all clock nodes (mx/x2 post dividers) in
clkops.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.c          |    5 +++
 arch/arm/mach-omap2/clock.h          |    1 +
 arch/arm/mach-omap2/clock44xx_data.c |   52 +++++++++++++++++++--------------
 3 files changed, 36 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 909e3c5..6ec4c67 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -388,6 +388,11 @@ const struct clkops clkops_omap3_core_dpll_ops = {
 
 #endif
 
+const struct clkops clkops_omap4_dpllmx_ops = {
+	.allow_idle	= omap4_dpllmx_allow_gatectrl,
+	.deny_idle	= omap4_dpllmx_deny_gatectrl,
+};
+
 /*
  * OMAP2+ clock reset and init functions
  */
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index c450d69..0725a6a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -150,5 +150,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
 extern const struct clkops clkops_omap3_core_dpll_ops;
+extern const struct clkops clkops_omap4_dpllmx_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index b843b6e..dcbe105 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = {
 static struct clk dpll_abe_x2_ck = {
 	.name		= "dpll_abe_x2_ck",
 	.parent		= &dpll_abe_ck,
-	.ops		= &clkops_null,
+	.flags		= CLOCK_CLKOUTX2,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap3_clkoutx2_recalc,
+	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 };
 
 static const struct clksel_rate div31_1to31_rates[] = {
@@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = {
 	.clksel		= dpll_abe_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = {
 	.clksel		= dpll_abe_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_ABE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -450,6 +452,7 @@ static struct clk dpll_core_ck = {
 static struct clk dpll_core_x2_ck = {
 	.name		= "dpll_core_x2_ck",
 	.parent		= &dpll_core_ck,
+	.flags		= CLOCK_CLKOUTX2,
 	.ops		= &clkops_null,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
@@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = {
 	.clksel		= dpll_core_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_CORE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = {
 	.clksel		= dpll_abe_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = {
 static struct clk dpll_iva_x2_ck = {
 	.name		= "dpll_iva_x2_ck",
 	.parent		= &dpll_iva_ck,
+	.flags		= CLOCK_CLKOUTX2,
 	.ops		= &clkops_null,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
@@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = {
 	.clksel		= dpll_iva_m4x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_IVA,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = {
 	.clksel		= dpll_iva_m4x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_IVA,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
 	.clksel		= dpll_mpu_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_MPU,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = {
 	.clksel		= dpll_per_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = {
 static struct clk dpll_per_x2_ck = {
 	.name		= "dpll_per_x2_ck",
 	.parent		= &dpll_per_ck,
-	.ops		= &clkops_null,
+	.flags		= CLOCK_CLKOUTX2,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap3_clkoutx2_recalc,
+	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 };
 
 static const struct clksel dpll_per_m2x2_div[] = {
@@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = {
 static struct clk dpll_unipro_x2_ck = {
 	.name		= "dpll_unipro_x2_ck",
 	.parent		= &dpll_unipro_ck,
+	.flags		= CLOCK_CLKOUTX2,
 	.ops		= &clkops_null,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
@@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = {
 	.clksel		= dpll_unipro_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = {
 static struct clk dpll_usb_clkdcoldo_ck = {
 	.name		= "dpll_usb_clkdcoldo_ck",
 	.parent		= &dpll_usb_ck,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
+	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 	.recalc		= &followparent_recalc,
 };
 
@@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
 	.clksel		= dpll_usb_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_USB,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
-- 
1.7.0.4

[PATCH v2 7/7] omap4: dpll: Enable auto gate control for all MX postdividers

[Rajendra Nayak]

Enable hardware gate control for all dpll MX and X2 postdividers.
This requires the allow_idle/deny_idle functions to be
populated for all clock nodes (mx/x2 post dividers) in
clkops.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/clock.c          |    5 +++
 arch/arm/mach-omap2/clock.h          |    1 +
 arch/arm/mach-omap2/clock44xx_data.c |   52 +++++++++++++++++++--------------
 3 files changed, 36 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 909e3c5..6ec4c67 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -388,6 +388,11 @@ const struct clkops clkops_omap3_core_dpll_ops = {
 
 #endif
 
+const struct clkops clkops_omap4_dpllmx_ops = {
+	.allow_idle	= omap4_dpllmx_allow_gatectrl,
+	.deny_idle	= omap4_dpllmx_deny_gatectrl,
+};
+
 /*
  * OMAP2+ clock reset and init functions
  */
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index c450d69..0725a6a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -150,5 +150,6 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
 extern const struct clkops clkops_omap3_core_dpll_ops;
+extern const struct clkops clkops_omap4_dpllmx_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index b843b6e..dcbe105 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = {
 static struct clk dpll_abe_x2_ck = {
 	.name		= "dpll_abe_x2_ck",
 	.parent		= &dpll_abe_ck,
-	.ops		= &clkops_null,
+	.flags		= CLOCK_CLKOUTX2,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap3_clkoutx2_recalc,
+	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 };
 
 static const struct clksel_rate div31_1to31_rates[] = {
@@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = {
 	.clksel		= dpll_abe_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = {
 	.clksel		= dpll_abe_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M3_DPLL_ABE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -450,6 +452,7 @@ static struct clk dpll_core_ck = {
 static struct clk dpll_core_x2_ck = {
 	.name		= "dpll_core_x2_ck",
 	.parent		= &dpll_core_ck,
+	.flags		= CLOCK_CLKOUTX2,
 	.ops		= &clkops_null,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
@@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = {
 	.clksel		= dpll_core_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_CORE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = {
 	.clksel		= dpll_abe_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_ABE,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = {
 	.clksel		= dpll_core_m6x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_CORE,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = {
 static struct clk dpll_iva_x2_ck = {
 	.name		= "dpll_iva_x2_ck",
 	.parent		= &dpll_iva_ck,
+	.flags		= CLOCK_CLKOUTX2,
 	.ops		= &clkops_null,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
@@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = {
 	.clksel		= dpll_iva_m4x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_IVA,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = {
 	.clksel		= dpll_iva_m4x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_IVA,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
 	.clksel		= dpll_mpu_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_MPU,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = {
 	.clksel		= dpll_per_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = {
 static struct clk dpll_per_x2_ck = {
 	.name		= "dpll_per_x2_ck",
 	.parent		= &dpll_per_ck,
-	.ops		= &clkops_null,
+	.flags		= CLOCK_CLKOUTX2,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap3_clkoutx2_recalc,
+	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 };
 
 static const struct clksel dpll_per_m2x2_div[] = {
@@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_PER,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M4_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M5_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M6_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = {
 	.clksel		= dpll_per_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M7_DPLL_PER,
 	.clksel_mask	= OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = {
 static struct clk dpll_unipro_x2_ck = {
 	.name		= "dpll_unipro_x2_ck",
 	.parent		= &dpll_unipro_ck,
+	.flags		= CLOCK_CLKOUTX2,
 	.ops		= &clkops_null,
 	.recalc		= &omap3_clkoutx2_recalc,
 };
@@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = {
 	.clksel		= dpll_unipro_m2x2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
@@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = {
 static struct clk dpll_usb_clkdcoldo_ck = {
 	.name		= "dpll_usb_clkdcoldo_ck",
 	.parent		= &dpll_usb_ck,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
+	.clksel_reg	= OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 	.recalc		= &followparent_recalc,
 };
 
@@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
 	.clksel		= dpll_usb_m2_div,
 	.clksel_reg	= OMAP4430_CM_DIV_M2_DPLL_USB,
 	.clksel_mask	= OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
-	.ops		= &clkops_null,
+	.ops		= &clkops_omap4_dpllmx_ops,
 	.recalc		= &omap2_clksel_recalc,
 	.round_rate	= &omap2_clksel_round_rate,
 	.set_rate	= &omap2_clksel_set_rate,
-- 
1.7.0.4

Re: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Paul Walmsley]

Hi Rajendra

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> index fc62fb5..6889c5a 100644
> --- a/arch/arm/plat-omap/clock.c
> +++ b/arch/arm/plat-omap/clock.c
> @@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
>  	return ret;
>  }
>
> +void omap_clk_enable_autoidle(void)
> +{
> +	struct clk *c;
> +
> +	mutex_lock(&clocks_mutex);

With the current OMAP clock code, it isn't sufficient to use a mutex here.  
Your underlying functions have to read, modify, and write a register that 
is also touched by clock functions like clk_set_rate(), which take the 
clockfw spinlock and not the mutex.  This is potentially racy and could 
result in inconsistencies between the internal clock tree data and the 
hardware settings.

While it is true that these functions are currently only called during PM 
init, I'd rather not commit code that is subject to known races into the 
tree.

So, before applying this patch, the mutexes have been converted into 
spinlocks.  I would appreciate it if you could help test this.  Updated 
patch follows, which has been queued for 2.6.39 as part of the 
'clk_autoidle_a_2.6.39' branch of git://git.pwsan.com/linux-2.6.


- Paul

From: Rajendra Nayak <rnayak@ti.com>
Date: Thu, 10 Feb 2011 14:46:36 +0530
Subject: [PATCH] omap: clock: Add allow_idle/deny_idle support in clkops

On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.

These function pointers can be populated for any clock
node which supports hardware level autogating.

Also add 2 new functions (omap_clk_enable_auotidle and
omap_clk_disable_autoidle) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: use spinlock rather than mutex due to race]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/plat-omap/clock.c              |   28 ++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    6 ++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..0cdac8d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,34 @@ struct clk *omap_clk_get_by_name(const char *name)
 	return ret;
 }
 
+void omap_clk_enable_autoidle(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->allow_idle)
+			c->ops->allow_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
+void omap_clk_disable_autoidle(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->deny_idle)
+			c->ops->deny_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
 /*
  * Low level helpers
  */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..167f1e0f 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
 					       u8 *, u8 *);
 	void			(*find_companion)(struct clk *, void __iomem **,
 						  u8 *);
+	void			(*allow_idle)(struct clk *);
+	void			(*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle(void);
+extern void omap_clk_disable_autoidle(void);
 
 extern const struct clkops clkops_null;
 
-- 
1.7.2.3

[PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Paul Walmsley]

Hi Rajendra

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> index fc62fb5..6889c5a 100644
> --- a/arch/arm/plat-omap/clock.c
> +++ b/arch/arm/plat-omap/clock.c
> @@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
>  	return ret;
>  }
>
> +void omap_clk_enable_autoidle(void)
> +{
> +	struct clk *c;
> +
> +	mutex_lock(&clocks_mutex);

With the current OMAP clock code, it isn't sufficient to use a mutex here.  
Your underlying functions have to read, modify, and write a register that 
is also touched by clock functions like clk_set_rate(), which take the 
clockfw spinlock and not the mutex.  This is potentially racy and could 
result in inconsistencies between the internal clock tree data and the 
hardware settings.

While it is true that these functions are currently only called during PM 
init, I'd rather not commit code that is subject to known races into the 
tree.

So, before applying this patch, the mutexes have been converted into 
spinlocks.  I would appreciate it if you could help test this.  Updated 
patch follows, which has been queued for 2.6.39 as part of the 
'clk_autoidle_a_2.6.39' branch of git://git.pwsan.com/linux-2.6.


- Paul

From: Rajendra Nayak <rnayak@ti.com>
Date: Thu, 10 Feb 2011 14:46:36 +0530
Subject: [PATCH] omap: clock: Add allow_idle/deny_idle support in clkops

On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.

These function pointers can be populated for any clock
node which supports hardware level autogating.

Also add 2 new functions (omap_clk_enable_auotidle and
omap_clk_disable_autoidle) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul at pwsan.com: use spinlock rather than mutex due to race]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/plat-omap/clock.c              |   28 ++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    6 ++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..0cdac8d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,34 @@ struct clk *omap_clk_get_by_name(const char *name)
 	return ret;
 }
 
+void omap_clk_enable_autoidle(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->allow_idle)
+			c->ops->allow_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
+void omap_clk_disable_autoidle(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->deny_idle)
+			c->ops->deny_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
 /*
  * Low level helpers
  */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..167f1e0f 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
 					       u8 *, u8 *);
 	void			(*find_companion)(struct clk *, void __iomem **,
 						  u8 *);
+	void			(*allow_idle)(struct clk *);
+	void			(*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle(void);
+extern void omap_clk_disable_autoidle(void);
 
 extern const struct clkops clkops_null;
 
-- 
1.7.2.3

Re: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Paul Walmsley]

On Sat, 12 Feb 2011, Paul Walmsley wrote:

> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
> 
> > diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> > index fc62fb5..6889c5a 100644
> > --- a/arch/arm/plat-omap/clock.c
> > +++ b/arch/arm/plat-omap/clock.c
> > @@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
> >  	return ret;
> >  }
> >
> > +void omap_clk_enable_autoidle(void)

I also renamed these functions to

omap_clk_enable_autoidle_all()
omap_clk_disable_autoidle_all()

since they operate on all clocks.  Updated patch follows.


- Paul

From: Rajendra Nayak <rnayak@ti.com>
Date: Thu, 10 Feb 2011 14:46:36 +0530
Subject: [PATCH] OMAP: clock: Add allow_idle/deny_idle support in clkops

On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.

These function pointers can be populated for any clock
node which supports hardware level autogating.

Also add 2 new functions (omap_clk_enable_autoidle_all and
omap_clk_disable_autoidle_all) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: use spinlock rather than mutex due to race; renamed functions]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/plat-omap/clock.c              |   28 ++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    6 ++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..585533a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,34 @@ struct clk *omap_clk_get_by_name(const char *name)
 	return ret;
 }
 
+void omap_clk_enable_autoidle_all(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->allow_idle)
+			c->ops->allow_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
+void omap_clk_disable_autoidle_all(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->deny_idle)
+			c->ops->deny_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
 /*
  * Low level helpers
  */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..8534f71 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
 					       u8 *, u8 *);
 	void			(*find_companion)(struct clk *, void __iomem **,
 						  u8 *);
+	void			(*allow_idle)(struct clk *);
+	void			(*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle_all(void);
+extern void omap_clk_disable_autoidle_all(void);
 
 extern const struct clkops clkops_null;
 
-- 
1.7.2.3

[PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Paul Walmsley]

On Sat, 12 Feb 2011, Paul Walmsley wrote:

> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
> 
> > diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> > index fc62fb5..6889c5a 100644
> > --- a/arch/arm/plat-omap/clock.c
> > +++ b/arch/arm/plat-omap/clock.c
> > @@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char *name)
> >  	return ret;
> >  }
> >
> > +void omap_clk_enable_autoidle(void)

I also renamed these functions to

omap_clk_enable_autoidle_all()
omap_clk_disable_autoidle_all()

since they operate on all clocks.  Updated patch follows.


- Paul

From: Rajendra Nayak <rnayak@ti.com>
Date: Thu, 10 Feb 2011 14:46:36 +0530
Subject: [PATCH] OMAP: clock: Add allow_idle/deny_idle support in clkops

On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
support hardware level autogating which can be controlled from
software.
Support such functionality by adding two new function pointer
allow_idle and deny_idle in the clkops structure.

These function pointers can be populated for any clock
node which supports hardware level autogating.

Also add 2 new functions (omap_clk_enable_autoidle_all and
omap_clk_disable_autoidle_all) which can be called from
architecture specific PM core code, if hardware level
autogating (for all supported clock nodes) is to be
enabled or disabled.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul at pwsan.com: use spinlock rather than mutex due to race; renamed functions]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/plat-omap/clock.c              |   28 ++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |    6 ++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5..585533a 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -335,6 +335,34 @@ struct clk *omap_clk_get_by_name(const char *name)
 	return ret;
 }
 
+void omap_clk_enable_autoidle_all(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->allow_idle)
+			c->ops->allow_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
+void omap_clk_disable_autoidle_all(void)
+{
+	struct clk *c;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+
+	list_for_each_entry(c, &clocks, node)
+		if (c->ops->deny_idle)
+			c->ops->deny_idle(c);
+
+	spin_lock_irqrestore(&clockfw_lock, flags);
+}
+
 /*
  * Low level helpers
  */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8eb0ada..8534f71 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
 					       u8 *, u8 *);
 	void			(*find_companion)(struct clk *, void __iomem **,
 						  u8 *);
+	void			(*allow_idle)(struct clk *);
+	void			(*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern void omap_clk_enable_autoidle_all(void);
+extern void omap_clk_disable_autoidle_all(void);
 
 extern const struct clkops clkops_null;
 
-- 
1.7.2.3

Re: [PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> All OMAP3/4 dpll's support hardware level autogating.
> Populate allow_idle/deny_idle function pointers for all
> DPLL's in clkops.
> 
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Thanks, queued for 2.6.39.  Two questions though.  Was the OMAP4 
autogeneration script updated?  Also, any technical reason why you didn't 
add the OMAP2 DPLL?


- Paul

[PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> All OMAP3/4 dpll's support hardware level autogating.
> Populate allow_idle/deny_idle function pointers for all
> DPLL's in clkops.
> 
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Thanks, queued for 2.6.39.  Two questions though.  Was the OMAP4 
autogeneration script updated?  Also, any technical reason why you didn't 
add the OMAP2 DPLL?


- Paul

Re: [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> Enable all dpll autoidle for OMAP4 and OMAP3 (OMAP3
> already had dpll autoidle turned on, but was done
> using low level cm accessor apis).
> On OMAP3, replace the cm accessor apis doing this
> with the now available support for doing this in
> clock framework, using omap_clk_enable_autoidle().

I propose this patch instead.  What do you think?  Care to reply with a 
Reviewed-by: and/or Tested-by: ?


- Paul

From: Paul Walmsley <paul@pwsan.com>
Date: Sat, 12 Feb 2011 17:36:38 -0600
Subject: [PATCH] OMAP2+: clock: autoidle as many clocks as possible in OMAP2+-common PM code

Attempt to enable autoidle for as many clocks as possible in the
OMAP2+-common PM code.  Currently, this only enables DPLL autoidle for
OMAP3/4 DPLLs; but it should also eventually enable autoidle for other
clocks and the OMAP2 DPLL/APLLs.

Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
the pm34xx.c/pm44xx.c code, rather than the common PM code.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/pm.c     |    8 ++++++++
 arch/arm/mach-omap2/pm34xx.c |   17 -----------------
 2 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d5a102c..b507702 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -262,6 +262,14 @@ static int __init omap2_common_pm_late_init(void)
 	/* Smartreflex device init */
 	omap_devinit_smartreflex();
 
+	/*
+	 * Set all OMAP3/4 DPLLs to autoidle.
+	 * XXX TODO: Add all the iclk autoidles in here as well,
+	 * the OMAP2 DPLL, the OMAP2 APLLs, and the AUTOEXTCLKMODE
+	 * control here too.
+	 */
+	omap_clk_enable_autoidle_all();
+
 	return 0;
 }
 late_initcall(omap2_common_pm_late_init);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..1fe2e73 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void)
 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
 	/*
-	 * Set all plls to autoidle. This is needed until autoidle is
-	 * enabled by clockfw
-	 */
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-			 MPU_MOD,
-			 CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-			 PLL_MOD,
-			 CM_AUTOIDLE);
-	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-			 PLL_MOD,
-			 CM_AUTOIDLE2);
-
-	/*
 	 * Enable control of expternal oscillator through
 	 * sys_clkreq. In the long run clock framework should
 	 * take care of this.
-- 
1.7.2.3

[PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> Enable all dpll autoidle for OMAP4 and OMAP3 (OMAP3
> already had dpll autoidle turned on, but was done
> using low level cm accessor apis).
> On OMAP3, replace the cm accessor apis doing this
> with the now available support for doing this in
> clock framework, using omap_clk_enable_autoidle().

I propose this patch instead.  What do you think?  Care to reply with a 
Reviewed-by: and/or Tested-by: ?


- Paul

From: Paul Walmsley <paul@pwsan.com>
Date: Sat, 12 Feb 2011 17:36:38 -0600
Subject: [PATCH] OMAP2+: clock: autoidle as many clocks as possible in OMAP2+-common PM code

Attempt to enable autoidle for as many clocks as possible in the
OMAP2+-common PM code.  Currently, this only enables DPLL autoidle for
OMAP3/4 DPLLs; but it should also eventually enable autoidle for other
clocks and the OMAP2 DPLL/APLLs.

Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
the pm34xx.c/pm44xx.c code, rather than the common PM code.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/pm.c     |    8 ++++++++
 arch/arm/mach-omap2/pm34xx.c |   17 -----------------
 2 files changed, 8 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index d5a102c..b507702 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -262,6 +262,14 @@ static int __init omap2_common_pm_late_init(void)
 	/* Smartreflex device init */
 	omap_devinit_smartreflex();
 
+	/*
+	 * Set all OMAP3/4 DPLLs to autoidle.
+	 * XXX TODO: Add all the iclk autoidles in here as well,
+	 * the OMAP2 DPLL, the OMAP2 APLLs, and the AUTOEXTCLKMODE
+	 * control here too.
+	 */
+	omap_clk_enable_autoidle_all();
+
 	return 0;
 }
 late_initcall(omap2_common_pm_late_init);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..1fe2e73 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void)
 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
 	/*
-	 * Set all plls to autoidle. This is needed until autoidle is
-	 * enabled by clockfw
-	 */
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-			 MPU_MOD,
-			 CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-			 PLL_MOD,
-			 CM_AUTOIDLE);
-	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-			 PLL_MOD,
-			 CM_AUTOIDLE2);
-
-	/*
 	 * Enable control of expternal oscillator through
 	 * sys_clkreq. In the long run clock framework should
 	 * take care of this.
-- 
1.7.2.3

Re: [PATCH v2 6/7] omap4: dpll: Add dpll api to control GATE_CTRL

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> On OMAP4, the dpll post divider outputs (MX outputs)
> along with clockout_x2 output provide a way to allow/deny
> hardware level autogating.
> Allowing autoidle would mean that the hw would autogate
> this clock when there is no dependency for it.
> Denying idle would mean that this clock output will be
> forced to stay enabled.
> 
> Add dpll api's to read/allow/deny idle control
> for these dpll mx postdividers.
> 
> NOTE: The gatectrl bit set to 0 allows gatectrl,
> and the bit set to 1 denies gatectrl.
> 
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Thanks, I moved the OMAP4-specific code to a file that is only compiled in 
on OMAP4, and added some documentation, and queued it for 2.6.39 in the 
'clk_autoidle_a_2.6.39' branch here.  Updated version follows.


- Paul

From: Rajendra Nayak <rnayak@ti.com>
Date: Thu, 10 Feb 2011 14:46:39 +0530
Subject: [PATCH] OMAP4: DPLL: Add dpll api to control GATE_CTRL

On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.

Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.

NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: moved OMAP4-specific DPLL control code to
 mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/Makefile            |    2 +-
 arch/arm/mach-omap2/clock.h             |    3 +
 arch/arm/mach-omap2/dpll44xx.c          |   78 +++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |   14 +++++-
 4 files changed, 95 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-omap2/dpll44xx.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9eeabaf..c21b3ae 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -120,7 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(clock-common) clock3xxx.o \
 					   clock3517.o clock36xx.o \
 					   dpll3xxx.o clock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o \
-					   dpll3xxx.o
+					   dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2a939e5..c450d69 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 int omap3_noncore_dpll_enable(struct clk *clk);
 void omap3_noncore_dpll_disable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
new file mode 100644
index 0000000..94a3592
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -0,0 +1,78 @@
+/*
+ * OMAP4-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Rajendra Nayak
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm-regbits-44xx.h"
+
+/* Supported only on OMAP4 */
+int omap4_dpllmx_gatectrl_read(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return -EINVAL;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	v &= mask;
+	v >>= __ffs(mask);
+
+	return v;
+}
+
+void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Clear the bit to allow gatectrl */
+	v &= ~mask;
+	__raw_writel(v, clk->clksel_reg);
+}
+
+void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Set the bit to deny gatectrl */
+	v |= mask;
+	__raw_writel(v, clk->clksel_reg);
+}
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8534f71..dd09e61 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -175,12 +175,24 @@ struct dpll_data {
 
 #endif
 
-/* struct clk.flags possibilities */
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
 #define CLOCK_IDLE_CONTROL	(1 << 1)
 #define CLOCK_NO_IDLE_PARENT	(1 << 2)
 #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2		(1 << 5)
 
 /**
  * struct clk - OMAP struct clk
-- 
1.7.2.3

[PATCH v2 6/7] omap4: dpll: Add dpll api to control GATE_CTRL

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> On OMAP4, the dpll post divider outputs (MX outputs)
> along with clockout_x2 output provide a way to allow/deny
> hardware level autogating.
> Allowing autoidle would mean that the hw would autogate
> this clock when there is no dependency for it.
> Denying idle would mean that this clock output will be
> forced to stay enabled.
> 
> Add dpll api's to read/allow/deny idle control
> for these dpll mx postdividers.
> 
> NOTE: The gatectrl bit set to 0 allows gatectrl,
> and the bit set to 1 denies gatectrl.
> 
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Thanks, I moved the OMAP4-specific code to a file that is only compiled in 
on OMAP4, and added some documentation, and queued it for 2.6.39 in the 
'clk_autoidle_a_2.6.39' branch here.  Updated version follows.


- Paul

From: Rajendra Nayak <rnayak@ti.com>
Date: Thu, 10 Feb 2011 14:46:39 +0530
Subject: [PATCH] OMAP4: DPLL: Add dpll api to control GATE_CTRL

On OMAP4, the dpll post divider outputs (MX outputs)
along with clockout_x2 output provide a way to allow/deny
hardware level autogating.
Allowing autoidle would mean that the hw would autogate
this clock when there is no dependency for it.
Denying idle would mean that this clock output will be
forced to stay enabled.

Add dpll api's to read/allow/deny idle control
for these dpll mx postdividers.

NOTE: The gatectrl bit set to 0 allows gatectrl,
and the bit set to 1 denies gatectrl.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul at pwsan.com: moved OMAP4-specific DPLL control code to
 mach-omap2/dpll44xx.c; added some documentation for CLOCK_CLKOUTX2]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
 arch/arm/mach-omap2/Makefile            |    2 +-
 arch/arm/mach-omap2/clock.h             |    3 +
 arch/arm/mach-omap2/dpll44xx.c          |   78 +++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/clock.h |   14 +++++-
 4 files changed, 95 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-omap2/dpll44xx.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9eeabaf..c21b3ae 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -120,7 +120,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(clock-common) clock3xxx.o \
 					   clock3517.o clock36xx.o \
 					   dpll3xxx.o clock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)		+= $(clock-common) clock44xx_data.o \
-					   dpll3xxx.o
+					   dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)		+= opp2420_data.o
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2a939e5..c450d69 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 int omap3_noncore_dpll_enable(struct clk *clk);
 void omap3_noncore_dpll_disable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
new file mode 100644
index 0000000..94a3592
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -0,0 +1,78 @@
+/*
+ * OMAP4-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Rajendra Nayak
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm-regbits-44xx.h"
+
+/* Supported only on OMAP4 */
+int omap4_dpllmx_gatectrl_read(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return -EINVAL;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	v &= mask;
+	v >>= __ffs(mask);
+
+	return v;
+}
+
+void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Clear the bit to allow gatectrl */
+	v &= ~mask;
+	__raw_writel(v, clk->clksel_reg);
+}
+
+void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+{
+	u32 v;
+	u32 mask;
+
+	if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+		return;
+
+	mask = clk->flags & CLOCK_CLKOUTX2 ?
+			OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+			OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+	v = __raw_readl(clk->clksel_reg);
+	/* Set the bit to deny gatectrl */
+	v |= mask;
+	__raw_writel(v, clk->clksel_reg);
+}
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 8534f71..dd09e61 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -175,12 +175,24 @@ struct dpll_data {
 
 #endif
 
-/* struct clk.flags possibilities */
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
 #define CLOCK_IDLE_CONTROL	(1 << 1)
 #define CLOCK_NO_IDLE_PARENT	(1 << 2)
 #define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */
 #define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2		(1 << 5)
 
 /**
  * struct clk - OMAP struct clk
-- 
1.7.2.3

Re: [PATCH v2 7/7] omap4: dpll: Enable auto gate control for all MX postdividers

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> Enable hardware gate control for all dpll MX and X2 postdividers.
> This requires the allow_idle/deny_idle functions to be
> populated for all clock nodes (mx/x2 post dividers) in
> clkops.
> 
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Thanks, queued for 2.6.39 in the 'clk_autoidle_a_2.6.39' branch.  Has the 
OMAP4 clock data autogenerator script been updated?


- Paul

[PATCH v2 7/7] omap4: dpll: Enable auto gate control for all MX postdividers

[Paul Walmsley]

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> Enable hardware gate control for all dpll MX and X2 postdividers.
> This requires the allow_idle/deny_idle functions to be
> populated for all clock nodes (mx/x2 post dividers) in
> clkops.
> 
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>

Thanks, queued for 2.6.39 in the 'clk_autoidle_a_2.6.39' branch.  Has the 
OMAP4 clock data autogenerator script been updated?


- Paul

Re: [PATCH v2 0/7] clock/dpll autoidle support

[Paul Walmsley]

Hi Rajendra

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> OMAP has various clock nodes and dpll's
> which support hardware level autoidle.
> Enabling hardware level autoidle provides
> better power savings without much software
> intervention.
> 
> This series does the following to help enable
> hardware level autoidling using clock framework
> for some of these nodes on OMAP3 and OMAP4
> 
> -1- Adds support for providing function pointers
> for enabling/disabling autoidle in clkops
> -2- Populates these in clkops for all OMAP3/4 dplls
> -3- Enables all dpll autoidle late in boot on OMAP3 and OMAP4
> -4- Adds support for mx postdivider autoidle (present
> only on OMAP4) and enables it late in OMAP4 boot

I've reviewed and commented on all of these, asked a few questions, made a 
few changes, and queued the results for 2.6.39 in two branches of 
git://git.pwsan.com/linux-2.6:

clk_a_2.6.39 (for the autoidle-independent fixes)
clk_autoidle_a_2.6.39 (for the autoidle-specific code and data changes)

Both branches have been added to the 'integration-2.6.39' branch of 
git://git.pwsan.com/linux-integration, and are available as part of the 
tag "integration-2.6.39-20110212-004".


thanks,

- Paul

[PATCH v2 0/7] clock/dpll autoidle support

[Paul Walmsley]

Hi Rajendra

On Thu, 10 Feb 2011, Rajendra Nayak wrote:

> OMAP has various clock nodes and dpll's
> which support hardware level autoidle.
> Enabling hardware level autoidle provides
> better power savings without much software
> intervention.
> 
> This series does the following to help enable
> hardware level autoidling using clock framework
> for some of these nodes on OMAP3 and OMAP4
> 
> -1- Adds support for providing function pointers
> for enabling/disabling autoidle in clkops
> -2- Populates these in clkops for all OMAP3/4 dplls
> -3- Enables all dpll autoidle late in boot on OMAP3 and OMAP4
> -4- Adds support for mx postdivider autoidle (present
> only on OMAP4) and enables it late in OMAP4 boot

I've reviewed and commented on all of these, asked a few questions, made a 
few changes, and queued the results for 2.6.39 in two branches of 
git://git.pwsan.com/linux-2.6:

clk_a_2.6.39 (for the autoidle-independent fixes)
clk_autoidle_a_2.6.39 (for the autoidle-specific code and data changes)

Both branches have been added to the 'integration-2.6.39' branch of 
git://git.pwsan.com/linux-integration, and are available as part of the 
tag "integration-2.6.39-20110212-004".


thanks,

- Paul

RE: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Sunday, February 13, 2011 5:35 AM
> To: Rajendra Nayak
> Cc: linux-omap@vger.kernel.org; b-cousson@ti.com; khilman@ti.com;
santosh.shilimkar@ti.com; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle
support in clkops
>
> Hi Rajendra
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> > index fc62fb5..6889c5a 100644
> > --- a/arch/arm/plat-omap/clock.c
> > +++ b/arch/arm/plat-omap/clock.c
> > @@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char
*name)
> >  	return ret;
> >  }
> >
> > +void omap_clk_enable_autoidle(void)
> > +{
> > +	struct clk *c;
> > +
> > +	mutex_lock(&clocks_mutex);
>
> With the current OMAP clock code, it isn't sufficient to use a mutex
here.
> Your underlying functions have to read, modify, and write a register
that
> is also touched by clock functions like clk_set_rate(), which take the
> clockfw spinlock and not the mutex.  This is potentially racy and could
> result in inconsistencies between the internal clock tree data and the
> hardware settings.
>
> While it is true that these functions are currently only called during
PM
> init, I'd rather not commit code that is subject to known races into the
> tree.
>
> So, before applying this patch, the mutexes have been converted into
> spinlocks.  I would appreciate it if you could help test this.  Updated
> patch follows, which has been queued for 2.6.39 as part of the
> 'clk_autoidle_a_2.6.39' branch of git://git.pwsan.com/linux-2.6.

I used the clk_autoidle_a_2.6.39 branch and tested OFF mode
in suspend on 3430sdp.
I also tested CORE ret in suspend (using some out of tree patches)
on 4430sdp.

A couple of issues on the clk_autoidle_a_2.6.39 branch:
-1- There seems to be a missing fix which causes an abort
at boot on omap4
http://marc.info/?l=linux-omap&m=129768574027232&w=2
-2- There is a trivial fix (Patch below) needed which otherwise
breaks build

----
>From fbfb508e319021026402d743d76cac294bd02cfa Mon Sep 17 00:00:00 2001
From: Rajendra Nayak <rnayak@ti.com>
Date: Mon, 14 Feb 2011 17:47:15 +0530
Subject: [PATCH] OMAP: clock: Fix compile break with a
s/spin_lock_irq*/spin_unlock_irq*

Trivial fix to do a s/spin_lock_irqrestore/spin_unlock_irqrestore
and fix the compile break.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/plat-omap/clock.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 585533a..a2b069f 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -346,7 +346,7 @@ void omap_clk_enable_autoidle_all(void)
 		if (c->ops->allow_idle)
 			c->ops->allow_idle(c);

-	spin_lock_irqrestore(&clockfw_lock, flags);
+	spin_unlock_irqrestore(&clockfw_lock, flags);
 }

 void omap_clk_disable_autoidle_all(void)
@@ -360,7 +360,7 @@ void omap_clk_disable_autoidle_all(void)
 		if (c->ops->deny_idle)
 			c->ops->deny_idle(c);

-	spin_lock_irqrestore(&clockfw_lock, flags);
+	spin_unlock_irqrestore(&clockfw_lock, flags);
 }

 /*
-- 
1.7.0.4

Regards,
Rajendra

>
>
> - Paul
>
> From: Rajendra Nayak <rnayak@ti.com>
> Date: Thu, 10 Feb 2011 14:46:36 +0530
> Subject: [PATCH] omap: clock: Add allow_idle/deny_idle support in clkops
>
> On OMAP various clock nodes (dpll's, mx post dividers, interface clocks)
> support hardware level autogating which can be controlled from
> software.
> Support such functionality by adding two new function pointer
> allow_idle and deny_idle in the clkops structure.
>
> These function pointers can be populated for any clock
> node which supports hardware level autogating.
>
> Also add 2 new functions (omap_clk_enable_auotidle and
> omap_clk_disable_autoidle) which can be called from
> architecture specific PM core code, if hardware level
> autogating (for all supported clock nodes) is to be
> enabled or disabled.
>
> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
> [paul@pwsan.com: use spinlock rather than mutex due to race]
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/arm/plat-omap/clock.c              |   28
++++++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/clock.h |    6 ++++++
>  2 files changed, 34 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> index fc62fb5..0cdac8d 100644
> --- a/arch/arm/plat-omap/clock.c
> +++ b/arch/arm/plat-omap/clock.c
> @@ -335,6 +335,34 @@ struct clk *omap_clk_get_by_name(const char *name)
>  	return ret;
>  }
>
> +void omap_clk_enable_autoidle(void)
> +{
> +	struct clk *c;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&clockfw_lock, flags);
> +
> +	list_for_each_entry(c, &clocks, node)
> +		if (c->ops->allow_idle)
> +			c->ops->allow_idle(c);
> +
> +	spin_lock_irqrestore(&clockfw_lock, flags);
> +}
> +
> +void omap_clk_disable_autoidle(void)
> +{
> +	struct clk *c;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&clockfw_lock, flags);
> +
> +	list_for_each_entry(c, &clocks, node)
> +		if (c->ops->deny_idle)
> +			c->ops->deny_idle(c);
> +
> +	spin_lock_irqrestore(&clockfw_lock, flags);
> +}
> +
>  /*
>   * Low level helpers
>   */
> diff --git a/arch/arm/plat-omap/include/plat/clock.h
b/arch/arm/plat-omap/include/plat/clock.h
> index 8eb0ada..167f1e0f 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -25,6 +25,8 @@ struct clockdomain;
>   * @disable: fn ptr that enables the current clock in hardware
>   * @find_idlest: function returning the IDLEST register for the clock's
IP blk
>   * @find_companion: function returning the "companion" clk reg for the
clock
> + * @allow_idle: fn ptr that enables autoidle for the current clock in
hardware
> + * @deny_idle: fn ptr that disables autoidle for the current clock in
hardware
>   *
>   * A "companion" clk is an accompanying clock to the one being queried
>   * that must be enabled for the IP module connected to the clock to
> @@ -42,6 +44,8 @@ struct clkops {
>  					       u8 *, u8 *);
>  	void			(*find_companion)(struct clk *, void
__iomem **,
>  						  u8 *);
> +	void			(*allow_idle)(struct clk *);
> +	void			(*deny_idle)(struct clk *);
>  };
>
>  #ifdef CONFIG_ARCH_OMAP2PLUS
> @@ -292,6 +296,8 @@ extern void clk_init_cpufreq_table(struct
cpufreq_frequency_table **table);
>  extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table
**table);
>  #endif
>  extern struct clk *omap_clk_get_by_name(const char *name);
> +extern void omap_clk_enable_autoidle(void);
> +extern void omap_clk_disable_autoidle(void);
>
>  extern const struct clkops clkops_null;
>
> --
> 1.7.2.3

[PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Sunday, February 13, 2011 5:35 AM
> To: Rajendra Nayak
> Cc: linux-omap at vger.kernel.org; b-cousson at ti.com; khilman at ti.com;
santosh.shilimkar at ti.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle
support in clkops
>
> Hi Rajendra
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
> > index fc62fb5..6889c5a 100644
> > --- a/arch/arm/plat-omap/clock.c
> > +++ b/arch/arm/plat-omap/clock.c
> > @@ -335,6 +335,32 @@ struct clk *omap_clk_get_by_name(const char
*name)
> >  	return ret;
> >  }
> >
> > +void omap_clk_enable_autoidle(void)
> > +{
> > +	struct clk *c;
> > +
> > +	mutex_lock(&clocks_mutex);
>
> With the current OMAP clock code, it isn't sufficient to use a mutex
here.
> Your underlying functions have to read, modify, and write a register
that
> is also touched by clock functions like clk_set_rate(), which take the
> clockfw spinlock and not the mutex.  This is potentially racy and could
> result in inconsistencies between the internal clock tree data and the
> hardware settings.
>
> While it is true that these functions are currently only called during
PM
> init, I'd rather not commit code that is subject to known races into the
> tree.
>
> So, before applying this patch, the mutexes have been converted into
> spinlocks.  I would appreciate it if you could help test this.  Updated
> patch follows, which has been queued for 2.6.39 as part of the
> 'clk_autoidle_a_2.6.39' branch of git://git.pwsan.com/linux-2.6.

I used the clk_autoidle_a_2.6.39 branch and tested OFF mode
in suspend on 3430sdp.
I also tested CORE ret in suspend (using some out of tree patches)
on 4430sdp.

A couple of issues on the clk_autoidle_a_2.6.39 branch:
-1- There seems to be a missing fix which causes an abort
at boot on omap4
http://marc.info/?l=linux-omap&m=129768574027232&w=2
-2- There is a trivial fix (Patch below) needed which otherwise
breaks build

----

RE: [PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Sunday, February 13, 2011 5:58 AM
> To: Rajendra Nayak
> Cc: linux-omap@vger.kernel.org; b-cousson@ti.com; khilman@ti.com;
santosh.shilimkar@ti.com; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support
for all DPLL's
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > All OMAP3/4 dpll's support hardware level autogating.
> > Populate allow_idle/deny_idle function pointers for all
> > DPLL's in clkops.
> >
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>
> Thanks, queued for 2.6.39.  Two questions though.  Was the OMAP4
> autogeneration script updated?  Also, any technical reason why you
didn't
> add the OMAP2 DPLL?

Yes, the autogen scripts are updated, however they are
currently in a separate branch (dpll-gatectrl).
Will merge them into master soon.

No real reason for not adding OMAP2 dpll autoidle support.
Its just that I started off trying to do this for OMAP4, and
then found me touching some omap3 stuff and hence
also did it for OMAP3.(For some reason I thought there
were no DPLL's in OMAP2).

Regards,
Rajendra

>
>
> - Paul

[PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Sunday, February 13, 2011 5:58 AM
> To: Rajendra Nayak
> Cc: linux-omap at vger.kernel.org; b-cousson at ti.com; khilman at ti.com;
santosh.shilimkar at ti.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support
for all DPLL's
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > All OMAP3/4 dpll's support hardware level autogating.
> > Populate allow_idle/deny_idle function pointers for all
> > DPLL's in clkops.
> >
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>
> Thanks, queued for 2.6.39.  Two questions though.  Was the OMAP4
> autogeneration script updated?  Also, any technical reason why you
didn't
> add the OMAP2 DPLL?

Yes, the autogen scripts are updated, however they are
currently in a separate branch (dpll-gatectrl).
Will merge them into master soon.

No real reason for not adding OMAP2 dpll autoidle support.
Its just that I started off trying to do this for OMAP4, and
then found me touching some omap3 stuff and hence
also did it for OMAP3.(For some reason I thought there
were no DPLL's in OMAP2).

Regards,
Rajendra

>
>
> - Paul

RE: [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Sunday, February 13, 2011 6:13 AM
> To: Rajendra Nayak
> Cc: linux-omap@vger.kernel.org; b-cousson@ti.com; khilman@ti.com;
santosh.shilimkar@ti.com; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle
late at boot
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > Enable all dpll autoidle for OMAP4 and OMAP3 (OMAP3
> > already had dpll autoidle turned on, but was done
> > using low level cm accessor apis).
> > On OMAP3, replace the cm accessor apis doing this
> > with the now available support for doing this in
> > clock framework, using omap_clk_enable_autoidle().
>
> I propose this patch instead.  What do you think?  Care to reply with a
> Reviewed-by: and/or Tested-by: ?

I agree, this is a better approach than what I proposed
in my patch.
Since I already tested the clk_autoidle_a_2.6.39 branch
which also has this patch included, you can add a
Tested-by: Rajendra Nayak <rnayak@ti.com>

Regards,
Rajendra

>
>
> - Paul
>
> From: Paul Walmsley <paul@pwsan.com>
> Date: Sat, 12 Feb 2011 17:36:38 -0600
> Subject: [PATCH] OMAP2+: clock: autoidle as many clocks as possible in
OMAP2+-common PM code
>
> Attempt to enable autoidle for as many clocks as possible in the
> OMAP2+-common PM code.  Currently, this only enables DPLL autoidle for
> OMAP3/4 DPLLs; but it should also eventually enable autoidle for other
> clocks and the OMAP2 DPLL/APLLs.
>
> Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
> the pm34xx.c/pm44xx.c code, rather than the common PM code.
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/arm/mach-omap2/pm.c     |    8 ++++++++
>  arch/arm/mach-omap2/pm34xx.c |   17 -----------------
>  2 files changed, 8 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
> index d5a102c..b507702 100644
> --- a/arch/arm/mach-omap2/pm.c
> +++ b/arch/arm/mach-omap2/pm.c
> @@ -262,6 +262,14 @@ static int __init omap2_common_pm_late_init(void)
>  	/* Smartreflex device init */
>  	omap_devinit_smartreflex();
>
> +	/*
> +	 * Set all OMAP3/4 DPLLs to autoidle.
> +	 * XXX TODO: Add all the iclk autoidles in here as well,
> +	 * the OMAP2 DPLL, the OMAP2 APLLs, and the AUTOEXTCLKMODE
> +	 * control here too.
> +	 */
> +	omap_clk_enable_autoidle_all();
> +
>  	return 0;
>  }
>  late_initcall(omap2_common_pm_late_init);
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 2f864e4..1fe2e73 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void)
>  	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
>
>  	/*
> -	 * Set all plls to autoidle. This is needed until autoidle is
> -	 * enabled by clockfw
> -	 */
> -	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
> -			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
> -	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
> -			 MPU_MOD,
> -			 CM_AUTOIDLE2);
> -	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
> -			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
> -			 PLL_MOD,
> -			 CM_AUTOIDLE);
> -	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
> -			 PLL_MOD,
> -			 CM_AUTOIDLE2);
> -
> -	/*
>  	 * Enable control of expternal oscillator through
>  	 * sys_clkreq. In the long run clock framework should
>  	 * take care of this.
> --
> 1.7.2.3

[PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Sunday, February 13, 2011 6:13 AM
> To: Rajendra Nayak
> Cc: linux-omap at vger.kernel.org; b-cousson at ti.com; khilman at ti.com;
santosh.shilimkar at ti.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle
late at boot
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > Enable all dpll autoidle for OMAP4 and OMAP3 (OMAP3
> > already had dpll autoidle turned on, but was done
> > using low level cm accessor apis).
> > On OMAP3, replace the cm accessor apis doing this
> > with the now available support for doing this in
> > clock framework, using omap_clk_enable_autoidle().
>
> I propose this patch instead.  What do you think?  Care to reply with a
> Reviewed-by: and/or Tested-by: ?

I agree, this is a better approach than what I proposed
in my patch.
Since I already tested the clk_autoidle_a_2.6.39 branch
which also has this patch included, you can add a
Tested-by: Rajendra Nayak <rnayak@ti.com>

Regards,
Rajendra

>
>
> - Paul
>
> From: Paul Walmsley <paul@pwsan.com>
> Date: Sat, 12 Feb 2011 17:36:38 -0600
> Subject: [PATCH] OMAP2+: clock: autoidle as many clocks as possible in
OMAP2+-common PM code
>
> Attempt to enable autoidle for as many clocks as possible in the
> OMAP2+-common PM code.  Currently, this only enables DPLL autoidle for
> OMAP3/4 DPLLs; but it should also eventually enable autoidle for other
> clocks and the OMAP2 DPLL/APLLs.
>
> Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
> the pm34xx.c/pm44xx.c code, rather than the common PM code.
>
> Signed-off-by: Paul Walmsley <paul@pwsan.com>
> ---
>  arch/arm/mach-omap2/pm.c     |    8 ++++++++
>  arch/arm/mach-omap2/pm34xx.c |   17 -----------------
>  2 files changed, 8 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
> index d5a102c..b507702 100644
> --- a/arch/arm/mach-omap2/pm.c
> +++ b/arch/arm/mach-omap2/pm.c
> @@ -262,6 +262,14 @@ static int __init omap2_common_pm_late_init(void)
>  	/* Smartreflex device init */
>  	omap_devinit_smartreflex();
>
> +	/*
> +	 * Set all OMAP3/4 DPLLs to autoidle.
> +	 * XXX TODO: Add all the iclk autoidles in here as well,
> +	 * the OMAP2 DPLL, the OMAP2 APLLs, and the AUTOEXTCLKMODE
> +	 * control here too.
> +	 */
> +	omap_clk_enable_autoidle_all();
> +
>  	return 0;
>  }
>  late_initcall(omap2_common_pm_late_init);
> diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
> index 2f864e4..1fe2e73 100644
> --- a/arch/arm/mach-omap2/pm34xx.c
> +++ b/arch/arm/mach-omap2/pm34xx.c
> @@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void)
>  	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
>
>  	/*
> -	 * Set all plls to autoidle. This is needed until autoidle is
> -	 * enabled by clockfw
> -	 */
> -	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
> -			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
> -	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
> -			 MPU_MOD,
> -			 CM_AUTOIDLE2);
> -	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
> -			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
> -			 PLL_MOD,
> -			 CM_AUTOIDLE);
> -	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
> -			 PLL_MOD,
> -			 CM_AUTOIDLE2);
> -
> -	/*
>  	 * Enable control of expternal oscillator through
>  	 * sys_clkreq. In the long run clock framework should
>  	 * take care of this.
> --
> 1.7.2.3

RE: [PATCH v2 7/7] omap4: dpll: Enable auto gate control for all MX postdividers

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul@pwsan.com]
> Sent: Sunday, February 13, 2011 6:41 AM
> To: Rajendra Nayak
> Cc: linux-omap@vger.kernel.org; b-cousson@ti.com; khilman@ti.com;
santosh.shilimkar@ti.com; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v2 7/7] omap4: dpll: Enable auto gate control for
all MX postdividers
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > Enable hardware gate control for all dpll MX and X2 postdividers.
> > This requires the allow_idle/deny_idle functions to be
> > populated for all clock nodes (mx/x2 post dividers) in
> > clkops.
> >
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>
> Thanks, queued for 2.6.39 in the 'clk_autoidle_a_2.6.39' branch.  Has
the
> OMAP4 clock data autogenerator script been updated?

Yes, the autogen scripts are updated. Will merge the changes
in master.

Regards,
Rajendra
>
>
> - Paul

[PATCH v2 7/7] omap4: dpll: Enable auto gate control for all MX postdividers

[Rajendra Nayak]

Hi Paul,

> -----Original Message-----
> From: Paul Walmsley [mailto:paul at pwsan.com]
> Sent: Sunday, February 13, 2011 6:41 AM
> To: Rajendra Nayak
> Cc: linux-omap at vger.kernel.org; b-cousson at ti.com; khilman at ti.com;
santosh.shilimkar at ti.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH v2 7/7] omap4: dpll: Enable auto gate control for
all MX postdividers
>
> On Thu, 10 Feb 2011, Rajendra Nayak wrote:
>
> > Enable hardware gate control for all dpll MX and X2 postdividers.
> > This requires the allow_idle/deny_idle functions to be
> > populated for all clock nodes (mx/x2 post dividers) in
> > clkops.
> >
> > Signed-off-by: Rajendra Nayak <rnayak@ti.com>
>
> Thanks, queued for 2.6.39 in the 'clk_autoidle_a_2.6.39' branch.  Has
the
> OMAP4 clock data autogenerator script been updated?

Yes, the autogen scripts are updated. Will merge the changes
in master.

Regards,
Rajendra
>
>
> - Paul

RE: [PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Paul Walmsley]

On Mon, 14 Feb 2011, Rajendra Nayak wrote:

> A couple of issues on the clk_autoidle_a_2.6.39 branch:
> -1- There seems to be a missing fix which causes an abort
> at boot on omap4
> http://marc.info/?l=linux-omap&m=129768574027232&w=2

This should be fixed now that this branch is rebased on your first two 
clock patches.

> -2- There is a trivial fix (Patch below) needed which otherwise
> breaks build

Thanks for this, I've folded this fix into the original patch.


- Paul

[PATCH v2 3/7] omap: clock: Add allow_idle/deny_idle support in clkops

[Paul Walmsley]

On Mon, 14 Feb 2011, Rajendra Nayak wrote:

> A couple of issues on the clk_autoidle_a_2.6.39 branch:
> -1- There seems to be a missing fix which causes an abort
> at boot on omap4
> http://marc.info/?l=linux-omap&m=129768574027232&w=2

This should be fixed now that this branch is rebased on your first two 
clock patches.

> -2- There is a trivial fix (Patch below) needed which otherwise
> breaks build

Thanks for this, I've folded this fix into the original patch.


- Paul

RE: [PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Paul Walmsley]

On Mon, 14 Feb 2011, Rajendra Nayak wrote:

> Yes, the autogen scripts are updated, however they are
> currently in a separate branch (dpll-gatectrl).
> Will merge them into master soon.

OK, great.

> No real reason for not adding OMAP2 dpll autoidle support.
> Its just that I started off trying to do this for OMAP4, and
> then found me touching some omap3 stuff and hence
> also did it for OMAP3.(For some reason I thought there
> were no DPLL's in OMAP2).

That's fine, I have some patches in progress that enable this for the 
OMAP2 DPLL and APLLs.


- Paul

[PATCH v2 4/7] omap: dpll: Add allow_idle/deny_idle support for all DPLL's

[Paul Walmsley]

On Mon, 14 Feb 2011, Rajendra Nayak wrote:

> Yes, the autogen scripts are updated, however they are
> currently in a separate branch (dpll-gatectrl).
> Will merge them into master soon.

OK, great.

> No real reason for not adding OMAP2 dpll autoidle support.
> Its just that I started off trying to do this for OMAP4, and
> then found me touching some omap3 stuff and hence
> also did it for OMAP3.(For some reason I thought there
> were no DPLL's in OMAP2).

That's fine, I have some patches in progress that enable this for the 
OMAP2 DPLL and APLLs.


- Paul

RE: [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Paul Walmsley]

On Mon, 14 Feb 2011, Rajendra Nayak wrote:

> Since I already tested the clk_autoidle_a_2.6.39 branch
> which also has this patch included, you can add a
> Tested-by: Rajendra Nayak <rnayak@ti.com>

Thanks, added.


- Paul

[PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Paul Walmsley]

On Mon, 14 Feb 2011, Rajendra Nayak wrote:

> Since I already tested the clk_autoidle_a_2.6.39 branch
> which also has this patch included, you can add a
> Tested-by: Rajendra Nayak <rnayak@ti.com>

Thanks, added.


- Paul

RE: [PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Paul Walmsley]

Hi

After Rajendra's E-mail here:

   http://marc.info/?l=linux-arm-kernel&m=129785498406128&w=2

upon looking further, mach-omap2/pm.c is compiled in for !CONFIG_PM.  
This will be dealt with in a separate patch, but in the meantime, I 
propose we enable clock autoidle if CONFIG_OMAP_RESET_CLOCKS is set.  
(Really this config option should be called CONFIG_OMAP_DONT_BREAK_CLOCKFW 
or CONFIG_OMAP_MAKE_POWER_MANAGEMENT_WORK, but all that, too, is a matter 
for another patch.)

Here's what I'm proposing to use as a replacement; comments welcome.  The 
clk_autoidle_a_2.6.39 branch has been updated accordingly.


- Paul

From: Paul Walmsley <paul@pwsan.com>
Date: Mon, 14 Feb 2011 09:39:11 -0700
Subject: [PATCH] OMAP2+: clock: autoidle as many clocks as possible if CONFIG_OMAP_RESET_CLOCKS

Attempt to enable autoidle for as many clocks as possible in the
OMAP2+-common CONFIG_OMAP_RESET_CLOCKS code.  Currently, this only
enables DPLL autoidle for OMAP3/4 DPLLs; but future patches will
enable autoidle for other clocks and the OMAP2 DPLL/APLLs.

In the long run, we should probably get rid of
CONFIG_OMAP_RESET_CLOCKS, and unconditionally run the code that it
selects.  Otherwise, the state of the clock tree won't match the
hardware state - this could result in clocks being enabled or disabled
unpredictably.

Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
the pm34xx.c/pm44xx.c code.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |   17 -----------------
 arch/arm/plat-omap/clock.c   |    1 +
 2 files changed, 1 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..1fe2e73 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void)
 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
 	/*
-	 * Set all plls to autoidle. This is needed until autoidle is
-	 * enabled by clockfw
-	 */
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-			 MPU_MOD,
-			 CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-			 PLL_MOD,
-			 CM_AUTOIDLE);
-	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-			 PLL_MOD,
-			 CM_AUTOIDLE2);
-
-	/*
 	 * Enable control of expternal oscillator through
 	 * sys_clkreq. In the long run clock framework should
 	 * take care of this.
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 0ae0eae..2770ddd 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -446,6 +446,7 @@ static int __init clk_disable_unused(void)
 	return 0;
 }
 late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
 #endif
 
 int __init clk_init(struct clk_functions * custom_clocks)
-- 
1.7.2.3

[PATCH v2 5/7] omap: dpll: Enable all OMAP3/4 dpll autoidle late at boot

[Paul Walmsley]

Hi

After Rajendra's E-mail here:

   http://marc.info/?l=linux-arm-kernel&m=129785498406128&w=2

upon looking further, mach-omap2/pm.c is compiled in for !CONFIG_PM.  
This will be dealt with in a separate patch, but in the meantime, I 
propose we enable clock autoidle if CONFIG_OMAP_RESET_CLOCKS is set.  
(Really this config option should be called CONFIG_OMAP_DONT_BREAK_CLOCKFW 
or CONFIG_OMAP_MAKE_POWER_MANAGEMENT_WORK, but all that, too, is a matter 
for another patch.)

Here's what I'm proposing to use as a replacement; comments welcome.  The 
clk_autoidle_a_2.6.39 branch has been updated accordingly.


- Paul

From: Paul Walmsley <paul@pwsan.com>
Date: Mon, 14 Feb 2011 09:39:11 -0700
Subject: [PATCH] OMAP2+: clock: autoidle as many clocks as possible if CONFIG_OMAP_RESET_CLOCKS

Attempt to enable autoidle for as many clocks as possible in the
OMAP2+-common CONFIG_OMAP_RESET_CLOCKS code.  Currently, this only
enables DPLL autoidle for OMAP3/4 DPLLs; but future patches will
enable autoidle for other clocks and the OMAP2 DPLL/APLLs.

In the long run, we should probably get rid of
CONFIG_OMAP_RESET_CLOCKS, and unconditionally run the code that it
selects.  Otherwise, the state of the clock tree won't match the
hardware state - this could result in clocks being enabled or disabled
unpredictably.

Based on a patch by Rajendra Nayak <rnayak@ti.com> that did this in
the pm34xx.c/pm44xx.c code.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/pm34xx.c |   17 -----------------
 arch/arm/plat-omap/clock.c   |    1 +
 2 files changed, 1 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f864e4..1fe2e73 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -814,23 +814,6 @@ static void __init prcm_setup_regs(void)
 	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
 	/*
-	 * Set all plls to autoidle. This is needed until autoidle is
-	 * enabled by clockfw
-	 */
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-			 MPU_MOD,
-			 CM_AUTOIDLE2);
-	omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-			 PLL_MOD,
-			 CM_AUTOIDLE);
-	omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-			 PLL_MOD,
-			 CM_AUTOIDLE2);
-
-	/*
 	 * Enable control of expternal oscillator through
 	 * sys_clkreq. In the long run clock framework should
 	 * take care of this.
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 0ae0eae..2770ddd 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -446,6 +446,7 @@ static int __init clk_disable_unused(void)
 	return 0;
 }
 late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
 #endif
 
 int __init clk_init(struct clk_functions * custom_clocks)
-- 
1.7.2.3