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From: "Maciej W. Rozycki" <macro@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>, <linux-mips@linux-mips.org>,
	<stable@vger.kernel.org>
Subject: [PATCH 3/9] MIPS: Fix unaligned PC interpretation in `compute_return_epc'
Date: Tue, 6 Jun 2017 00:16:25 +0100	[thread overview]
Message-ID: <alpine.DEB.2.00.1706050247310.10864@tp.orcam.me.uk> (raw)
In-Reply-To: <alpine.DEB.2.00.1706040314270.10864@tp.orcam.me.uk>

Fix a regression introduced with commit fb6883e5809c ("MIPS: microMIPS:
Support handling of delay slots.") and defer to `__compute_return_epc'
if the ISA bit is set in EPC with non-MIPS16, non-microMIPS hardware,
which will then arrange for a SIGBUS due to an unaligned instruction
reference.  Returning EPC here is never correct as the API defines this
function's result to be either a negative error code on failure or one
of 0 and BRANCH_LIKELY_TAKEN on success.

Cc: stable@vger.kernel.org # 3.9+
Fixes: fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.")
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-compute-return-epc-unaligned.diff
Index: linux-sfr-test/arch/mips/include/asm/branch.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/branch.h	2016-10-22 10:43:21.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/branch.h	2016-11-08 04:55:33.724746000 +0000
@@ -74,10 +74,7 @@ static inline int compute_return_epc(str
 			return __microMIPS_compute_return_epc(regs);
 		if (cpu_has_mips16)
 			return __MIPS16e_compute_return_epc(regs);
-		return regs->cp0_epc;
-	}
-
-	if (!delay_slot(regs)) {
+	} else if (!delay_slot(regs)) {
 		regs->cp0_epc += 4;
 		return 0;
 	}

WARNING: multiple messages have this Message-ID (diff)
From: "Maciej W. Rozycki" <macro@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>,
	linux-mips@linux-mips.org, stable@vger.kernel.org
Subject: [PATCH 3/9] MIPS: Fix unaligned PC interpretation in `compute_return_epc'
Date: Tue, 6 Jun 2017 00:16:25 +0100	[thread overview]
Message-ID: <alpine.DEB.2.00.1706050247310.10864@tp.orcam.me.uk> (raw)
Message-ID: <20170605231625.ADm6kZQtY--Ml6xbUndoUkh2VG7ijWn5s9vnkoG_mpE@z> (raw)
In-Reply-To: <alpine.DEB.2.00.1706040314270.10864@tp.orcam.me.uk>

Fix a regression introduced with commit fb6883e5809c ("MIPS: microMIPS:
Support handling of delay slots.") and defer to `__compute_return_epc'
if the ISA bit is set in EPC with non-MIPS16, non-microMIPS hardware,
which will then arrange for a SIGBUS due to an unaligned instruction
reference.  Returning EPC here is never correct as the API defines this
function's result to be either a negative error code on failure or one
of 0 and BRANCH_LIKELY_TAKEN on success.

Cc: stable@vger.kernel.org # 3.9+
Fixes: fb6883e5809c ("MIPS: microMIPS: Support handling of delay slots.")
Signed-off-by: Maciej W. Rozycki <macro@imgtec.com>
---
linux-mips-compute-return-epc-unaligned.diff
Index: linux-sfr-test/arch/mips/include/asm/branch.h
===================================================================
--- linux-sfr-test.orig/arch/mips/include/asm/branch.h	2016-10-22 10:43:21.000000000 +0100
+++ linux-sfr-test/arch/mips/include/asm/branch.h	2016-11-08 04:55:33.724746000 +0000
@@ -74,10 +74,7 @@ static inline int compute_return_epc(str
 			return __microMIPS_compute_return_epc(regs);
 		if (cpu_has_mips16)
 			return __MIPS16e_compute_return_epc(regs);
-		return regs->cp0_epc;
-	}
-
-	if (!delay_slot(regs)) {
+	} else if (!delay_slot(regs)) {
 		regs->cp0_epc += 4;
 		return 0;
 	}

  parent reply	other threads:[~2017-06-05 23:16 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-05 23:14 [PATCH 0/9] Instruction emulation fixes Maciej W. Rozycki
2017-06-05 23:14 ` Maciej W. Rozycki
2017-06-05 23:15 ` [PATCH 1/9] MIPS: math-emu: Prevent wrong ISA mode instruction emulation Maciej W. Rozycki
2017-06-05 23:15   ` Maciej W. Rozycki
2017-06-05 23:15 ` [PATCH 2/9] MIPS: Actually decode JALX in `__compute_return_epc_for_insn' Maciej W. Rozycki
2017-06-05 23:15   ` Maciej W. Rozycki
2017-06-05 23:16 ` Maciej W. Rozycki [this message]
2017-06-05 23:16   ` [PATCH 3/9] MIPS: Fix unaligned PC interpretation in `compute_return_epc' Maciej W. Rozycki
2017-06-05 23:17 ` [PATCH 4/9] MIPS: Send SIGILL for BPOSGE32 in `__compute_return_epc_for_insn' Maciej W. Rozycki
2017-06-05 23:17   ` Maciej W. Rozycki
2017-06-08 13:11   ` Ralf Baechle
2017-06-08 15:03     ` Maciej W. Rozycki
2017-06-08 15:03       ` Maciej W. Rozycki
2017-06-05 23:17 ` [PATCH 5/9] MIPS: Rename `sigill_r6' to `sigill_r2r6' " Maciej W. Rozycki
2017-06-05 23:17   ` Maciej W. Rozycki
2017-06-06  6:06   ` Greg KH
2017-06-06 16:13     ` Maciej W. Rozycki
2017-06-06 16:13       ` Maciej W. Rozycki
2017-06-05 23:18 ` [PATCH 6/9] MIPS: Send SIGILL for linked branches " Maciej W. Rozycki
2017-06-05 23:18   ` Maciej W. Rozycki
2017-06-05 23:19 ` [PATCH 7/9] MIPS: Send SIGILL for R6 " Maciej W. Rozycki
2017-06-05 23:19   ` Maciej W. Rozycki
2017-06-05 23:19 ` [PATCH 8/9] MIPS: Fix a typo: s/preset/present/ in r2-to-r6 emulation error message Maciej W. Rozycki
2017-06-05 23:19   ` Maciej W. Rozycki
2017-06-05 23:20 ` [PATCH 9/9] MIPS: math-emu: For MFHC1/MTHC1 also return SIGILL right away Maciej W. Rozycki
2017-06-05 23:20   ` Maciej W. Rozycki

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