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From: Thomas Gleixner <tglx@linutronix.de>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>,
	"H. Peter Anvin" <h.peter.anvin@intel.com>,
	Ingo Molnar <mingo@elte.hu>,
	Peter Zijlstra <peterz@infradead.org>,
	Stephane Eranian <eranian@google.com>,
	Borislav Petkov <bp@suse.de>, Dave Hansen <dave.hansen@intel.com>,
	Nilay Vaish <nilayvaish@gmail.com>, Shaohua Li <shli@fb.com>,
	David Carrillo-Cisneros <davidcc@google.com>,
	Ravi V Shankar <ravi.v.shankar@intel.com>,
	Sai Prakhya <sai.praneeth.prakhya@intel.com>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID
Date: Mon, 17 Oct 2016 18:54:37 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.20.1610171853480.4991@nanos> (raw)
In-Reply-To: <20161017163524.GA1808@intel.com>

On Mon, 17 Oct 2016, Luck, Tony wrote:
> > > I wonder whether this is the proper abstraction level. We might as well do
> > > the following:
> > > 
> > > rdtresources[] = {
> > >      {
> > > 	.name	= "L3",
> > >      },
> > >      {
> > > 	.name	= "L3Data",
> > >      },
> > >      {
> > > 	.name	= "L3Code",
> > >      },
> > > 
> > > and enable either L3 or L3Data+L3Code. Not sure if that makes things
> > > simpler, but it's definitely worth a thought or two.
> > 
> > This way will be better than having cdp_enabled/capable for L3 and not
> > for L2.  And this doesn't change current userinterface design either,
> > I think.
> 
> User interface would change if you did this. The schemata file would
> look like this with CDP enabled:
> 
> # cat schemata
> L3Data:0=fffff;1=fffff;2=fffff;3=fffff
> L3Code:0=fffff;1=fffff;2=fffff;3=fffff
> 
> but that is easier to read than the current:
> 
> # cat schemata
> L3:0=fffff,fffff;1=fffff,fffff;2=fffff,fffff;3=fffff,fffff
> 
> which gives you no clue on which mask is code and which is data.

Indeed.
 
> We'd also end up with "info/L3Data/" and "info/L3code/"
> which would be a little redundant (since the files in each
> would contain the same numbers), but perhaps that is worth
> it to get the better schemata file.

I think so. Making the user interface more intuitive is always worth it.

Thanks,

	tglx

  parent reply	other threads:[~2016-10-17 17:01 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-15  2:12 [PATCH v4 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-17 10:31   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-17 10:32   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-17 10:48   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-17 10:57   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-17 11:03   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-17 13:45   ` Thomas Gleixner
2016-10-17 18:06     ` Fenghua Yu
2016-10-17 16:35       ` Luck, Tony
2016-10-17 16:43         ` Yu, Fenghua
2016-10-17 20:20           ` Luck, Tony
2016-10-17 16:54         ` Thomas Gleixner [this message]
2016-10-17 16:53       ` Thomas Gleixner
2016-10-17 17:02       ` Thomas Gleixner
2016-10-17 21:22         ` Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-17 14:44   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-17 19:35   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-17 19:46   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-17 21:14   ` Thomas Gleixner
2016-10-17 21:50     ` Luck, Tony
2016-10-17 22:52       ` Thomas Gleixner
2016-10-17 23:00         ` Luck, Tony
2016-10-17 23:03           ` Thomas Gleixner
2016-10-17 23:10             ` Luck, Tony
2016-10-17 23:25               ` Thomas Gleixner
2016-10-18  1:18     ` Fenghua Yu
2016-10-17 23:20       ` Thomas Gleixner
2016-10-17 23:37         ` Luck, Tony
2016-10-18  2:56           ` Fenghua Yu
2016-10-18 10:44           ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-17 21:27   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-17 22:01   ` Thomas Gleixner
2016-10-17 22:17     ` Luck, Tony
2016-10-15  2:12 ` [PATCH v4 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-17 22:35   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu

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