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From: Thomas Gleixner <tglx@linutronix.de>
To: "Luck, Tony" <tony.luck@intel.com>
Cc: "Yu, Fenghua" <fenghua.yu@intel.com>,
	"Anvin, H Peter" <h.peter.anvin@intel.com>,
	Ingo Molnar <mingo@elte.hu>,
	Peter Zijlstra <peterz@infradead.org>,
	Stephane Eranian <eranian@google.com>,
	Borislav Petkov <bp@suse.de>,
	"Hansen, Dave" <dave.hansen@intel.com>,
	Nilay Vaish <nilayvaish@gmail.com>, Shaohua Li <shli@fb.com>,
	David Carrillo-Cisneros <davidcc@google.com>,
	"Shankar, Ravi V" <ravi.v.shankar@intel.com>,
	"Prakhya, Sai Praneeth" <sai.praneeth.prakhya@intel.com>,
	Vikas Shivappa <vikas.shivappa@linux.intel.com>,
	linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: RE: [PATCH v4 13/18] x86/intel_rdt: Add mkdir to resctrl file system
Date: Tue, 18 Oct 2016 01:03:09 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.20.1610180059380.6407@nanos> (raw)
In-Reply-To: <3908561D78D1C84285E8C5FCA982C28F3A20010B@ORSMSX114.amr.corp.intel.com>

On Mon, 17 Oct 2016, Luck, Tony wrote:
> > So how are we going to deal with that in the schematas? Assume the L3=16
> > and L2=8 case(no CDP). So effectively any write of L2 to CLOSID=0 will
> > affect the setting of L2 in CLOSID=8.
> >
> > Will the code tell the user that L2 cannot be set for CLOSID >= 8? 
> >
> > Will it print the setting of CLOSID - 8 for CLOSID >= 8 when you read the
> > schemata file of CLOSID >= 8?
> 
> The default and first 7 directories you make will have lines in schemata for
> both L3 and L2.  The next 8 will just have L3 (and won't let you add L2).
> 
> > And of course this becomes very interesting when CLOSID 1 is deleted, then
> > what happens to CLOSID 9? Not to talk about the case when CLOSID 1 is
> > reused again.
> 
> Deleting CLOSID 1 won't affect CLOSID 9.

How so? CLOSID 9 is using CLOSID 1 L2 settings. Are we just keeping the L2
setting of CLOSID 1 around and do not reset it to default?

>  When you make a new directory that gets allocated CLOSID 1, it will have
>  both L3 and L2 lines.

Now CLOSID 1 is reused and reset to all 1's per default and even if not
then the operator will set a new L2 value and therefor wreckaging CLOSID 9.

Thanks,

	tglx

  reply	other threads:[~2016-10-17 23:05 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-15  2:12 [PATCH v4 00/18] Intel Cache Allocation Technology Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 01/18] Documentation, ABI: Add a document entry for cache id Fenghua Yu
2016-10-17 10:31   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 02/18] cacheinfo: Introduce " Fenghua Yu
2016-10-17 10:32   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 03/18] x86, intel_cacheinfo: Enable cache id in x86 Fenghua Yu
2016-10-17 10:48   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 04/18] x86/intel_rdt: Feature discovery Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 05/18] Documentation, x86: Documentation for Intel resource allocation user interface Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 06/18] x86/intel_rdt: Add CONFIG, Makefile, and basic initialization Fenghua Yu
2016-10-17 10:57   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery Fenghua Yu
2016-10-17 11:03   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters from CPUID Fenghua Yu
2016-10-17 13:45   ` Thomas Gleixner
2016-10-17 18:06     ` Fenghua Yu
2016-10-17 16:35       ` Luck, Tony
2016-10-17 16:43         ` Yu, Fenghua
2016-10-17 20:20           ` Luck, Tony
2016-10-17 16:54         ` Thomas Gleixner
2016-10-17 16:53       ` Thomas Gleixner
2016-10-17 17:02       ` Thomas Gleixner
2016-10-17 21:22         ` Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 09/18] x86/cqm: Move PQR_ASSOC management code into generic code used by both CQM and CAT Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 10/18] x86/intel_rdt: Build structures for each resource based on cache topology Fenghua Yu
2016-10-17 14:44   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 11/18] x86/intel_rdt: Add basic resctrl filesystem support Fenghua Yu
2016-10-17 19:35   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 12/18] x86/intel_rdt: Add "info" files to resctrl file system Fenghua Yu
2016-10-17 19:46   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 13/18] x86/intel_rdt: Add mkdir " Fenghua Yu
2016-10-17 21:14   ` Thomas Gleixner
2016-10-17 21:50     ` Luck, Tony
2016-10-17 22:52       ` Thomas Gleixner
2016-10-17 23:00         ` Luck, Tony
2016-10-17 23:03           ` Thomas Gleixner [this message]
2016-10-17 23:10             ` Luck, Tony
2016-10-17 23:25               ` Thomas Gleixner
2016-10-18  1:18     ` Fenghua Yu
2016-10-17 23:20       ` Thomas Gleixner
2016-10-17 23:37         ` Luck, Tony
2016-10-18  2:56           ` Fenghua Yu
2016-10-18 10:44           ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 14/18] x86/intel_rdt: Add cpus file Fenghua Yu
2016-10-17 21:27   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 15/18] x86/intel_rdt: Add tasks files Fenghua Yu
2016-10-17 22:01   ` Thomas Gleixner
2016-10-17 22:17     ` Luck, Tony
2016-10-15  2:12 ` [PATCH v4 16/18] x86/intel_rdt: Add schemata file Fenghua Yu
2016-10-17 22:35   ` Thomas Gleixner
2016-10-15  2:12 ` [PATCH v4 17/18] x86/intel_rdt: Add scheduler hook Fenghua Yu
2016-10-15  2:12 ` [PATCH v4 18/18] MAINTAINERS: Add maintainer for Intel RDT resource allocation Fenghua Yu

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