From: Thomas Gleixner <tglx@linutronix.de> To: Kyle Huey <me@kylehuey.com> Cc: "Robert O'Callahan" <robert@ocallahan.org>, "Andy Lutomirski" <luto@kernel.org>, "Ingo Molnar" <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Jeff Dike" <jdike@addtoit.com>, "Richard Weinberger" <richard@nod.at>, "Alexander Viro" <viro@zeniv.linux.org.uk>, "Shuah Khan" <shuah@kernel.org>, "Dave Hansen" <dave.hansen@linux.intel.com>, "Borislav Petkov" <bp@suse.de>, "Peter Zijlstra" <peterz@infradead.org>, "Boris Ostrovsky" <boris.ostrovsky@oracle.com>, "Len Brown" <len.brown@intel.com>, "Dmitry Safonov" <dsafonov@virtuozzo.com>, "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>, "David Matlack" <dmatlack@google.com>, "Nadav Amit" <nadav.amit@gmail.com>, "Andi Kleen" <andi@firstfloor.org>, linux-kernel@vger.kernel.org, user-mode-linux-devel@lists.sourceforge.net, user-mode-linux-user@lists.sourceforge.net, linux-kselftest@vger.kernel.org, kvm@vger.kernel.org Subject: Re: [PATCH v15 6/9] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Date: Tue, 14 Mar 2017 21:36:22 +0100 (CET) [thread overview] Message-ID: <alpine.DEB.2.20.1703142112200.3770@nanos> (raw) In-Reply-To: <20170311194702.28754-7-khuey@kylehuey.com> On Sat, 11 Mar 2017, Kyle Huey wrote: > static void init_intel_misc_features(struct cpuinfo_x86 *c) > { > u64 msr; > > + if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) > + return; > + > + msr = 0; > + wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); > + this_cpu_write(msr_misc_features_shadow, msr); > + > if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { > if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) > set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); > } > > probe_xeon_phi_r3mwait(c); The way you are doing it breaks the ring3 mwait feature because you overwrite the R3MWAIT bit the first time you update the MSR on context switch. > } What you really want is to fixup the r3mwait part: static void probe_xeon_phi_r3mwait(c) { .... if (ring3mwait_disabled) return; set_cpu_cap(c, X86_FEATURE_RING3MWAIT); this_cpu_or(msr_misc_features_shadow, 1UL << MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); if (c == &boot_cpu_data) ELF_HWCAP2 |= HWCAP2_RING3MWAIT; } and have a function for cpuid fault: static void init_cpuid_fault(c) { if (rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) return; if ((msr & MSR_PLATFORM_INFO_CPUID_FAULT)) set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); } and then do: static void init_intel_misc_features(struct cpuinfo_x86 *c) { u64 msr; if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) return; /* Clear all MISC features */ this_cpu_write(msr_misc_features_shadow, 0); /* Check the features and update the shadow control bits */ init_cpuid_fault(c); probe_xeon_phi_r3mwait(c); msr_write(MSR_MISC_FEATURE_ENABLES, this_cpu_read(msr_misc_features_shadow); } Hmm? Thanks, tglx
WARNING: multiple messages have this Message-ID (diff)
From: Thomas Gleixner <tglx@linutronix.de> To: Kyle Huey <me@kylehuey.com> Cc: "Robert O'Callahan" <robert@ocallahan.org>, "Andy Lutomirski" <luto@kernel.org>, "Ingo Molnar" <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>, x86@kernel.org, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Jeff Dike" <jdike@addtoit.com>, "Richard Weinberger" <richard@nod.at>, "Alexander Viro" <viro@zeniv.linux.org.uk>, "Shuah Khan" <shuah@kernel.org>, "Dave Hansen" <dave.hansen@linux.intel.com>, "Borislav Petkov" <bp@suse.de>, "Peter Zijlstra" <peterz@infradead.org>, "Boris Ostrovsky" <boris.ostrovsky@oracle.com>, "Len Brown" <len.brown@intel.com>, "Dmitry Safonov" <dsafonov@virtuozzo.com>, "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>, "David Matlack" <dmatlack@google.com>, "Nadav Amit" <nadav.amit@gmail.com> Subject: Re: [PATCH v15 6/9] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Date: Tue, 14 Mar 2017 21:36:22 +0100 (CET) [thread overview] Message-ID: <alpine.DEB.2.20.1703142112200.3770@nanos> (raw) In-Reply-To: <20170311194702.28754-7-khuey@kylehuey.com> On Sat, 11 Mar 2017, Kyle Huey wrote: > static void init_intel_misc_features(struct cpuinfo_x86 *c) > { > u64 msr; > > + if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) > + return; > + > + msr = 0; > + wrmsrl(MSR_MISC_FEATURES_ENABLES, msr); > + this_cpu_write(msr_misc_features_shadow, msr); > + > if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) { > if (msr & MSR_PLATFORM_INFO_CPUID_FAULT) > set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); > } > > probe_xeon_phi_r3mwait(c); The way you are doing it breaks the ring3 mwait feature because you overwrite the R3MWAIT bit the first time you update the MSR on context switch. > } What you really want is to fixup the r3mwait part: static void probe_xeon_phi_r3mwait(c) { .... if (ring3mwait_disabled) return; set_cpu_cap(c, X86_FEATURE_RING3MWAIT); this_cpu_or(msr_misc_features_shadow, 1UL << MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT); if (c == &boot_cpu_data) ELF_HWCAP2 |= HWCAP2_RING3MWAIT; } and have a function for cpuid fault: static void init_cpuid_fault(c) { if (rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) return; if ((msr & MSR_PLATFORM_INFO_CPUID_FAULT)) set_cpu_cap(c, X86_FEATURE_CPUID_FAULT); } and then do: static void init_intel_misc_features(struct cpuinfo_x86 *c) { u64 msr; if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr)) return; /* Clear all MISC features */ this_cpu_write(msr_misc_features_shadow, 0); /* Check the features and update the shadow control bits */ init_cpuid_fault(c); probe_xeon_phi_r3mwait(c); msr_write(MSR_MISC_FEATURE_ENABLES, this_cpu_read(msr_misc_features_shadow); } Hmm? Thanks, tglx
next prev parent reply other threads:[~2017-03-14 20:38 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-11 19:46 [PATCH v15 0/9] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Kyle Huey 2017-03-11 19:46 ` Kyle Huey 2017-03-11 19:46 ` [PATCH v15 1/9] x86/arch_prctl/64: Use SYSCALL_DEFINE2 to define sys_arch_prctl Kyle Huey 2017-03-11 19:46 ` Kyle Huey 2017-03-11 19:46 ` [PATCH v15 2/9] x86/arch_prctl/64: Rename do_arch_prctl to do_arch_prctl_64 Kyle Huey 2017-03-11 19:46 ` Kyle Huey 2017-03-11 19:46 ` [PATCH v15 3/9] x86/arch_prctl: Add do_arch_prctl_common Kyle Huey 2017-03-11 19:46 ` Kyle Huey 2017-03-11 19:46 ` [PATCH v15 4/9] x86/syscalls/32: Wire up arch_prctl on x86-32 Kyle Huey 2017-03-11 19:46 ` Kyle Huey 2017-03-11 19:46 ` [PATCH v15 5/9] x86/cpufeature: Detect CPUID faulting support Kyle Huey 2017-03-11 19:46 ` Kyle Huey 2017-03-11 19:46 ` [PATCH v15 6/9] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Kyle Huey 2017-03-11 19:46 ` Kyle Huey 2017-03-14 20:36 ` Thomas Gleixner [this message] 2017-03-14 20:36 ` Thomas Gleixner 2017-03-20 8:01 ` Kyle Huey 2017-03-20 8:01 ` Kyle Huey 2017-03-14 21:47 ` Linus Torvalds 2017-03-14 21:47 ` Linus Torvalds 2017-03-16 11:09 ` Michael Ellerman 2017-03-16 11:09 ` Michael Ellerman 2017-03-16 14:30 ` Kyle Huey 2017-03-16 14:30 ` Kyle Huey 2017-03-16 18:23 ` Linus Torvalds 2017-03-16 18:23 ` Linus Torvalds 2017-03-17 7:56 ` Geert Uytterhoeven 2017-03-17 7:56 ` Geert Uytterhoeven 2017-03-11 19:47 ` [PATCH v15 7/9] x86/arch_prctl: Selftest for ARCH_[GET|SET]_CPUID Kyle Huey 2017-03-11 19:47 ` Kyle Huey 2017-03-11 19:47 ` [PATCH v15 8/9] KVM: x86: virtualize cpuid faulting Kyle Huey 2017-03-11 19:47 ` Kyle Huey 2017-03-11 19:47 ` [PATCH v15 9/9] x86/arch_prctl: Rename 'code' argument to 'option' Kyle Huey 2017-03-11 19:47 ` Kyle Huey 2017-03-14 20:07 ` Thomas Gleixner 2017-03-14 20:07 ` Thomas Gleixner 2017-03-20 8:01 ` Kyle Huey 2017-03-20 8:01 ` Kyle Huey
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