From: Vince Weaver <vincent.weaver@maine.edu>
To: "H. Taheri" <rezato@gmail.com>
Cc: "linux-perf-users@vger.kernel.org" <linux-perf-users@vger.kernel.org>
Subject: Re: Not getting PMC events on Broadwell-EX
Date: Tue, 8 Aug 2017 09:53:24 -0400 (EDT) [thread overview]
Message-ID: <alpine.DEB.2.20.1708080951470.8732@macbook-air> (raw)
In-Reply-To: <B10BA2E5-3BC7-481F-8EC7-DFEB229526EC@vmware.com>
On Mon, 7 Aug 2017, H. Taheri wrote:
> I am getting 0s, or <not supported>, or <not counted> for events that
> are supposed to work on this processor. For example, according to Intel
> documentation, L2_RQSTS.MISS and L2_RQSTS.REFERENCES are supported on
> this processor with event code 0x24 and unit masks 0x3f and 0xff. But
> when I run perf stat (also with -d -d -d to see if the built-in command
> options can get the cache stats), I get:
Check your docs on the order for the fields.
You can use libpfm4 as so:
./check_events L2_RQSTS:MISS
Requested Event: L2_RQSTS:MISS
Actual Event:
bdw_ep::L2_RQSTS:MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0
PMU : Intel Broadwell EP
IDX : 421527583
Codes : 0x533f24
You want the umask first, then the event (0x3f24)
Vince
next prev parent reply other threads:[~2017-08-08 13:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-08 4:37 Not getting PMC events on Broadwell-EX H. Taheri
2017-08-08 13:53 ` Vince Weaver [this message]
2017-08-08 16:32 ` Andi Kleen
2017-08-08 16:54 ` Reza Taheri
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