* Not getting PMC events on Broadwell-EX
@ 2017-08-08 4:37 H. Taheri
2017-08-08 13:53 ` Vince Weaver
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: H. Taheri @ 2017-08-08 4:37 UTC (permalink / raw)
To: linux-perf-users
Hi experts,
I am getting 0s, or <not supported>, or <not counted> for events that are supposed to work on this processor. For example, according to Intel documentation, L2_RQSTS.MISS and L2_RQSTS.REFERENCES are supported on this processor with event code 0x24 and unit masks 0x3f and 0xff. But when I run perf stat (also with -d -d -d to see if the built-in command options can get the cache stats), I get:
[root@prme-perf-broadwell-2 intel]# perf stat -d -d -d -e cycles -e instructions -e r24ff -e r243f sleep 10
Performance counter stats for 'sleep 10':
295,132 cycles
676,801 instructions # 2.29 insn per cycle
0 r24ff
0 r243f
175,865 L1-dcache-loads
12,686 L1-dcache-load-misses # 7.21% of all L1-dcache hits (67.93%)
<not counted> LLC-loads (0.00%)
<not counted> LLC-load-misses (0.00%)
<not supported> L1-icache-loads
<not counted> L1-icache-load-misses (0.00%)
<not counted> dTLB-loads (0.00%)
<not counted> dTLB-load-misses (0.00%)
<not counted> iTLB-loads (0.00%)
<not counted> iTLB-load-misses (0.00%)
<not supported> L1-dcache-prefetches
<not supported> L1-dcache-prefetch-misses
10.001308205 seconds time elapsed
This is the /proc/cpuinfo from the guest:
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 79
model name : Intel(R) Xeon(R) CPU E7-8890 v4 @ 2.20GHz
stepping : 1
microcode : 0xb00001d
cpu MHz : 1200.031
cache size : 30720 KB
physical id : 0
siblings : 48
core id : 0
cpu cores : 24
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 20
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch ida arat epb pln pts dtherm intel_pt tpr_shadow vnmi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm rdseed adx smap xsaveopt cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local
bogomips : 4388.87
clflush size : 64
cache_alignment : 64
address sizes : 46 bits physical, 48 bits virtual
power management:
Thanks,
Reza
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Not getting PMC events on Broadwell-EX
2017-08-08 4:37 Not getting PMC events on Broadwell-EX H. Taheri
@ 2017-08-08 13:53 ` Vince Weaver
2017-08-08 16:32 ` Andi Kleen
2017-08-08 16:54 ` Reza Taheri
2 siblings, 0 replies; 4+ messages in thread
From: Vince Weaver @ 2017-08-08 13:53 UTC (permalink / raw)
To: H. Taheri; +Cc: linux-perf-users
On Mon, 7 Aug 2017, H. Taheri wrote:
> I am getting 0s, or <not supported>, or <not counted> for events that
> are supposed to work on this processor. For example, according to Intel
> documentation, L2_RQSTS.MISS and L2_RQSTS.REFERENCES are supported on
> this processor with event code 0x24 and unit masks 0x3f and 0xff. But
> when I run perf stat (also with -d -d -d to see if the built-in command
> options can get the cache stats), I get:
Check your docs on the order for the fields.
You can use libpfm4 as so:
./check_events L2_RQSTS:MISS
Requested Event: L2_RQSTS:MISS
Actual Event:
bdw_ep::L2_RQSTS:MISS:k=1:u=1:e=0:i=0:c=0:t=0:intx=0:intxcp=0
PMU : Intel Broadwell EP
IDX : 421527583
Codes : 0x533f24
You want the umask first, then the event (0x3f24)
Vince
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Not getting PMC events on Broadwell-EX
2017-08-08 4:37 Not getting PMC events on Broadwell-EX H. Taheri
2017-08-08 13:53 ` Vince Weaver
@ 2017-08-08 16:32 ` Andi Kleen
2017-08-08 16:54 ` Reza Taheri
2 siblings, 0 replies; 4+ messages in thread
From: Andi Kleen @ 2017-08-08 16:32 UTC (permalink / raw)
To: H. Taheri; +Cc: linux-perf-users
"H. Taheri" <rezato@gmail.com> writes:
> I am getting 0s, or <not supported>, or <not counted> for events that are supposed to work on this processor. For example, according to Intel documentation, L2_RQSTS.MISS and L2_RQSTS.REFERENCES are supported on this processor with event code 0x24 and unit masks 0x3f and 0xff. But when I run perf stat (also with -d -d -d to see if the built-in command options can get the cache stats), I get:
>
> [root@prme-perf-broadwell-2 intel]# perf stat -d -d -d -e cycles -e instructions -e r24ff -e r243f sleep 10
You're missing -a, so it's only measuring sleep itself.
-Andi
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: Not getting PMC events on Broadwell-EX
2017-08-08 4:37 Not getting PMC events on Broadwell-EX H. Taheri
2017-08-08 13:53 ` Vince Weaver
2017-08-08 16:32 ` Andi Kleen
@ 2017-08-08 16:54 ` Reza Taheri
2 siblings, 0 replies; 4+ messages in thread
From: Reza Taheri @ 2017-08-08 16:54 UTC (permalink / raw)
To: linux-perf-users
I see my mistake now. It really is umask followed by eventsel, even if the perf-stat man page says:
-e, --event=
Select the PMU event. Selection can be:
• a symbolic event name (use perf list to list all events)
• a raw PMU event (eventsel+umask) in the form of rNNN where NNN is a hexadecimal event descriptor.
I ran the following to collect the programmable version of retired_inst and unhalted core_cycles, and the outputs match the fixed counters.
[root@prme-perf-broadwell-2 ~]# perf stat -a -e cycles -e instructions -e r03c -e r00c0 sleep 10
Performance counter stats for 'system wide':
2,505,518,503 cycles
925,145,561 instructions # 0.37 insn per cycle
2,526,621,584 r03c
929,277,772 r00c0
10.001461051 seconds time elapsed
Thanks,
Reza
^ permalink raw reply [flat|nested] 4+ messages in thread
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2017-08-08 4:37 Not getting PMC events on Broadwell-EX H. Taheri
2017-08-08 13:53 ` Vince Weaver
2017-08-08 16:32 ` Andi Kleen
2017-08-08 16:54 ` Reza Taheri
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