* [Qemu-devel] [PATCH v6 01/26] tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 02/26] tcg: Dynamically allocate TCGOps Richard Henderson
` (29 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
These are now trivial sets and tests against NULL. Unwrap.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.h | 4 ---
tcg/tcg.h | 9 -------
target/alpha/translate.c | 22 ++++++++--------
target/arm/translate-a64.c | 35 +++++++++++-------------
target/arm/translate.c | 29 ++++++++++----------
target/cris/translate.c | 2 +-
target/hppa/translate.c | 63 ++++++++++++++++++++++----------------------
target/i386/translate.c | 13 +++++----
target/m68k/translate.c | 14 +++++-----
target/mips/translate.c | 2 +-
target/nios2/translate.c | 6 ++---
target/ppc/translate.c | 2 +-
target/s390x/translate.c | 42 ++++++++++++++---------------
target/sh4/translate.c | 2 +-
target/sparc/translate.c | 2 +-
target/tilegx/translate.c | 10 +++----
target/unicore32/translate.c | 4 +--
tcg/tcg.c | 4 +--
18 files changed, 122 insertions(+), 143 deletions(-)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 3129159907..ca07b32b65 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -807,8 +807,6 @@ void tcg_gen_lookup_and_goto_ptr(void);
#define tcg_global_mem_new tcg_global_mem_new_i32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
#define tcg_temp_free tcg_temp_free_i32
-#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
-#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
#else
@@ -817,8 +815,6 @@ void tcg_gen_lookup_and_goto_ptr(void);
#define tcg_global_mem_new tcg_global_mem_new_i64
#define tcg_temp_local_new() tcg_temp_local_new_i64()
#define tcg_temp_free tcg_temp_free_i64
-#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
-#define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
#endif
diff --git a/tcg/tcg.h b/tcg/tcg.h
index cb7b329876..c21194c858 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -428,15 +428,6 @@ typedef TCGv_ptr TCGv_env;
#error Unhandled TARGET_LONG_BITS value
#endif
-/* See the comment before tcgv_i32_temp. */
-#define TCGV_UNUSED_I32(x) (x = (TCGv_i32)NULL)
-#define TCGV_UNUSED_I64(x) (x = (TCGv_i64)NULL)
-#define TCGV_UNUSED_PTR(x) (x = (TCGv_ptr)NULL)
-
-#define TCGV_IS_UNUSED_I32(x) ((x) == (TCGv_i32)NULL)
-#define TCGV_IS_UNUSED_I64(x) ((x) == (TCGv_i64)NULL)
-#define TCGV_IS_UNUSED_PTR(x) ((x) == (TCGv_ptr)NULL)
-
/* call flags */
/* Helper does not read globals (either directly or through an exception). It
implies TCG_CALL_NO_WRITE_GLOBALS. */
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 629f35ec8e..73a1b5e63e 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -156,7 +156,7 @@ void alpha_translate_init(void)
static TCGv load_zero(DisasContext *ctx)
{
- if (TCGV_IS_UNUSED_I64(ctx->zero)) {
+ if (!ctx->zero) {
ctx->zero = tcg_const_i64(0);
}
return ctx->zero;
@@ -164,7 +164,7 @@ static TCGv load_zero(DisasContext *ctx)
static TCGv dest_sink(DisasContext *ctx)
{
- if (TCGV_IS_UNUSED_I64(ctx->sink)) {
+ if (!ctx->sink) {
ctx->sink = tcg_temp_new();
}
return ctx->sink;
@@ -172,18 +172,18 @@ static TCGv dest_sink(DisasContext *ctx)
static void free_context_temps(DisasContext *ctx)
{
- if (!TCGV_IS_UNUSED_I64(ctx->sink)) {
+ if (ctx->sink) {
tcg_gen_discard_i64(ctx->sink);
tcg_temp_free(ctx->sink);
- TCGV_UNUSED_I64(ctx->sink);
+ ctx->sink = NULL;
}
- if (!TCGV_IS_UNUSED_I64(ctx->zero)) {
+ if (ctx->zero) {
tcg_temp_free(ctx->zero);
- TCGV_UNUSED_I64(ctx->zero);
+ ctx->zero = NULL;
}
- if (!TCGV_IS_UNUSED_I64(ctx->lit)) {
+ if (ctx->lit) {
tcg_temp_free(ctx->lit);
- TCGV_UNUSED_I64(ctx->lit);
+ ctx->lit = NULL;
}
}
@@ -2948,9 +2948,9 @@ static int alpha_tr_init_disas_context(DisasContextBase *dcbase,
/* Similarly for flush-to-zero. */
ctx->tb_ftz = -1;
- TCGV_UNUSED_I64(ctx->zero);
- TCGV_UNUSED_I64(ctx->sink);
- TCGV_UNUSED_I64(ctx->lit);
+ ctx->zero = NULL;
+ ctx->sink = NULL;
+ ctx->lit = NULL;
/* Bound the number of insns to execute to those left on the page. */
if (in_superpage(ctx, ctx->base.pc_first)) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 625ef2dfd2..460bab5987 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -405,10 +405,7 @@ static void unallocated_encoding(DisasContext *s)
static void init_tmp_a64_array(DisasContext *s)
{
#ifdef CONFIG_DEBUG_TCG
- int i;
- for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) {
- TCGV_UNUSED_I64(s->tmp_a64[i]);
- }
+ memset(s->tmp_a64, 0, sizeof(s->tmp_a64));
#endif
s->tmp_a64_count = 0;
}
@@ -6276,7 +6273,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
return;
}
- TCGV_UNUSED_PTR(fpst);
+ fpst = NULL;
break;
case 0xc: /* FMAXNMP */
case 0xd: /* FADDP */
@@ -6371,7 +6368,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tcg_res);
}
- if (!TCGV_IS_UNUSED_PTR(fpst)) {
+ if (fpst) {
tcg_temp_free_ptr(fpst);
}
}
@@ -6387,7 +6384,7 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
bool is_u, int size, int shift)
{
bool extended_result = false;
- bool round = !TCGV_IS_UNUSED_I64(tcg_rnd);
+ bool round = tcg_rnd != NULL;
int ext_lshift = 0;
TCGv_i64 tcg_src_hi;
@@ -6533,7 +6530,7 @@ static void handle_scalar_simd_shri(DisasContext *s,
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
} else {
- TCGV_UNUSED_I64(tcg_round);
+ tcg_round = NULL;
}
tcg_rn = read_fp_dreg(s, rn);
@@ -6649,7 +6646,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
} else {
- TCGV_UNUSED_I64(tcg_round);
+ tcg_round = NULL;
}
for (i = 0; i < elements; i++) {
@@ -8239,8 +8236,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
tcg_fpstatus = get_fpstatus_ptr();
} else {
- TCGV_UNUSED_I32(tcg_rmode);
- TCGV_UNUSED_PTR(tcg_fpstatus);
+ tcg_rmode = NULL;
+ tcg_fpstatus = NULL;
}
if (size == 3) {
@@ -8360,7 +8357,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
} else {
- TCGV_UNUSED_I64(tcg_round);
+ tcg_round = NULL;
}
for (i = 0; i < elements; i++) {
@@ -8502,7 +8499,7 @@ static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
uint64_t round_const = 1ULL << (shift - 1);
tcg_round = tcg_const_i64(round_const);
} else {
- TCGV_UNUSED_I64(tcg_round);
+ tcg_round = NULL;
}
for (i = 0; i < elements; i++) {
@@ -9168,7 +9165,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
if (opcode >= 0x58) {
fpst = get_fpstatus_ptr();
} else {
- TCGV_UNUSED_PTR(fpst);
+ fpst = NULL;
}
if (!fp_access_check(s)) {
@@ -9305,7 +9302,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
}
}
- if (!TCGV_IS_UNUSED_PTR(fpst)) {
+ if (fpst) {
tcg_temp_free_ptr(fpst);
}
}
@@ -10226,13 +10223,13 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
if (need_fpstatus) {
tcg_fpstatus = get_fpstatus_ptr();
} else {
- TCGV_UNUSED_PTR(tcg_fpstatus);
+ tcg_fpstatus = NULL;
}
if (need_rmode) {
tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
gen_helper_set_rmode(tcg_rmode, tcg_rmode, cpu_env);
} else {
- TCGV_UNUSED_I32(tcg_rmode);
+ tcg_rmode = NULL;
}
if (size == 3) {
@@ -10593,7 +10590,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
if (is_fp) {
fpst = get_fpstatus_ptr();
} else {
- TCGV_UNUSED_PTR(fpst);
+ fpst = NULL;
}
if (size == 3) {
@@ -10917,7 +10914,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
}
}
- if (!TCGV_IS_UNUSED_PTR(fpst)) {
+ if (fpst) {
tcg_temp_free_ptr(fpst);
}
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4afb0c86ec..0b74ce7dec 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2165,8 +2165,8 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
tmp3 = tcg_const_i32((insn & 1) << 5);
break;
default:
- TCGV_UNUSED_I32(tmp2);
- TCGV_UNUSED_I32(tmp3);
+ tmp2 = NULL;
+ tmp3 = NULL;
}
gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3);
tcg_temp_free_i32(tmp3);
@@ -4935,7 +4935,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
}
} else /* size == 0 */ {
if (load) {
- TCGV_UNUSED_I32(tmp2);
+ tmp2 = NULL;
for (n = 0; n < 4; n++) {
tmp = tcg_temp_new_i32();
gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
@@ -6639,11 +6639,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tmp = neon_load_reg(rn, 1);
neon_store_scratch(2, tmp);
}
- TCGV_UNUSED_I32(tmp3);
+ tmp3 = NULL;
for (pass = 0; pass < 2; pass++) {
if (src1_wide) {
neon_load_reg64(cpu_V0, rn + pass);
- TCGV_UNUSED_I32(tmp);
+ tmp = NULL;
} else {
if (pass == 1 && rd == rn) {
tmp = neon_load_scratch(2);
@@ -6656,7 +6656,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
if (src2_wide) {
neon_load_reg64(cpu_V1, rm + pass);
- TCGV_UNUSED_I32(tmp2);
+ tmp2 = NULL;
} else {
if (pass == 1 && rd == rm) {
tmp2 = neon_load_scratch(2);
@@ -7074,7 +7074,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
if (rm & 1) {
return 1;
}
- TCGV_UNUSED_I32(tmp2);
+ tmp2 = NULL;
for (pass = 0; pass < 2; pass++) {
neon_load_reg64(cpu_V0, rm + pass);
tmp = tcg_temp_new_i32();
@@ -7213,7 +7213,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
if (neon_2rm_is_float_op(op)) {
tcg_gen_ld_f32(cpu_F0s, cpu_env,
neon_reg_offset(rm, pass));
- TCGV_UNUSED_I32(tmp);
+ tmp = NULL;
} else {
tmp = neon_load_reg(rm, pass);
}
@@ -8662,7 +8662,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
rn = (insn >> 16) & 0xf;
tmp = load_reg(s, rn);
} else {
- TCGV_UNUSED_I32(tmp);
+ tmp = NULL;
}
rd = (insn >> 12) & 0xf;
switch(op1) {
@@ -9501,7 +9501,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
/* compute total size */
loaded_base = 0;
- TCGV_UNUSED_I32(loaded_var);
+ loaded_var = NULL;
n = 0;
for(i=0;i<16;i++) {
if (insn & (1 << i))
@@ -10043,7 +10043,7 @@ static int disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_gen_addi_i32(addr, addr, -offset);
}
- TCGV_UNUSED_I32(loaded_var);
+ loaded_var = NULL;
for (i = 0; i < 16; i++) {
if ((insn & (1 << i)) == 0)
continue;
@@ -11324,7 +11324,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
} else if (op != 0xf) { /* mvn doesn't read its first operand */
tmp = load_reg(s, rd);
} else {
- TCGV_UNUSED_I32(tmp);
+ tmp = NULL;
}
tmp2 = load_reg(s, rm);
@@ -11655,7 +11655,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
tcg_gen_addi_i32(addr, addr, 4);
}
}
- TCGV_UNUSED_I32(tmp);
+ tmp = NULL;
if (insn & (1 << 8)) {
if (insn & (1 << 11)) {
/* pop pc */
@@ -11800,8 +11800,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
case 12:
{
/* load/store multiple */
- TCGv_i32 loaded_var;
- TCGV_UNUSED_I32(loaded_var);
+ TCGv_i32 loaded_var = NULL;
rn = (insn >> 8) & 0x7;
addr = load_reg(s, rn);
for (i = 0; i < 8; i++) {
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 2831419845..74822ed31f 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -2603,7 +2603,7 @@ static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
gen_load(dc, tmp32, addr, 4, 0);
} else {
- TCGV_UNUSED(tmp32);
+ tmp32 = NULL;
}
tcg_temp_free(addr);
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 53aa1f88c4..31d9a2a31b 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -125,7 +125,7 @@ void hppa_translate_init(void)
int i;
- TCGV_UNUSED(cpu_gr[0]);
+ cpu_gr[0] = NULL;
for (i = 1; i < 32; i++) {
cpu_gr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUHPPAState, gr[i]),
@@ -140,28 +140,31 @@ void hppa_translate_init(void)
static DisasCond cond_make_f(void)
{
- DisasCond r = { .c = TCG_COND_NEVER };
- TCGV_UNUSED(r.a0);
- TCGV_UNUSED(r.a1);
- return r;
+ return (DisasCond){
+ .c = TCG_COND_NEVER,
+ .a0 = NULL,
+ .a1 = NULL,
+ };
}
static DisasCond cond_make_n(void)
{
- DisasCond r = { .c = TCG_COND_NE, .a0_is_n = true, .a1_is_0 = true };
- r.a0 = cpu_psw_n;
- TCGV_UNUSED(r.a1);
- return r;
+ return (DisasCond){
+ .c = TCG_COND_NE,
+ .a0 = cpu_psw_n,
+ .a0_is_n = true,
+ .a1 = NULL,
+ .a1_is_0 = true
+ };
}
static DisasCond cond_make_0(TCGCond c, TCGv a0)
{
- DisasCond r = { .c = c, .a1_is_0 = true };
+ DisasCond r = { .c = c, .a1 = NULL, .a1_is_0 = true };
assert (c != TCG_COND_NEVER && c != TCG_COND_ALWAYS);
r.a0 = tcg_temp_new();
tcg_gen_mov_tl(r.a0, a0);
- TCGV_UNUSED(r.a1);
return r;
}
@@ -199,8 +202,8 @@ static void cond_free(DisasCond *cond)
}
cond->a0_is_n = false;
cond->a1_is_0 = false;
- TCGV_UNUSED(cond->a0);
- TCGV_UNUSED(cond->a1);
+ cond->a0 = NULL;
+ cond->a1 = NULL;
/* fallthru */
case TCG_COND_ALWAYS:
cond->c = TCG_COND_NEVER;
@@ -716,9 +719,8 @@ static DisasCond do_sed_cond(unsigned orig, TCGv res)
static DisasCond do_unit_cond(unsigned cf, TCGv res, TCGv in1, TCGv in2)
{
DisasCond cond;
- TCGv tmp, cb;
+ TCGv tmp, cb = NULL;
- TCGV_UNUSED(cb);
if (cf & 8) {
/* Since we want to test lots of carry-out bits all at once, do not
* do our normal thing and compute carry-in of bit B+1 since that
@@ -826,8 +828,8 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2,
DisasCond cond;
dest = tcg_temp_new();
- TCGV_UNUSED(cb);
- TCGV_UNUSED(cb_msb);
+ cb = NULL;
+ cb_msb = NULL;
if (shift) {
tmp = get_temp(ctx);
@@ -856,7 +858,7 @@ static DisasJumpType do_add(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2,
}
/* Compute signed overflow if required. */
- TCGV_UNUSED(sv);
+ sv = NULL;
if (is_tsv || c == 6) {
sv = do_add_sv(ctx, dest, in1, in2);
if (is_tsv) {
@@ -919,7 +921,7 @@ static DisasJumpType do_sub(DisasContext *ctx, unsigned rt, TCGv in1, TCGv in2,
tcg_temp_free(zero);
/* Compute signed overflow if required. */
- TCGV_UNUSED(sv);
+ sv = NULL;
if (is_tsv || c == 6) {
sv = do_sub_sv(ctx, dest, in1, in2);
if (is_tsv) {
@@ -965,7 +967,7 @@ static DisasJumpType do_cmpclr(DisasContext *ctx, unsigned rt, TCGv in1,
tcg_gen_sub_tl(dest, in1, in2);
/* Compute signed overflow if required. */
- TCGV_UNUSED(sv);
+ sv = NULL;
if ((cf >> 1) == 6) {
sv = do_sub_sv(ctx, dest, in1, in2);
}
@@ -2070,8 +2072,7 @@ static DisasJumpType trans_ds(DisasContext *ctx, uint32_t insn,
/* Install the new nullification. */
if (cf) {
- TCGv sv;
- TCGV_UNUSED(sv);
+ TCGv sv = NULL;
if (cf >> 1 == 6) {
/* ??? The lshift is supposed to contribute to overflow. */
sv = do_add_sv(ctx, dest, add1, add2);
@@ -2542,7 +2543,7 @@ static DisasJumpType trans_cmpb(DisasContext *ctx, uint32_t insn,
tcg_gen_sub_tl(dest, in1, in2);
- TCGV_UNUSED(sv);
+ sv = NULL;
if (c == 6) {
sv = do_sub_sv(ctx, dest, in1, in2);
}
@@ -2571,8 +2572,8 @@ static DisasJumpType trans_addb(DisasContext *ctx, uint32_t insn,
}
in2 = load_gpr(ctx, r);
dest = dest_gpr(ctx, r);
- TCGV_UNUSED(sv);
- TCGV_UNUSED(cb_msb);
+ sv = NULL;
+ cb_msb = NULL;
switch (c) {
default:
@@ -3732,18 +3733,16 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase,
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
TranslationBlock *tb = ctx->base.tb;
- int i, bound;
+ int bound;
ctx->cs = cs;
ctx->iaoq_f = tb->pc;
ctx->iaoq_b = tb->cs_base;
ctx->iaoq_n = -1;
- TCGV_UNUSED(ctx->iaoq_n_var);
+ ctx->iaoq_n_var = NULL;
ctx->ntemps = 0;
- for (i = 0; i < ARRAY_SIZE(ctx->temps); ++i) {
- TCGV_UNUSED(ctx->temps[i]);
- }
+ memset(ctx->temps, 0, sizeof(ctx->temps));
bound = -(tb->pc | TARGET_PAGE_MASK) / 4;
return MIN(max_insns, bound);
@@ -3804,7 +3803,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
tcg_gen_addi_tl(ctx->iaoq_n_var, cpu_iaoq_b, 4);
} else {
ctx->iaoq_n = ctx->iaoq_b + 4;
- TCGV_UNUSED(ctx->iaoq_n_var);
+ ctx->iaoq_n_var = NULL;
}
if (unlikely(ctx->null_cond.c == TCG_COND_ALWAYS)) {
@@ -3819,7 +3818,7 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
/* Free any temporaries allocated. */
for (i = 0, n = ctx->ntemps; i < n; ++i) {
tcg_temp_free(ctx->temps[i]);
- TCGV_UNUSED(ctx->temps[i]);
+ ctx->temps[i] = NULL;
}
ctx->ntemps = 0;
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 088a9d9766..8c5f12985a 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -689,7 +689,7 @@ static void gen_compute_eflags(DisasContext *s)
return;
}
- TCGV_UNUSED(zero);
+ zero = NULL;
dst = cpu_cc_dst;
src1 = cpu_cc_src;
src2 = cpu_cc_src2;
@@ -2050,9 +2050,8 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,
/* Compute the address, with a minimum number of TCG ops. */
static TCGv gen_lea_modrm_1(AddressParts a)
{
- TCGv ea;
+ TCGv ea = NULL;
- TCGV_UNUSED(ea);
if (a.index >= 0) {
if (a.scale == 0) {
ea = cpu_regs[a.index];
@@ -2067,7 +2066,7 @@ static TCGv gen_lea_modrm_1(AddressParts a)
} else if (a.base >= 0) {
ea = cpu_regs[a.base];
}
- if (TCGV_IS_UNUSED(ea)) {
+ if (!ea) {
tcg_gen_movi_tl(cpu_A0, a.disp);
ea = cpu_A0;
} else if (a.disp != 0) {
@@ -3951,7 +3950,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
/* Re-use the carry-out from a previous round. */
- TCGV_UNUSED(carry_in);
+ carry_in = NULL;
carry_out = (b == 0x1f6 ? cpu_cc_dst : cpu_cc_src2);
switch (s->cc_op) {
case CC_OP_ADCX:
@@ -3979,7 +3978,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
break;
}
/* If we can't reuse carry-out, get it out of EFLAGS. */
- if (TCGV_IS_UNUSED(carry_in)) {
+ if (!carry_in) {
if (s->cc_op != CC_OP_ADCX && s->cc_op != CC_OP_ADOX) {
gen_compute_eflags(s);
}
@@ -7672,7 +7671,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
tcg_gen_mov_tl(a0, cpu_A0);
} else {
gen_op_mov_v_reg(ot, t0, rm);
- TCGV_UNUSED(a0);
+ a0 = NULL;
}
gen_op_mov_v_reg(ot, t1, reg);
tcg_gen_andi_tl(cpu_tmp0, t0, 3);
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index b60909222c..e78c9f208b 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -3956,8 +3956,8 @@ DISAS_INSN(bfop_reg)
int ofs = extract32(ext, 6, 5); /* big bit-endian */
TCGv mask, tofs, tlen;
- TCGV_UNUSED(tofs);
- TCGV_UNUSED(tlen);
+ tofs = NULL;
+ tlen = NULL;
if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
tofs = tcg_temp_new();
tlen = tcg_temp_new();
@@ -3973,7 +3973,7 @@ DISAS_INSN(bfop_reg)
}
tcg_gen_andi_i32(QREG_CC_N, QREG_CC_N, ~maski);
mask = tcg_const_i32(ror32(maski, ofs));
- if (!TCGV_IS_UNUSED(tofs)) {
+ if (tofs) {
tcg_gen_movi_i32(tofs, ofs);
tcg_gen_movi_i32(tlen, len);
}
@@ -3985,13 +3985,13 @@ DISAS_INSN(bfop_reg)
tcg_gen_andi_i32(tmp, tmp, 31);
mask = tcg_const_i32(0x7fffffffu);
tcg_gen_shr_i32(mask, mask, tmp);
- if (!TCGV_IS_UNUSED(tlen)) {
+ if (tlen) {
tcg_gen_addi_i32(tlen, tmp, 1);
}
} else {
/* Immediate width */
mask = tcg_const_i32(0x7fffffffu >> (len - 1));
- if (!TCGV_IS_UNUSED(tlen)) {
+ if (tlen) {
tcg_gen_movi_i32(tlen, len);
}
}
@@ -4001,7 +4001,7 @@ DISAS_INSN(bfop_reg)
tcg_gen_rotl_i32(QREG_CC_N, src, tmp);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotr_i32(mask, mask, tmp);
- if (!TCGV_IS_UNUSED(tofs)) {
+ if (tofs) {
tcg_gen_mov_i32(tofs, tmp);
}
} else {
@@ -4009,7 +4009,7 @@ DISAS_INSN(bfop_reg)
tcg_gen_rotli_i32(QREG_CC_N, src, ofs);
tcg_gen_andc_i32(QREG_CC_N, QREG_CC_N, mask);
tcg_gen_rotri_i32(mask, mask, ofs);
- if (!TCGV_IS_UNUSED(tofs)) {
+ if (tofs) {
tcg_gen_movi_i32(tofs, ofs);
}
}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b022f840c9..d05ee67e63 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -20453,7 +20453,7 @@ void mips_tcg_init(void)
{
int i;
- TCGV_UNUSED(cpu_gpr[0]);
+ cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++)
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUMIPSState, active_tc.gpr[i]),
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 72329002ac..0afd10f08a 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -124,7 +124,7 @@ static uint8_t get_opxcode(uint32_t code)
static TCGv load_zero(DisasContext *dc)
{
- if (TCGV_IS_UNUSED_I32(dc->zero)) {
+ if (!dc->zero) {
dc->zero = tcg_const_i32(0);
}
return dc->zero;
@@ -754,12 +754,12 @@ static void handle_instruction(DisasContext *dc, CPUNios2State *env)
goto illegal_op;
}
- TCGV_UNUSED_I32(dc->zero);
+ dc->zero = NULL;
instr = &i_type_instructions[op];
instr->handler(dc, code, instr->flags);
- if (!TCGV_IS_UNUSED_I32(dc->zero)) {
+ if (dc->zero) {
tcg_temp_free(dc->zero);
}
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 998fbed848..4f7b66f990 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3495,7 +3495,7 @@ static inline void gen_bcond(DisasContext *ctx, int type)
else
tcg_gen_mov_tl(target, cpu_lr);
} else {
- TCGV_UNUSED(target);
+ target = NULL;
}
if (LK(ctx->opcode))
gen_setlr(ctx, ctx->nip);
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 85d0a6c3af..03eca099f6 100644
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -440,11 +440,9 @@ static void set_cc_static(DisasContext *s)
/* calculates cc into cc_op */
static void gen_op_calc_cc(DisasContext *s)
{
- TCGv_i32 local_cc_op;
- TCGv_i64 dummy;
+ TCGv_i32 local_cc_op = NULL;
+ TCGv_i64 dummy = NULL;
- TCGV_UNUSED_I32(local_cc_op);
- TCGV_UNUSED_I64(dummy);
switch (s->cc_op) {
default:
dummy = tcg_const_i64(0);
@@ -534,10 +532,10 @@ static void gen_op_calc_cc(DisasContext *s)
tcg_abort();
}
- if (!TCGV_IS_UNUSED_I32(local_cc_op)) {
+ if (local_cc_op) {
tcg_temp_free_i32(local_cc_op);
}
- if (!TCGV_IS_UNUSED_I64(dummy)) {
+ if (dummy) {
tcg_temp_free_i64(dummy);
}
@@ -1195,7 +1193,7 @@ static ExitStatus help_branch(DisasContext *s, DisasCompare *c,
goto egress;
}
} else {
- if (TCGV_IS_UNUSED_I64(cdest)) {
+ if (!cdest) {
/* E.g. bcr %r0 -> no branch. */
ret = NO_EXIT;
goto egress;
@@ -1415,7 +1413,7 @@ static ExitStatus op_andi(DisasContext *s, DisasOps *o)
static ExitStatus op_bas(DisasContext *s, DisasOps *o)
{
tcg_gen_movi_i64(o->out, pc_to_link_info(s, s->next_pc));
- if (!TCGV_IS_UNUSED_I64(o->in2)) {
+ if (o->in2) {
tcg_gen_mov_i64(psw_addr, o->in2);
per_branch(s, false);
return EXIT_PC_UPDATED;
@@ -2997,7 +2995,7 @@ static ExitStatus op_mov2(DisasContext *s, DisasOps *o)
{
o->out = o->in2;
o->g_out = o->g_in2;
- TCGV_UNUSED_I64(o->in2);
+ o->in2 = NULL;
o->g_in2 = false;
return NO_EXIT;
}
@@ -3009,7 +3007,7 @@ static ExitStatus op_mov2e(DisasContext *s, DisasOps *o)
o->out = o->in2;
o->g_out = o->g_in2;
- TCGV_UNUSED_I64(o->in2);
+ o->in2 = NULL;
o->g_in2 = false;
switch (s->tb->flags & FLAG_MASK_ASC) {
@@ -3043,8 +3041,8 @@ static ExitStatus op_movx(DisasContext *s, DisasOps *o)
o->out2 = o->in2;
o->g_out = o->g_in1;
o->g_out2 = o->g_in2;
- TCGV_UNUSED_I64(o->in1);
- TCGV_UNUSED_I64(o->in2);
+ o->in1 = NULL;
+ o->in2 = NULL;
o->g_in1 = o->g_in2 = false;
return NO_EXIT;
}
@@ -5801,11 +5799,11 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
s->insn = insn;
s->fields = &f;
o.g_out = o.g_out2 = o.g_in1 = o.g_in2 = false;
- TCGV_UNUSED_I64(o.out);
- TCGV_UNUSED_I64(o.out2);
- TCGV_UNUSED_I64(o.in1);
- TCGV_UNUSED_I64(o.in2);
- TCGV_UNUSED_I64(o.addr1);
+ o.out = NULL;
+ o.out2 = NULL;
+ o.in1 = NULL;
+ o.in2 = NULL;
+ o.addr1 = NULL;
/* Implement the instruction. */
if (insn->help_in1) {
@@ -5828,19 +5826,19 @@ static ExitStatus translate_one(CPUS390XState *env, DisasContext *s)
}
/* Free any temporaries created by the helpers. */
- if (!TCGV_IS_UNUSED_I64(o.out) && !o.g_out) {
+ if (o.out && !o.g_out) {
tcg_temp_free_i64(o.out);
}
- if (!TCGV_IS_UNUSED_I64(o.out2) && !o.g_out2) {
+ if (o.out2 && !o.g_out2) {
tcg_temp_free_i64(o.out2);
}
- if (!TCGV_IS_UNUSED_I64(o.in1) && !o.g_in1) {
+ if (o.in1 && !o.g_in1) {
tcg_temp_free_i64(o.in1);
}
- if (!TCGV_IS_UNUSED_I64(o.in2) && !o.g_in2) {
+ if (o.in2 && !o.g_in2) {
tcg_temp_free_i64(o.in2);
}
- if (!TCGV_IS_UNUSED_I64(o.addr1)) {
+ if (o.addr1) {
tcg_temp_free_i64(o.addr1);
}
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 703020fe87..48ea0fe7e0 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1901,7 +1901,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insns)
op_dst = op_src = op_opc = -1;
mt_dst = -1;
st_src = st_mop = -1;
- TCGV_UNUSED(op_arg);
+ op_arg = NULL;
i = 0;
#define NEXT_INSN \
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 849a02aebd..71e0853e43 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5922,7 +5922,7 @@ void sparc_tcg_init(void)
*rtl[i].ptr = tcg_global_mem_new(cpu_env, rtl[i].off, rtl[i].name);
}
- TCGV_UNUSED(cpu_regs[0]);
+ cpu_regs[0] = NULL;
for (i = 1; i < 8; ++i) {
cpu_regs[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUSPARCState, gregs[i]),
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
index d55549dabc..d63bf5bba3 100644
--- a/target/tilegx/translate.c
+++ b/target/tilegx/translate.c
@@ -143,7 +143,7 @@ static bool check_gr(DisasContext *dc, uint8_t reg)
static TCGv load_zero(DisasContext *dc)
{
- if (TCGV_IS_UNUSED_I64(dc->zero)) {
+ if (!dc->zero) {
dc->zero = tcg_const_i64(0);
}
return dc->zero;
@@ -2324,7 +2324,7 @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
for (i = 0; i < ARRAY_SIZE(dc->wb); i++) {
DisasContextTemp *wb = &dc->wb[i];
wb->reg = TILEGX_R_NOREG;
- TCGV_UNUSED_I64(wb->val);
+ wb->val = NULL;
}
dc->num_wb = 0;
@@ -2384,9 +2384,9 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
dc->exit_tb = false;
dc->atomic_excp = TILEGX_EXCP_NONE;
dc->jmp.cond = TCG_COND_NEVER;
- TCGV_UNUSED_I64(dc->jmp.dest);
- TCGV_UNUSED_I64(dc->jmp.val1);
- TCGV_UNUSED_I64(dc->zero);
+ dc->jmp.dest = NULL;
+ dc->jmp.val1 = NULL;
+ dc->zero = NULL;
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
qemu_log_lock();
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
index 384aa86027..5b51f2166d 100644
--- a/target/unicore32/translate.c
+++ b/target/unicore32/translate.c
@@ -1230,7 +1230,7 @@ static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
if (UCOP_OPCODES != 0x0f && UCOP_OPCODES != 0x0d) {
tmp = load_reg(s, UCOP_REG_N);
} else {
- TCGV_UNUSED(tmp);
+ tmp = NULL;
}
switch (UCOP_OPCODES) {
@@ -1652,7 +1652,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* compute total size */
loaded_base = 0;
- TCGV_UNUSED(loaded_var);
+ loaded_var = NULL;
n = 0;
for (i = 0; i < 6; i++) {
if (UCOP_SET(i)) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index c22f1c4441..68bcd2267b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1358,8 +1358,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
TCGv_i64 retl, reth;
TCGTemp *split_args[MAX_OPC_PARAM];
- TCGV_UNUSED_I64(retl);
- TCGV_UNUSED_I64(reth);
+ retl = NULL;
+ reth = NULL;
if (sizemask != 0) {
for (i = real_args = 0; i < nargs; ++i) {
int is_64bit = sizemask & (1 << (i+1)*2);
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 02/26] tcg: Dynamically allocate TCGOps
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 01/26] tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 03/26] tcg: Generalize TCGOp parameters Richard Henderson
` (28 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
With no fixed array allocation, we can't overflow a buffer.
This will be important as optimizations related to host vectors
may expand the number of ops used.
Use QTAILQ to link the ops together.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/gen-icount.h | 9 ++--
include/qemu/queue.h | 5 ++
target/arm/translate.h | 10 ++--
tcg/tcg.h | 35 +++++-------
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 2 +-
target/cris/translate.c | 2 -
target/lm32/translate.c | 2 -
target/microblaze/translate.c | 4 --
tcg/optimize.c | 16 ++----
tcg/tcg-op.c | 24 ---------
tcg/tcg.c | 123 ++++++++++++++++--------------------------
12 files changed, 77 insertions(+), 157 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 049bba86e9..54aaa61d65 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -5,7 +5,7 @@
/* Helpers for instruction counting code generation. */
-static int icount_start_insn_idx;
+static TCGOp *icount_start_insn;
static inline void gen_tb_start(TranslationBlock *tb)
{
@@ -26,8 +26,8 @@ static inline void gen_tb_start(TranslationBlock *tb)
/* We emit a movi with a dummy immediate argument. Keep the insn index
* of the movi so that we later (when we know the actual insn count)
* can update the immediate argument with the actual insn count. */
- icount_start_insn_idx = tcg_op_buf_count();
tcg_gen_movi_i32(imm, 0xdeadbeef);
+ icount_start_insn = tcg_last_op();
tcg_gen_sub_i32(count, count, imm);
tcg_temp_free_i32(imm);
@@ -48,14 +48,11 @@ static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
if (tb_cflags(tb) & CF_USE_ICOUNT) {
/* Update the num_insn immediate parameter now that we know
* the actual insn count. */
- tcg_set_insn_param(icount_start_insn_idx, 1, num_insns);
+ tcg_set_insn_param(icount_start_insn, 1, num_insns);
}
gen_set_label(tcg_ctx->exitreq_label);
tcg_gen_exit_tb((uintptr_t)tb + TB_EXIT_REQUESTED);
-
- /* Terminate the linked list. */
- tcg_ctx->gen_op_buf[tcg_ctx->gen_op_buf[0].prev].next = 0;
}
static inline void gen_io_start(void)
diff --git a/include/qemu/queue.h b/include/qemu/queue.h
index 35292c3155..aa270d2b38 100644
--- a/include/qemu/queue.h
+++ b/include/qemu/queue.h
@@ -425,6 +425,11 @@ struct { \
(var); \
(var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)))
+#define QTAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, prev_var) \
+ for ((var) = (*(((struct headname *)((head)->tqh_last))->tqh_last)); \
+ (var) && ((prev_var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)), 1); \
+ (var) = (prev_var))
+
/*
* Tail queue access methods.
*/
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 410ba79c0d..cd7313ace7 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -66,8 +66,8 @@ typedef struct DisasContext {
bool ss_same_el;
/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
int c15_cpar;
- /* TCG op index of the current insn_start. */
- int insn_start_idx;
+ /* TCG op of the current insn_start. */
+ TCGOp *insn_start;
#define TMP_A64_MAX 16
int tmp_a64_count;
TCGv_i64 tmp_a64[TMP_A64_MAX];
@@ -117,9 +117,9 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
syn >>= ARM_INSN_START_WORD2_SHIFT;
/* We check and clear insn_start_idx to catch multiple updates. */
- assert(s->insn_start_idx != 0);
- tcg_set_insn_param(s->insn_start_idx, 2, syn);
- s->insn_start_idx = 0;
+ assert(s->insn_start != NULL);
+ tcg_set_insn_param(s->insn_start, 2, syn);
+ s->insn_start = NULL;
}
/* is_jmp field values */
diff --git a/tcg/tcg.h b/tcg/tcg.h
index c21194c858..a577447846 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -29,6 +29,7 @@
#include "cpu.h"
#include "exec/tb-context.h"
#include "qemu/bitops.h"
+#include "qemu/queue.h"
#include "tcg-mo.h"
#include "tcg-target.h"
@@ -48,8 +49,6 @@
* and up to 4 + N parameters on 64-bit archs
* (N = number of input arguments + output arguments). */
#define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
-#define OPC_BUF_SIZE 640
-#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
#define CPU_TEMP_BUF_NLONGS 128
@@ -572,23 +571,18 @@ typedef struct TCGOp {
unsigned callo : 2; /* 14 */
unsigned : 2; /* 16 */
- /* Index of the prev/next op, or 0 for the end of the list. */
- unsigned prev : 16; /* 32 */
- unsigned next : 16; /* 48 */
-
/* Lifetime data of the operands. */
- unsigned life : 16; /* 64 */
+ unsigned life : 16; /* 32 */
+
+ /* Next and previous opcodes. */
+ QTAILQ_ENTRY(TCGOp) link;
/* Arguments for the opcode. */
TCGArg args[MAX_OPC_PARAM];
} TCGOp;
-/* Make sure that we don't expand the structure without noticing. */
-QEMU_BUILD_BUG_ON(sizeof(TCGOp) != 8 + sizeof(TCGArg) * MAX_OPC_PARAM);
-
/* Make sure operands fit in the bitfields above. */
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
-QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16));
typedef struct TCGProfile {
int64_t tb_count1;
@@ -642,8 +636,6 @@ struct TCGContext {
int goto_tb_issue_mask;
#endif
- int gen_next_op_idx;
-
/* Code generation. Note that we specifically do not use tcg_insn_unit
here, because there's too much arithmetic throughout that relies
on addition and subtraction working on bytes. Rely on the GCC
@@ -674,12 +666,12 @@ struct TCGContext {
TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
+ QTAILQ_HEAD(TCGOpHead, TCGOp) ops, free_ops;
+
/* Tells which temporary holds a given register.
It does not take into account fixed registers */
TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
- TCGOp gen_op_buf[OPC_BUF_SIZE];
-
uint16_t gen_insn_end_off[TCG_MAX_INSNS];
target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
};
@@ -769,21 +761,21 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
}
#endif
-static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
+static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
{
- tcg_ctx->gen_op_buf[op_idx].args[arg] = v;
+ op->args[arg] = v;
}
-/* The number of opcodes emitted so far. */
-static inline int tcg_op_buf_count(void)
+/* The last op that was emitted. */
+static inline TCGOp *tcg_last_op(void)
{
- return tcg_ctx->gen_next_op_idx;
+ return QTAILQ_LAST(&tcg_ctx->ops, TCGOpHead);
}
/* Test for whether to terminate the TB for using too many opcodes. */
static inline bool tcg_op_buf_full(void)
{
- return tcg_op_buf_count() >= OPC_MAX_SIZE;
+ return false;
}
/* pool based memory allocation */
@@ -967,6 +959,7 @@ bool tcg_op_supported(TCGOpcode op);
void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
+TCGOp *tcg_emit_op(TCGOpcode opc);
void tcg_op_remove(TCGContext *s, TCGOp *op);
TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 460bab5987..ba94f7d045 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11290,8 +11290,8 @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- dc->insn_start_idx = tcg_op_buf_count();
tcg_gen_insn_start(dc->pc, 0, 0);
+ dc->insn_start = tcg_last_op();
}
static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0b74ce7dec..20c3246912 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -12065,10 +12065,10 @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- dc->insn_start_idx = tcg_op_buf_count();
tcg_gen_insn_start(dc->pc,
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
0);
+ dc->insn_start = tcg_last_op();
}
static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
diff --git a/target/cris/translate.c b/target/cris/translate.c
index 74822ed31f..f51a731db9 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3297,8 +3297,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
qemu_log("--------------\n");
qemu_log("IN: %s\n", lookup_symbol(pc_start));
log_target_disas(cs, pc_start, dc->pc - pc_start);
- qemu_log("\nisize=%d osize=%d\n",
- dc->pc - pc_start, tcg_op_buf_count());
qemu_log_unlock();
}
#endif
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
index b8b2b13e36..2e1c5e6d01 100644
--- a/target/lm32/translate.c
+++ b/target/lm32/translate.c
@@ -1156,8 +1156,6 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
qemu_log_lock();
qemu_log("\n");
log_target_disas(cs, pc_start, dc->pc - pc_start);
- qemu_log("\nisize=%d osize=%d\n",
- dc->pc - pc_start, tcg_op_buf_count());
qemu_log_unlock();
}
#endif
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index e7b5597c46..7628b0e25b 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1808,11 +1808,7 @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
&& qemu_log_in_addr_range(pc_start)) {
qemu_log_lock();
qemu_log("--------------\n");
-#if DISAS_GNU
log_target_disas(cs, pc_start, dc->pc - pc_start);
-#endif
- qemu_log("\nisize=%d osize=%d\n",
- dc->pc - pc_start, tcg_op_buf_count());
qemu_log_unlock();
}
#endif
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 438321c6cc..e495680e95 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -602,8 +602,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
/* Propagate constants and copies, fold constant expressions. */
void tcg_optimize(TCGContext *s)
{
- int oi, oi_next, nb_temps, nb_globals;
- TCGOp *prev_mb = NULL;
+ int nb_temps, nb_globals;
+ TCGOp *op, *op_next, *prev_mb = NULL;
struct tcg_temp_info *infos;
TCGTempSet temps_used;
@@ -617,17 +617,13 @@ void tcg_optimize(TCGContext *s)
bitmap_zero(temps_used.l, nb_temps);
infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps);
- for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
+ QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
tcg_target_ulong mask, partmask, affected;
int nb_oargs, nb_iargs, i;
TCGArg tmp;
-
- TCGOp * const op = &s->gen_op_buf[oi];
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
- oi_next = op->next;
-
/* Count the arguments, and initialize the temps that are
going to be used */
if (opc == INDEX_op_call) {
@@ -1261,9 +1257,6 @@ void tcg_optimize(TCGContext *s)
rh = op->args[1];
tcg_opt_gen_movi(s, op, rl, (int32_t)a);
tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32));
-
- /* We've done all we need to do with the movi. Skip it. */
- oi_next = op2->next;
break;
}
goto do_default;
@@ -1280,9 +1273,6 @@ void tcg_optimize(TCGContext *s)
rh = op->args[1];
tcg_opt_gen_movi(s, op, rl, (int32_t)r);
tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32));
-
- /* We've done all we need to do with the movi. Skip it. */
- oi_next = op2->next;
break;
}
goto do_default;
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 3cad30b1f2..0c509bfe46 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -42,30 +42,6 @@ extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
#define TCGV_HIGH TCGV_HIGH_link_error
#endif
-/* Note that this is optimized for sequential allocation during translate.
- Up to and including filling in the forward link immediately. We'll do
- proper termination of the end of the list after we finish translation. */
-
-static inline TCGOp *tcg_emit_op(TCGOpcode opc)
-{
- TCGContext *ctx = tcg_ctx;
- int oi = ctx->gen_next_op_idx;
- int ni = oi + 1;
- int pi = oi - 1;
- TCGOp *op = &ctx->gen_op_buf[oi];
-
- tcg_debug_assert(oi < OPC_BUF_SIZE);
- ctx->gen_op_buf[0].prev = oi;
- ctx->gen_next_op_idx = ni;
-
- memset(op, 0, offsetof(TCGOp, args));
- op->opc = opc;
- op->prev = pi;
- op->next = ni;
-
- return op;
-}
-
void tcg_gen_op1(TCGOpcode opc, TCGArg a1)
{
TCGOp *op = tcg_emit_op(opc);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 68bcd2267b..f26949a900 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -862,9 +862,8 @@ void tcg_func_start(TCGContext *s)
s->goto_tb_issue_mask = 0;
#endif
- s->gen_op_buf[0].next = 1;
- s->gen_op_buf[0].prev = 0;
- s->gen_next_op_idx = 1;
+ QTAILQ_INIT(&s->ops);
+ QTAILQ_INIT(&s->free_ops);
}
static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
@@ -1339,7 +1338,6 @@ bool tcg_op_supported(TCGOpcode op)
and endian swap in tcg_reg_alloc_call(). */
void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
{
- TCGContext *s = tcg_ctx;
int i, real_args, nb_rets, pi;
unsigned sizemask, flags;
TCGHelperInfo *info;
@@ -1395,17 +1393,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
}
#endif /* TCG_TARGET_EXTEND_ARGS */
- i = s->gen_next_op_idx;
- tcg_debug_assert(i < OPC_BUF_SIZE);
- s->gen_op_buf[0].prev = i;
- s->gen_next_op_idx = i + 1;
- op = &s->gen_op_buf[i];
-
- /* Set links for sequential allocation during translation. */
- memset(op, 0, offsetof(TCGOp, args));
- op->opc = INDEX_op_call;
- op->prev = i - 1;
- op->next = i + 1;
+ op = tcg_emit_op(INDEX_op_call);
pi = 0;
if (ret != NULL) {
@@ -1622,20 +1610,18 @@ void tcg_dump_ops(TCGContext *s)
{
char buf[128];
TCGOp *op;
- int oi;
- for (oi = s->gen_op_buf[0].next; oi != 0; oi = op->next) {
+ QTAILQ_FOREACH(op, &s->ops, link) {
int i, k, nb_oargs, nb_iargs, nb_cargs;
const TCGOpDef *def;
TCGOpcode c;
int col = 0;
- op = &s->gen_op_buf[oi];
c = op->opc;
def = &tcg_op_defs[c];
if (c == INDEX_op_insn_start) {
- col += qemu_log("%s ----", oi != s->gen_op_buf[0].next ? "\n" : "");
+ col += qemu_log("\n ----");
for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
target_ulong a;
@@ -1898,65 +1884,51 @@ static void process_op_defs(TCGContext *s)
void tcg_op_remove(TCGContext *s, TCGOp *op)
{
- int next = op->next;
- int prev = op->prev;
-
- /* We should never attempt to remove the list terminator. */
- tcg_debug_assert(op != &s->gen_op_buf[0]);
-
- s->gen_op_buf[next].prev = prev;
- s->gen_op_buf[prev].next = next;
-
- memset(op, 0, sizeof(*op));
+ QTAILQ_REMOVE(&s->ops, op, link);
+ QTAILQ_INSERT_TAIL(&s->free_ops, op, link);
#ifdef CONFIG_PROFILER
atomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1);
#endif
}
-TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op,
- TCGOpcode opc, int nargs)
+static TCGOp *tcg_op_alloc(TCGOpcode opc)
{
- int oi = s->gen_next_op_idx;
- int prev = old_op->prev;
- int next = old_op - s->gen_op_buf;
- TCGOp *new_op;
+ TCGContext *s = tcg_ctx;
+ TCGOp *op;
- tcg_debug_assert(oi < OPC_BUF_SIZE);
- s->gen_next_op_idx = oi + 1;
+ if (likely(QTAILQ_EMPTY(&s->free_ops))) {
+ op = tcg_malloc(sizeof(TCGOp));
+ } else {
+ op = QTAILQ_FIRST(&s->free_ops);
+ QTAILQ_REMOVE(&s->free_ops, op, link);
+ }
+ memset(op, 0, offsetof(TCGOp, link));
+ op->opc = opc;
- new_op = &s->gen_op_buf[oi];
- *new_op = (TCGOp){
- .opc = opc,
- .prev = prev,
- .next = next
- };
- s->gen_op_buf[prev].next = oi;
- old_op->prev = oi;
+ return op;
+}
+
+TCGOp *tcg_emit_op(TCGOpcode opc)
+{
+ TCGOp *op = tcg_op_alloc(opc);
+ QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link);
+ return op;
+}
+TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op,
+ TCGOpcode opc, int nargs)
+{
+ TCGOp *new_op = tcg_op_alloc(opc);
+ QTAILQ_INSERT_BEFORE(old_op, new_op, link);
return new_op;
}
TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op,
TCGOpcode opc, int nargs)
{
- int oi = s->gen_next_op_idx;
- int prev = old_op - s->gen_op_buf;
- int next = old_op->next;
- TCGOp *new_op;
-
- tcg_debug_assert(oi < OPC_BUF_SIZE);
- s->gen_next_op_idx = oi + 1;
-
- new_op = &s->gen_op_buf[oi];
- *new_op = (TCGOp){
- .opc = opc,
- .prev = prev,
- .next = next
- };
- s->gen_op_buf[next].prev = oi;
- old_op->next = oi;
-
+ TCGOp *new_op = tcg_op_alloc(opc);
+ QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link);
return new_op;
}
@@ -2006,23 +1978,19 @@ static void tcg_la_bb_end(TCGContext *s)
static void liveness_pass_1(TCGContext *s)
{
int nb_globals = s->nb_globals;
- int oi, oi_prev;
+ TCGOp *op, *op_prev;
tcg_la_func_end(s);
- for (oi = s->gen_op_buf[0].prev; oi != 0; oi = oi_prev) {
+ QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, TCGOpHead, link, op_prev) {
int i, nb_iargs, nb_oargs;
TCGOpcode opc_new, opc_new2;
bool have_opc_new2;
TCGLifeData arg_life = 0;
TCGTemp *arg_ts;
-
- TCGOp * const op = &s->gen_op_buf[oi];
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
- oi_prev = op->prev;
-
switch (opc) {
case INDEX_op_call:
{
@@ -2233,8 +2201,9 @@ static void liveness_pass_1(TCGContext *s)
static bool liveness_pass_2(TCGContext *s)
{
int nb_globals = s->nb_globals;
- int nb_temps, i, oi, oi_next;
+ int nb_temps, i;
bool changes = false;
+ TCGOp *op, *op_next;
/* Create a temporary for each indirect global. */
for (i = 0; i < nb_globals; ++i) {
@@ -2256,16 +2225,13 @@ static bool liveness_pass_2(TCGContext *s)
its->state = TS_DEAD;
}
- for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
- TCGOp *op = &s->gen_op_buf[oi];
+ QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
TCGLifeData arg_life = op->life;
int nb_iargs, nb_oargs, call_flags;
TCGTemp *arg_ts, *dir_ts;
- oi_next = op->next;
-
if (opc == INDEX_op_call) {
nb_oargs = op->callo;
nb_iargs = op->calli;
@@ -3168,13 +3134,16 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
#ifdef CONFIG_PROFILER
TCGProfile *prof = &s->prof;
#endif
- int i, oi, oi_next, num_insns;
+ int i, num_insns;
+ TCGOp *op;
#ifdef CONFIG_PROFILER
{
int n;
- n = s->gen_op_buf[0].prev + 1;
+ QTAILQ_FOREACH(op, &s->ops, link) {
+ n++;
+ }
atomic_set(&prof->op_count, prof->op_count + n);
if (n > prof->op_count_max) {
atomic_set(&prof->op_count_max, n);
@@ -3260,11 +3229,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
#endif
num_insns = -1;
- for (oi = s->gen_op_buf[0].next; oi != 0; oi = oi_next) {
- TCGOp * const op = &s->gen_op_buf[oi];
+ QTAILQ_FOREACH(op, &s->ops, link) {
TCGOpcode opc = op->opc;
- oi_next = op->next;
#ifdef CONFIG_PROFILER
atomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1);
#endif
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 03/26] tcg: Generalize TCGOp parameters
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 01/26] tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED* Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 02/26] tcg: Dynamically allocate TCGOps Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 04/26] tcg: Add types and basic operations for host vectors Richard Henderson
` (27 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
We had two fields specific to INDEX_op_call. Rename these and
add some macros so that the fields may be reused for other opcodes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 10 ++++++----
tcg/optimize.c | 4 ++--
tcg/tcg.c | 22 +++++++++++-----------
3 files changed, 19 insertions(+), 17 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index a577447846..f25efa9795 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -566,10 +566,9 @@ typedef uint16_t TCGLifeData;
typedef struct TCGOp {
TCGOpcode opc : 8; /* 8 */
- /* The number of out and in parameter for a call. */
- unsigned calli : 4; /* 12 */
- unsigned callo : 2; /* 14 */
- unsigned : 2; /* 16 */
+ /* Parameters for this opcode. See below. */
+ unsigned param1 : 4; /* 12 */
+ unsigned param2 : 4; /* 16 */
/* Lifetime data of the operands. */
unsigned life : 16; /* 32 */
@@ -581,6 +580,9 @@ typedef struct TCGOp {
TCGArg args[MAX_OPC_PARAM];
} TCGOp;
+#define TCGOP_CALLI(X) (X)->param1
+#define TCGOP_CALLO(X) (X)->param2
+
/* Make sure operands fit in the bitfields above. */
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
diff --git a/tcg/optimize.c b/tcg/optimize.c
index e495680e95..2cbbeefd53 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -627,8 +627,8 @@ void tcg_optimize(TCGContext *s)
/* Count the arguments, and initialize the temps that are
going to be used */
if (opc == INDEX_op_call) {
- nb_oargs = op->callo;
- nb_iargs = op->calli;
+ nb_oargs = TCGOP_CALLO(op);
+ nb_iargs = TCGOP_CALLI(op);
for (i = 0; i < nb_oargs + nb_iargs; i++) {
TCGTemp *ts = arg_temp(op->args[i]);
if (ts) {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f26949a900..93caa0be93 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1430,7 +1430,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
} else {
nb_rets = 0;
}
- op->callo = nb_rets;
+ TCGOP_CALLO(op) = nb_rets;
real_args = 0;
for (i = 0; i < nargs; i++) {
@@ -1469,10 +1469,10 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
}
op->args[pi++] = (uintptr_t)func;
op->args[pi++] = flags;
- op->calli = real_args;
+ TCGOP_CALLI(op) = real_args;
/* Make sure the fields didn't overflow. */
- tcg_debug_assert(op->calli == real_args);
+ tcg_debug_assert(TCGOP_CALLI(op) == real_args);
tcg_debug_assert(pi <= ARRAY_SIZE(op->args));
#if defined(__sparc__) && !defined(__arch64__) \
@@ -1634,8 +1634,8 @@ void tcg_dump_ops(TCGContext *s)
}
} else if (c == INDEX_op_call) {
/* variable number of arguments */
- nb_oargs = op->callo;
- nb_iargs = op->calli;
+ nb_oargs = TCGOP_CALLO(op);
+ nb_iargs = TCGOP_CALLI(op);
nb_cargs = def->nb_cargs;
/* function name, flags, out args */
@@ -1996,8 +1996,8 @@ static void liveness_pass_1(TCGContext *s)
{
int call_flags;
- nb_oargs = op->callo;
- nb_iargs = op->calli;
+ nb_oargs = TCGOP_CALLO(op);
+ nb_iargs = TCGOP_CALLI(op);
call_flags = op->args[nb_oargs + nb_iargs + 1];
/* pure functions can be removed if their result is unused */
@@ -2233,8 +2233,8 @@ static bool liveness_pass_2(TCGContext *s)
TCGTemp *arg_ts, *dir_ts;
if (opc == INDEX_op_call) {
- nb_oargs = op->callo;
- nb_iargs = op->calli;
+ nb_oargs = TCGOP_CALLO(op);
+ nb_iargs = TCGOP_CALLI(op);
call_flags = op->args[nb_oargs + nb_iargs + 1];
} else {
nb_iargs = def->nb_iargs;
@@ -2915,8 +2915,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
{
- const int nb_oargs = op->callo;
- const int nb_iargs = op->calli;
+ const int nb_oargs = TCGOP_CALLO(op);
+ const int nb_iargs = TCGOP_CALLI(op);
const TCGLifeData arg_life = op->life;
int flags, nb_regs, i;
TCGReg reg;
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 04/26] tcg: Add types and basic operations for host vectors
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (2 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 03/26] tcg: Generalize TCGOp parameters Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders Richard Henderson
` (26 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Nothing uses or enables them yet.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Makefile.target | 4 +-
tcg/tcg-op.h | 30 +++++
tcg/tcg-opc.h | 26 ++++
tcg/tcg.h | 56 +++++++++
tcg/tcg-op-vec.c | 362 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg.c | 100 ++++++++++++++-
tcg/README | 58 +++++++++
7 files changed, 630 insertions(+), 6 deletions(-)
create mode 100644 tcg/tcg-op-vec.c
diff --git a/Makefile.target b/Makefile.target
index e4244c188a..5ca758f13c 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -93,8 +93,8 @@ all: $(PROGS) stap
# cpu emulator library
obj-y += exec.o
obj-y += accel/
-obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o
-obj-$(CONFIG_TCG) += tcg/tcg-common.o
+obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o
+obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o
obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o
obj-y += fpu/softfloat.o
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index ca07b32b65..9b0560e4d3 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -35,6 +35,10 @@ void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
+void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
+void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
+void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
+
static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
{
tcg_gen_op1(opc, tcgv_i32_arg(a1));
@@ -903,6 +907,30 @@ void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
+void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
+void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
+void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
+void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
+void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
+void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
+void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
+void tcg_gen_movi_v64(TCGv_vec, uint64_t);
+void tcg_gen_movi_v128(TCGv_vec, uint64_t, uint64_t);
+void tcg_gen_movi_v256(TCGv_vec, uint64_t, uint64_t, uint64_t, uint64_t);
+void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+
+void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
+void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
+void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
+
#if TARGET_LONG_BITS == 64
#define tcg_gen_movi_tl tcg_gen_movi_i64
#define tcg_gen_mov_tl tcg_gen_mov_i64
@@ -1001,6 +1029,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
+#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
#else
#define tcg_gen_movi_tl tcg_gen_movi_i32
#define tcg_gen_mov_tl tcg_gen_mov_i32
@@ -1098,6 +1127,7 @@ void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
+#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
#endif
#if UINTPTR_MAX == UINT32_MAX
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 956fb1e9f3..4e62eda14b 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -204,8 +204,34 @@ DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
+/* Host vector support. */
+
+#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
+
+DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
+DEF(movi_vec, 1, 0, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) /* vecl defines const args */
+DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
+
+DEF(dup_vec, 1, 1, 0, IMPLVEC)
+DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
+
+DEF(ld_vec, 1, 1, 1, IMPLVEC)
+DEF(st_vec, 0, 2, 1, IMPLVEC)
+
+DEF(add_vec, 1, 2, 0, IMPLVEC)
+DEF(sub_vec, 1, 2, 0, IMPLVEC)
+DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
+
+DEF(and_vec, 1, 2, 0, IMPLVEC)
+DEF(or_vec, 1, 2, 0, IMPLVEC)
+DEF(xor_vec, 1, 2, 0, IMPLVEC)
+DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
+DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
+DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
#undef IMPL64
+#undef IMPLVEC
#undef DEF
diff --git a/tcg/tcg.h b/tcg/tcg.h
index f25efa9795..2acebd387a 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -170,6 +170,27 @@ typedef uint64_t TCGRegSet;
# error "Missing unsigned widening multiply"
#endif
+#if !defined(TCG_TARGET_HAS_v64) \
+ && !defined(TCG_TARGET_HAS_v128) \
+ && !defined(TCG_TARGET_HAS_v256)
+#define TCG_TARGET_MAYBE_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_orc_vec 0
+#else
+#define TCG_TARGET_MAYBE_vec 1
+#endif
+#ifndef TCG_TARGET_HAS_v64
+#define TCG_TARGET_HAS_v64 0
+#endif
+#ifndef TCG_TARGET_HAS_v128
+#define TCG_TARGET_HAS_v128 0
+#endif
+#ifndef TCG_TARGET_HAS_v256
+#define TCG_TARGET_HAS_v256 0
+#endif
+
#ifndef TARGET_INSN_START_EXTRA_WORDS
# define TARGET_INSN_START_WORDS 1
#else
@@ -246,6 +267,11 @@ typedef struct TCGPool {
typedef enum TCGType {
TCG_TYPE_I32,
TCG_TYPE_I64,
+
+ TCG_TYPE_V64,
+ TCG_TYPE_V128,
+ TCG_TYPE_V256,
+
TCG_TYPE_COUNT, /* number of different types */
/* An alias for the size of the host register. */
@@ -396,6 +422,8 @@ typedef tcg_target_ulong TCGArg;
* TCGv_i32 : 32 bit integer type
* TCGv_i64 : 64 bit integer type
* TCGv_ptr : a host pointer type
+ * TCGv_vec : a host vector type; the exact size is not exposed
+ to the CPU front-end code.
* TCGv : an integer type the same size as target_ulong
(an alias for either TCGv_i32 or TCGv_i64)
The compiler's type checking will complain if you mix them
@@ -418,6 +446,7 @@ typedef tcg_target_ulong TCGArg;
typedef struct TCGv_i32_d *TCGv_i32;
typedef struct TCGv_i64_d *TCGv_i64;
typedef struct TCGv_ptr_d *TCGv_ptr;
+typedef struct TCGv_vec_d *TCGv_vec;
typedef TCGv_ptr TCGv_env;
#if TARGET_LONG_BITS == 32
#define TCGv TCGv_i32
@@ -583,6 +612,9 @@ typedef struct TCGOp {
#define TCGOP_CALLI(X) (X)->param1
#define TCGOP_CALLO(X) (X)->param2
+#define TCGOP_VECL(X) (X)->param1
+#define TCGOP_VECE(X) (X)->param2
+
/* Make sure operands fit in the bitfields above. */
QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
@@ -720,6 +752,11 @@ static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
return tcgv_i32_temp((TCGv_i32)v);
}
+static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
+{
+ return tcgv_i32_temp((TCGv_i32)v);
+}
+
static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
{
return temp_arg(tcgv_i32_temp(v));
@@ -735,6 +772,11 @@ static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
return temp_arg(tcgv_ptr_temp(v));
}
+static inline TCGArg tcgv_vec_arg(TCGv_vec v)
+{
+ return temp_arg(tcgv_vec_temp(v));
+}
+
static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
{
(void)temp_idx(t); /* trigger embedded assert */
@@ -751,6 +793,11 @@ static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
return (TCGv_ptr)temp_tcgv_i32(t);
}
+static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
+{
+ return (TCGv_vec)temp_tcgv_i32(t);
+}
+
#if TCG_TARGET_REG_BITS == 32
static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
{
@@ -826,9 +873,12 @@ TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
+TCGv_vec tcg_temp_new_vec(TCGType type);
+TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
void tcg_temp_free_i32(TCGv_i32 arg);
void tcg_temp_free_i64(TCGv_i64 arg);
+void tcg_temp_free_vec(TCGv_vec arg);
static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
const char *name)
@@ -910,6 +960,8 @@ enum {
/* Instruction is optional and not implemented by the host, or insn
is generic and should not be implemened by the host. */
TCG_OPF_NOT_PRESENT = 0x10,
+ /* Instruction operands are vectors. */
+ TCG_OPF_VECTOR = 0x20,
};
typedef struct TCGOpDef {
@@ -975,6 +1027,10 @@ TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
TCGv_i32 tcg_const_local_i32(int32_t val);
TCGv_i64 tcg_const_local_i64(int64_t val);
+TCGv_vec tcg_const_zeros_vec(TCGType);
+TCGv_vec tcg_const_ones_vec(TCGType);
+TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
+TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
TCGLabel *gen_new_label(void);
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
new file mode 100644
index 0000000000..dc04c11860
--- /dev/null
+++ b/tcg/tcg-op-vec.c
@@ -0,0 +1,362 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "tcg.h"
+#include "tcg-op.h"
+#include "tcg-mo.h"
+
+/* Reduce the number of ifdefs below. This assumes that all uses of
+ TCGV_HIGH and TCGV_LOW are properly protected by a conditional that
+ the compiler can eliminate. */
+#if TCG_TARGET_REG_BITS == 64
+extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64);
+extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
+#define TCGV_LOW TCGV_LOW_link_error
+#define TCGV_HIGH TCGV_HIGH_link_error
+#endif
+
+void vec_gen_2(TCGOpcode opc, TCGType type, unsigned vece, TCGArg r, TCGArg a)
+{
+ TCGOp *op = tcg_emit_op(opc);
+ TCGOP_VECL(op) = type - TCG_TYPE_V64;
+ TCGOP_VECE(op) = vece;
+ op->args[0] = r;
+ op->args[1] = a;
+}
+
+void vec_gen_3(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg r, TCGArg a, TCGArg b)
+{
+ TCGOp *op = tcg_emit_op(opc);
+ TCGOP_VECL(op) = type - TCG_TYPE_V64;
+ TCGOP_VECE(op) = vece;
+ op->args[0] = r;
+ op->args[1] = a;
+ op->args[2] = b;
+}
+
+void vec_gen_4(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg r, TCGArg a, TCGArg b, TCGArg c)
+{
+ TCGOp *op = tcg_emit_op(opc);
+ TCGOP_VECL(op) = type - TCG_TYPE_V64;
+ TCGOP_VECE(op) = vece;
+ op->args[0] = r;
+ op->args[1] = a;
+ op->args[2] = b;
+ op->args[3] = c;
+}
+
+static void vec_gen_op2(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGType type = rt->base_type;
+
+ tcg_debug_assert(at->base_type == type);
+ vec_gen_2(opc, type, vece, temp_arg(rt), temp_arg(at));
+}
+
+static void vec_gen_op3(TCGOpcode opc, unsigned vece,
+ TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGType type = rt->base_type;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ vec_gen_3(opc, type, vece, temp_arg(rt), temp_arg(at), temp_arg(bt));
+}
+
+void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
+{
+ if (r != a) {
+ vec_gen_op2(INDEX_op_mov_vec, 0, r, a);
+ }
+}
+
+#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
+
+static void tcg_gen_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
+}
+
+TCGv_vec tcg_const_zeros_vec(TCGType type)
+{
+ TCGv_vec ret = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(ret, MO_REG, 0);
+ return ret;
+}
+
+TCGv_vec tcg_const_ones_vec(TCGType type)
+{
+ TCGv_vec ret = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(ret, MO_REG, -1);
+ return ret;
+}
+
+TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec m)
+{
+ TCGTemp *t = tcgv_vec_temp(m);
+ return tcg_const_zeros_vec(t->base_type);
+}
+
+TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
+{
+ TCGTemp *t = tcgv_vec_temp(m);
+ return tcg_const_ones_vec(t->base_type);
+}
+
+void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
+{
+ if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
+ tcg_gen_dupi_vec(r, MO_32, a);
+ } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
+ tcg_gen_dupi_vec(r, MO_64, a);
+ } else {
+ TCGv_i64 c = tcg_const_i64(a);
+ tcg_gen_dup_i64_vec(MO_64, r, c);
+ tcg_temp_free_i64(c);
+ }
+}
+
+void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)
+{
+ tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
+}
+
+void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)
+{
+ tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
+}
+
+void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
+{
+ tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
+}
+
+void tcg_gen_movi_v64(TCGv_vec r, uint64_t a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGArg ri = temp_arg(rt);
+
+ tcg_debug_assert(rt->base_type == TCG_TYPE_V64);
+ if (TCG_TARGET_REG_BITS == 64) {
+ vec_gen_2(INDEX_op_movi_vec, TCG_TYPE_V64, 0, ri, a);
+ } else {
+ vec_gen_3(INDEX_op_movi_vec, TCG_TYPE_V64, 0, ri, a, a >> 32);
+ }
+}
+
+void tcg_gen_movi_v128(TCGv_vec r, uint64_t a, uint64_t b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGArg ri = temp_arg(rt);
+
+ tcg_debug_assert(rt->base_type == TCG_TYPE_V128);
+ if (a == b) {
+ tcg_gen_dup64i_vec(r, a);
+ } else if (TCG_TARGET_REG_BITS == 64) {
+ vec_gen_3(INDEX_op_movi_vec, TCG_TYPE_V128, 0, ri, a, b);
+ } else {
+ TCGOp *op = tcg_emit_op(INDEX_op_movi_vec);
+ TCGOP_VECL(op) = TCG_TYPE_V128 - TCG_TYPE_V64;
+ op->args[0] = ri;
+ op->args[1] = a;
+ op->args[2] = a >> 32;
+ op->args[3] = b;
+ op->args[4] = b >> 32;
+ }
+}
+
+void tcg_gen_movi_v256(TCGv_vec r, uint64_t a, uint64_t b,
+ uint64_t c, uint64_t d)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGTemp *rt = arg_temp(ri);
+
+ tcg_debug_assert(rt->base_type == TCG_TYPE_V256);
+ if (a == b && a == c && a == d) {
+ tcg_gen_dup64i_vec(r, a);
+ } else {
+ TCGOp *op = tcg_emit_op(INDEX_op_movi_vec);
+ TCGOP_VECL(op) = TCG_TYPE_V256 - TCG_TYPE_V64;
+ op->args[0] = ri;
+ if (TCG_TARGET_REG_BITS == 64) {
+ op->args[1] = a;
+ op->args[2] = b;
+ op->args[3] = c;
+ op->args[4] = d;
+ } else {
+ op->args[1] = a;
+ op->args[2] = a >> 32;
+ op->args[3] = b;
+ op->args[4] = b >> 32;
+ op->args[5] = c;
+ op->args[6] = c >> 32;
+ op->args[7] = d;
+ op->args[8] = d >> 32;
+ }
+ }
+}
+
+void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ TCGArg ai = tcgv_i64_arg(a);
+ vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai);
+ } else if (vece == MO_64) {
+ TCGArg al = tcgv_i32_arg(TCGV_LOW(a));
+ TCGArg ah = tcgv_i32_arg(TCGV_HIGH(a));
+ vec_gen_3(INDEX_op_dup2_vec, type, MO_64, ri, al, ah);
+ } else {
+ TCGArg ai = tcgv_i32_arg(TCGV_LOW(a));
+ vec_gen_2(INDEX_op_dup_vec, type, MO_64, ri, ai);
+ }
+}
+
+void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec r, TCGv_i32 a)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGArg ai = tcgv_i32_arg(a);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ vec_gen_2(INDEX_op_dup_vec, type, vece, ri, ai);
+}
+
+static void vec_gen_ldst(TCGOpcode opc, TCGv_vec r, TCGv_ptr b, TCGArg o)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGArg bi = tcgv_ptr_arg(b);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ vec_gen_3(opc, type, 0, ri, bi, o);
+}
+
+void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr b, TCGArg o)
+{
+ vec_gen_ldst(INDEX_op_ld_vec, r, b, o);
+}
+
+void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr b, TCGArg o)
+{
+ vec_gen_ldst(INDEX_op_st_vec, r, b, o);
+}
+
+void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr b, TCGArg o, TCGType low_type)
+{
+ TCGArg ri = tcgv_vec_arg(r);
+ TCGArg bi = tcgv_ptr_arg(b);
+ TCGTemp *rt = arg_temp(ri);
+ TCGType type = rt->base_type;
+
+ tcg_debug_assert(low_type >= TCG_TYPE_V64);
+ tcg_debug_assert(low_type <= type);
+ vec_gen_3(INDEX_op_st_vec, low_type, 0, ri, bi, o);
+}
+
+void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_add_vec, vece, r, a, b);
+}
+
+void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_sub_vec, vece, r, a, b);
+}
+
+void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_and_vec, 0, r, a, b);
+}
+
+void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_or_vec, 0, r, a, b);
+}
+
+void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ vec_gen_op3(INDEX_op_xor_vec, 0, r, a, b);
+}
+
+void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ if (TCG_TARGET_HAS_andc_vec) {
+ vec_gen_op3(INDEX_op_andc_vec, 0, r, a, b);
+ } else {
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
+ tcg_gen_not_vec(0, t, b);
+ tcg_gen_and_vec(0, r, a, t);
+ tcg_temp_free_vec(t);
+ }
+}
+
+void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ if (TCG_TARGET_HAS_orc_vec) {
+ vec_gen_op3(INDEX_op_orc_vec, 0, r, a, b);
+ } else {
+ TCGv_vec t = tcg_temp_new_vec_matching(r);
+ tcg_gen_not_vec(0, t, b);
+ tcg_gen_or_vec(0, r, a, t);
+ tcg_temp_free_vec(t);
+ }
+}
+
+void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ if (TCG_TARGET_HAS_not_vec) {
+ vec_gen_op2(INDEX_op_not_vec, 0, r, a);
+ } else {
+ TCGv_vec t = tcg_const_ones_vec_matching(r);
+ tcg_gen_xor_vec(0, r, a, t);
+ tcg_temp_free_vec(t);
+ }
+}
+
+void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ if (TCG_TARGET_HAS_neg_vec) {
+ vec_gen_op2(INDEX_op_neg_vec, vece, r, a);
+ } else {
+ TCGv_vec t = tcg_const_zeros_vec_matching(r);
+ tcg_gen_sub_vec(vece, r, t, a);
+ tcg_temp_free_vec(t);
+ }
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 93caa0be93..16b8faf66f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -106,6 +106,18 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg);
static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
const int *const_args);
+#if TCG_TARGET_MAYBE_vec
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
+ unsigned vece, const TCGArg *args,
+ const int *const_args);
+#else
+static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
+ unsigned vece, const TCGArg *args,
+ const int *const_args)
+{
+ g_assert_not_reached();
+}
+#endif
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
intptr_t arg2);
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
@@ -146,8 +158,7 @@ struct tcg_region_state {
};
static struct tcg_region_state region;
-
-static TCGRegSet tcg_target_available_regs[2];
+static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT];
static TCGRegSet tcg_target_call_clobber_regs;
#if TCG_TARGET_INSN_UNIT_SIZE == 1
@@ -1026,6 +1037,41 @@ TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
return temp_tcgv_i64(t);
}
+TCGv_vec tcg_temp_new_vec(TCGType type)
+{
+ TCGTemp *t;
+
+#ifdef CONFIG_DEBUG_TCG
+ switch (type) {
+ case TCG_TYPE_V64:
+ assert(TCG_TARGET_HAS_v64);
+ break;
+ case TCG_TYPE_V128:
+ assert(TCG_TARGET_HAS_v128);
+ break;
+ case TCG_TYPE_V256:
+ assert(TCG_TARGET_HAS_v256);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+#endif
+
+ t = tcg_temp_new_internal(type, 0);
+ return temp_tcgv_vec(t);
+}
+
+/* Create a new temp of the same type as an existing temp. */
+TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match)
+{
+ TCGTemp *t = tcgv_vec_temp(match);
+
+ tcg_debug_assert(t->temp_allocated != 0);
+
+ t = tcg_temp_new_internal(t->base_type, 0);
+ return temp_tcgv_vec(t);
+}
+
static void tcg_temp_free_internal(TCGTemp *ts)
{
TCGContext *s = tcg_ctx;
@@ -1057,6 +1103,11 @@ void tcg_temp_free_i64(TCGv_i64 arg)
tcg_temp_free_internal(tcgv_i64_temp(arg));
}
+void tcg_temp_free_vec(TCGv_vec arg)
+{
+ tcg_temp_free_internal(tcgv_vec_temp(arg));
+}
+
TCGv_i32 tcg_const_i32(int32_t val)
{
TCGv_i32 t0;
@@ -1114,6 +1165,9 @@ int tcg_check_temp_count(void)
Test the runtime variable that controls each opcode. */
bool tcg_op_supported(TCGOpcode op)
{
+ const bool have_vec
+ = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256;
+
switch (op) {
case INDEX_op_discard:
case INDEX_op_set_label:
@@ -1327,6 +1381,29 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_mulsh_i64:
return TCG_TARGET_HAS_mulsh_i64;
+ case INDEX_op_mov_vec:
+ case INDEX_op_movi_vec:
+ case INDEX_op_dup_vec:
+ case INDEX_op_dupi_vec:
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ return have_vec;
+ case INDEX_op_dup2_vec:
+ return have_vec && TCG_TARGET_REG_BITS == 32;
+ case INDEX_op_not_vec:
+ return have_vec && TCG_TARGET_HAS_not_vec;
+ case INDEX_op_neg_vec:
+ return have_vec && TCG_TARGET_HAS_neg_vec;
+ case INDEX_op_andc_vec:
+ return have_vec && TCG_TARGET_HAS_andc_vec;
+ case INDEX_op_orc_vec:
+ return have_vec && TCG_TARGET_HAS_orc_vec;
+
case NB_OPS:
break;
}
@@ -1661,6 +1738,14 @@ void tcg_dump_ops(TCGContext *s)
nb_iargs = def->nb_iargs;
nb_cargs = def->nb_cargs;
+ if (c == INDEX_op_movi_vec) {
+ nb_cargs = (64 / TCG_TARGET_REG_BITS) << TCGOP_VECL(op);
+ }
+ if (def->flags & TCG_OPF_VECTOR) {
+ col += qemu_log("v%d,e%d,", 64 << TCGOP_VECL(op),
+ 8 << TCGOP_VECE(op));
+ }
+
k = 0;
for (i = 0; i < nb_oargs; i++) {
if (k != 0) {
@@ -2890,8 +2975,13 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
/* emit instruction */
- tcg_out_op(s, op->opc, new_args, const_args);
-
+ if (def->flags & TCG_OPF_VECTOR) {
+ tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op),
+ new_args, const_args);
+ } else {
+ tcg_out_op(s, op->opc, new_args, const_args);
+ }
+
/* move the outputs in the correct register if needed */
for(i = 0; i < nb_oargs; i++) {
ts = arg_temp(op->args[i]);
@@ -3239,10 +3329,12 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
switch (opc) {
case INDEX_op_mov_i32:
case INDEX_op_mov_i64:
+ case INDEX_op_mov_vec:
tcg_reg_alloc_mov(s, op);
break;
case INDEX_op_movi_i32:
case INDEX_op_movi_i64:
+ case INDEX_op_dupi_vec:
tcg_reg_alloc_movi(s, op);
break;
case INDEX_op_insn_start:
diff --git a/tcg/README b/tcg/README
index 03bfb6acd4..e14990fb9b 100644
--- a/tcg/README
+++ b/tcg/README
@@ -503,6 +503,64 @@ of the memory access.
For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a
64-bit memory access specified in flags.
+********* Host vector operations
+
+All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE.
+The former specifies the length of the vector in log2 64-bit units; the
+later specifies the length of the element (if applicable) in log2 8-bit units.
+E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
+
+* mov_vec v0, v1
+* ld_vec v0, t1
+* st_vec v0, t1
+
+ Move, load and store.
+
+* movi_vec v0, a, b, ...
+
+ Move with constant data. There are arguments to hold the entire
+ vector value, stored little-endian. Note that the way MAX_OPC_PARAM
+ is sized for 64- and 32-bit hosts, there are enough slots for v256,
+ but not a future v512.
+
+ Prefer dupi_vec when possible.
+
+* dup_vec v0, r1
+
+ Duplicate the low N bits of R1 into VECL/VECE copies across V0.
+
+* dupi_vec v0, c
+
+ Similarly, for a constant.
+ Smaller values will be replicated to host register size by the expanders.
+
+* dup2_vec v0, r1, r2
+
+ Duplicate r2:r1 into VECL/64 copies across V0. This opcode is
+ only present for 32-bit hosts.
+
+* add_vec v0, v1, v2
+
+ v0 = v1 + v2, in elements across the vector.
+
+* sub_vec v0, v1, v2
+
+ Similarly, v0 = v1 - v2.
+
+* neg_vec v0, v1
+
+ Similarly, v0 = -v1.
+
+* and_vec v0, v1, v2
+* or_vec v0, v1, v2
+* xor_vec v0, v1, v2
+* andc_vec v0, v1, v2
+* orc_vec v0, v1, v2
+* not_vec v0, v1
+
+ Similarly, logical operations with and without compliment.
+ Note that VECE is unused.
+
*********
Note 1: Some shortcuts are defined when the last operand is known to be
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (3 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 04/26] tcg: Add types and basic operations for host vectors Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-12-06 10:21 ` Kirill Batuzov
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 06/26] tcg: Allow multiple word entries into the constant pool Richard Henderson
` (25 subsequent siblings)
30 siblings, 1 reply; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Makefile.target | 2 +-
accel/tcg/tcg-runtime.h | 29 ++
tcg/tcg-gvec-desc.h | 49 ++
tcg/tcg-op-gvec.h | 152 +++++++
tcg/tcg-op.h | 1 +
accel/tcg/tcg-runtime-gvec.c | 295 ++++++++++++
tcg/tcg-op-gvec.c | 1017 ++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 36 +-
accel/tcg/Makefile.objs | 2 +-
9 files changed, 1573 insertions(+), 10 deletions(-)
create mode 100644 tcg/tcg-gvec-desc.h
create mode 100644 tcg/tcg-op-gvec.h
create mode 100644 accel/tcg/tcg-runtime-gvec.c
create mode 100644 tcg/tcg-op-gvec.c
diff --git a/Makefile.target b/Makefile.target
index 5ca758f13c..d828cec433 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -93,7 +93,7 @@ all: $(PROGS) stap
# cpu emulator library
obj-y += exec.o
obj-y += accel/
-obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o
+obj-$(CONFIG_TCG) += tcg/tcg.o tcg/tcg-op.o tcg/tcg-op-vec.o tcg/tcg-op-gvec.o
obj-$(CONFIG_TCG) += tcg/tcg-common.o tcg/optimize.o
obj-$(CONFIG_TCG_INTERPRETER) += tcg/tci.o
obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 1df17d0ba9..76ee41ce58 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -134,3 +134,32 @@ GEN_ATOMIC_HELPERS(xor_fetch)
GEN_ATOMIC_HELPERS(xchg)
#undef GEN_ATOMIC_HELPERS
+
+DEF_HELPER_FLAGS_3(gvec_mov, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_dup8, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup16, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup32, TCG_CALL_NO_RWG, void, ptr, i32, i32)
+DEF_HELPER_FLAGS_3(gvec_dup64, TCG_CALL_NO_RWG, void, ptr, i32, i64)
+
+DEF_HELPER_FLAGS_4(gvec_add8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_add64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_sub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/tcg-gvec-desc.h b/tcg/tcg-gvec-desc.h
new file mode 100644
index 0000000000..8ba9a8168d
--- /dev/null
+++ b/tcg/tcg-gvec-desc.h
@@ -0,0 +1,49 @@
+/*
+ * Generic vector operation descriptor
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
+#define SIMD_OPRSZ_SHIFT 0
+#define SIMD_OPRSZ_BITS 5
+
+#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
+#define SIMD_MAXSZ_BITS 5
+
+#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
+
+/* Create a descriptor from components. */
+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
+
+/* Extract the operation size from a descriptor. */
+static inline intptr_t simd_oprsz(uint32_t desc)
+{
+ return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
+}
+
+/* Extract the max vector size from a descriptor. */
+static inline intptr_t simd_maxsz(uint32_t desc)
+{
+ return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
+}
+
+/* Extract the operation-specific data from a descriptor. */
+static inline int32_t simd_data(uint32_t desc)
+{
+ return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS);
+}
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
new file mode 100644
index 0000000000..95739946ff
--- /dev/null
+++ b/tcg/tcg-op-gvec.h
@@ -0,0 +1,152 @@
+/*
+ * Generic vector operation expansion
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * "Generic" vectors. All operands are given as offsets from ENV,
+ * and therefore cannot also be allocated via tcg_global_mem_new_*.
+ * OPRSZ is the byte size of the vector upon which the operation is performed.
+ * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared.
+ *
+ * All sizes must be 8 or any multiple of 16.
+ * When OPRSZ is 8, the alignment may be 8, otherwise must be 16.
+ * Operands may completely, but not partially, overlap.
+ */
+
+/* Expand a call to a gvec-style helper, with pointers to two vector
+ operands, and a descriptor (see tcg-gvec-desc.h). */
+typedef void (gen_helper_gvec_2)(TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2 *fn);
+
+/* Similarly, passing an extra pointer (e.g. env or float_status). */
+typedef void (gen_helper_gvec_2_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_2_ptr *fn);
+
+/* Similarly, with three vector operands. */
+typedef void (gen_helper_gvec_3)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_3 *fn);
+
+typedef void (gen_helper_gvec_3_ptr)(TCGv_ptr, TCGv_ptr, TCGv_ptr,
+ TCGv_ptr, TCGv_i32);
+void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_3_ptr *fn);
+
+/* Expand a gvec operation. Either inline or out-of-line depending on
+ the actual vector size and the operations supported by the host. */
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_2 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+} GVecGen2;
+
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
+ void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_3 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load dest as a 3rd source operand. */
+ bool load_dest;
+} GVecGen3;
+
+void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz, const GVecGen2 *);
+void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t opsz, uint32_t clsz, const GVecGen3 *);
+
+/* Expand a specific vector operation. */
+
+void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz);
+
+void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+
+void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+
+void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t s, uint32_t m);
+void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s,
+ uint32_t m, TCGv_i32);
+void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s,
+ uint32_t m, TCGv_i64);
+
+void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
+void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
+void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
+void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
+
+/*
+ * 64-bit vector operations. Use these when the register has been allocated
+ * with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
+ * OPRSZ = MAXSZ = 8.
+ */
+
+void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a);
+void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a);
+void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a);
+
+void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+
+void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 9b0560e4d3..5f49785cb3 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -914,6 +914,7 @@ void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
+void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
void tcg_gen_movi_v64(TCGv_vec, uint64_t);
void tcg_gen_movi_v128(TCGv_vec, uint64_t, uint64_t);
void tcg_gen_movi_v256(TCGv_vec, uint64_t, uint64_t, uint64_t, uint64_t);
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
new file mode 100644
index 0000000000..cd1ce12b7e
--- /dev/null
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -0,0 +1,295 @@
+/*
+ * Generic vectorized operation runtime
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "cpu.h"
+#include "exec/helper-proto.h"
+#include "tcg-gvec-desc.h"
+
+
+/* Virtually all hosts support 16-byte vectors. Those that don't can emulate
+ them via GCC's generic vector extension. This turns out to be simpler and
+ more reliable than getting the compiler to autovectorize.
+
+ In tcg-op-gvec.c, we asserted that both the size and alignment
+ of the data are multiples of 16. */
+
+typedef uint8_t vec8 __attribute__((vector_size(16)));
+typedef uint16_t vec16 __attribute__((vector_size(16)));
+typedef uint32_t vec32 __attribute__((vector_size(16)));
+typedef uint64_t vec64 __attribute__((vector_size(16)));
+
+static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
+{
+ intptr_t maxsz = simd_maxsz(desc);
+ intptr_t i;
+
+ if (unlikely(maxsz > oprsz)) {
+ for (i = oprsz; i < maxsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = 0;
+ }
+ }
+}
+
+void HELPER(gvec_add8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) + *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) + *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) + *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_add64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) + *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) - *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) - *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) - *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) - *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = -*(vec8 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg16)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = -*(vec16 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg32)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = -*(vec32 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = -*(vec64 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mov)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+
+ memcpy(d, a, oprsz);
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup64)(void *d, uint32_t desc, uint64_t c)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ if (c == 0) {
+ oprsz = 0;
+ } else {
+ for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
+ *(uint64_t *)(d + i) = c;
+ }
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup32)(void *d, uint32_t desc, uint32_t c)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ if (c == 0) {
+ oprsz = 0;
+ } else {
+ for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
+ *(uint32_t *)(d + i) = c;
+ }
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_dup16)(void *d, uint32_t desc, uint32_t c)
+{
+ HELPER(gvec_dup32)(d, desc, 0x00010001 * (c & 0xffff));
+}
+
+void HELPER(gvec_dup8)(void *d, uint32_t desc, uint32_t c)
+{
+ HELPER(gvec_dup32)(d, desc, 0x01010101 * (c & 0xff));
+}
+
+void HELPER(gvec_not)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = ~*(vec64 *)(a + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_and)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) & *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_or)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) | *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_xor)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) ^ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_andc)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
new file mode 100644
index 0000000000..925c293f9c
--- /dev/null
+++ b/tcg/tcg-op-gvec.c
@@ -0,0 +1,1017 @@
+/*
+ * Generic vector operation expansion
+ *
+ * Copyright (c) 2017 Linaro
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "tcg.h"
+#include "tcg-op.h"
+#include "tcg-op-gvec.h"
+#include "tcg-gvec-desc.h"
+
+#define REP8(x) ((x) * 0x0101010101010101ull)
+#define REP16(x) ((x) * 0x0001000100010001ull)
+
+#define MAX_UNROLL 4
+
+/* Verify vector size and alignment rules. OFS should be the OR of all
+ of the operand offsets so that we can check them all at once. */
+static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
+{
+ uint32_t align = maxsz > 16 || oprsz >= 16 ? 15 : 7;
+ tcg_debug_assert(oprsz > 0);
+ tcg_debug_assert(oprsz <= maxsz);
+ tcg_debug_assert((oprsz & align) == 0);
+ tcg_debug_assert((maxsz & align) == 0);
+ tcg_debug_assert((ofs & align) == 0);
+}
+
+/* Verify vector overlap rules for two operands. */
+static void check_overlap_2(uint32_t d, uint32_t a, uint32_t s)
+{
+ tcg_debug_assert(d == a || d + s <= a || a + s <= d);
+}
+
+/* Verify vector overlap rules for three operands. */
+static void check_overlap_3(uint32_t d, uint32_t a, uint32_t b, uint32_t s)
+{
+ check_overlap_2(d, a, s);
+ check_overlap_2(d, b, s);
+ check_overlap_2(a, b, s);
+}
+
+/* Create a descriptor from components. */
+uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
+{
+ uint32_t desc = 0;
+
+ assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
+ assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
+ assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+
+ oprsz = (oprsz / 8) - 1;
+ maxsz = (maxsz / 8) - 1;
+ desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
+ desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
+ desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
+
+ return desc;
+}
+
+/* Generate a call to a gvec-style helper with two vector operands. */
+void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_2 *fn)
+{
+ TCGv_ptr a0, a1;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+
+ fn(a0, a1, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands. */
+void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, int32_t data,
+ gen_helper_gvec_3 *fn)
+{
+ TCGv_ptr a0, a1, a2;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+ a2 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
+
+ fn(a0, a1, a2, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_ptr(a2);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_2_ptr *fn)
+{
+ TCGv_ptr a0, a1;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+
+ fn(a0, a1, ptr, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_i32(desc);
+}
+
+/* Generate a call to a gvec-style helper with three vector operands
+ and an extra pointer operand. */
+void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
+ int32_t data, gen_helper_gvec_3_ptr *fn)
+{
+ TCGv_ptr a0, a1, a2;
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+
+ a0 = tcg_temp_new_ptr();
+ a1 = tcg_temp_new_ptr();
+ a2 = tcg_temp_new_ptr();
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ tcg_gen_addi_ptr(a1, cpu_env, aofs);
+ tcg_gen_addi_ptr(a2, cpu_env, bofs);
+
+ fn(a0, a1, a2, ptr, desc);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_ptr(a1);
+ tcg_temp_free_ptr(a2);
+ tcg_temp_free_i32(desc);
+}
+
+/* Return true if we want to implement something of OPRSZ bytes
+ in units of LNSZ. This limits the expansion of inline code. */
+static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz)
+{
+ uint32_t lnct = oprsz / lnsz;
+ return lnct >= 1 && lnct <= MAX_UNROLL;
+}
+
+static void expand_clr(uint32_t dofs, uint32_t maxsz);
+
+/* Set OPRSZ bytes at DOFS to replications of IN or IN_C. */
+static void do_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i32 in, uint32_t in_c,
+ void (*ool)(TCGv_ptr, TCGv_i32, TCGv_i32))
+{
+ TCGv_vec t_vec;
+ uint32_t i;
+
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ t_vec = tcg_temp_new_vec(TCG_TYPE_V256);
+ } else if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ t_vec = tcg_temp_new_vec(TCG_TYPE_V128);
+ } else if (TCG_TARGET_HAS_v64 && check_size_impl(oprsz, 8)) {
+ t_vec = tcg_temp_new_vec(TCG_TYPE_V64);
+ } else {
+ TCGv_i32 t_i32 = in ? in : tcg_const_i32(in_c);
+
+ if (check_size_impl(oprsz, 4)) {
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_st_i32(t_i32, cpu_env, dofs + i);
+ }
+ if (in == NULL) {
+ tcg_temp_free_i32(t_i32);
+ }
+ goto done;
+ } else {
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ ool(a0, desc, t_i32);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_i32(desc);
+ if (in == NULL) {
+ tcg_temp_free_i32(t_i32);
+ }
+ return;
+ }
+ }
+
+ if (in) {
+ tcg_gen_dup_i32_vec(vece, t_vec, in);
+ } else {
+ tcg_gen_dup32i_vec(t_vec, in_c);
+ }
+
+ i = 0;
+ if (TCG_TARGET_HAS_v256) {
+ for (; i + 32 <= oprsz; i += 32) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
+ }
+ }
+ if (TCG_TARGET_HAS_v128) {
+ for (; i + 16 <= oprsz; i += 16) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
+ }
+ }
+ if (TCG_TARGET_HAS_v64) {
+ for (; i < oprsz; i += 8) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
+ }
+ }
+
+ done:
+ tcg_debug_assert(i == oprsz);
+ if (i < maxsz) {
+ expand_clr(dofs + i, maxsz - i);
+ }
+}
+
+/* Likewise, but with 64-bit quantities. */
+static void do_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i64 in, uint64_t in_c)
+{
+ TCGv_vec t_vec;
+ uint32_t i;
+
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ t_vec = tcg_temp_new_vec(TCG_TYPE_V256);
+ } else if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ t_vec = tcg_temp_new_vec(TCG_TYPE_V128);
+ } else if (TCG_TARGET_HAS_v64 && TCG_TARGET_REG_BITS == 32
+ && check_size_impl(oprsz, 8)) {
+ t_vec = tcg_temp_new_vec(TCG_TYPE_V64);
+ } else {
+ TCGv_i64 t_i64 = in ? in : tcg_const_i64(in_c);
+
+ if (check_size_impl(oprsz, 8)) {
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_st_i64(t_i64, cpu_env, dofs + i);
+ }
+ if (in == NULL) {
+ tcg_temp_free_i64(t_i64);
+ }
+ goto done;
+ } else {
+ TCGv_ptr a0 = tcg_temp_new_ptr();
+ TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
+
+ tcg_gen_addi_ptr(a0, cpu_env, dofs);
+ gen_helper_gvec_dup64(a0, desc, t_i64);
+
+ tcg_temp_free_ptr(a0);
+ tcg_temp_free_i32(desc);
+ if (in == NULL) {
+ tcg_temp_free_i64(t_i64);
+ }
+ return;
+ }
+ }
+
+ if (in) {
+ tcg_gen_dup_i64_vec(vece, t_vec, in);
+ } else {
+ tcg_gen_dup64i_vec(t_vec, in_c);
+ }
+
+ i = 0;
+ if (TCG_TARGET_HAS_v256) {
+ for (; i + 32 <= oprsz; i += 32) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
+ }
+ }
+ if (TCG_TARGET_HAS_v128) {
+ for (; i + 16 <= oprsz; i += 16) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
+ }
+ }
+ if (TCG_TARGET_HAS_v64) {
+ for (; i < oprsz; i += 8) {
+ tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
+ }
+ }
+
+ done:
+ tcg_debug_assert(i == oprsz);
+ if (i < maxsz) {
+ expand_clr(dofs + i, maxsz - i);
+ }
+}
+
+/* Likewise, but with zero. */
+static void expand_clr(uint32_t dofs, uint32_t maxsz)
+{
+ if (TCG_TARGET_REG_BITS == 64) {
+ do_dup_i64(MO_64, dofs, maxsz, maxsz, NULL, 0);
+ } else {
+ do_dup_i32(MO_32, dofs, maxsz, maxsz, NULL, 0, gen_helper_gvec_dup32);
+ }
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using i32 elements. */
+static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t opsz,
+ void (*fni)(TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ fni(t0, t0);
+ tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
+static void expand_3_i32(uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, bool load_dest,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i32(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1);
+ tcg_gen_st_i32(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
+static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t opsz,
+ void (*fni)(TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ fni(t0, t0);
+ tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
+static void expand_3_i64(uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, bool load_dest,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i64(t2, cpu_env, dofs + i);
+ }
+ fni(t2, t0, t1);
+ tcg_gen_st_i64(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t0);
+}
+
+/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
+static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t tysz, TCGType type,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ fni(vece, t0, t0);
+ tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t0);
+}
+
+/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
+static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz,
+ uint32_t tysz, TCGType type, bool load_dest,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ if (load_dest) {
+ tcg_gen_ld_vec(t2, cpu_env, dofs + i);
+ }
+ fni(vece, t2, t0, t1);
+ tcg_gen_st_vec(t2, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t0);
+}
+
+/* Expand a vector two-operand operation. */
+void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, maxsz);
+
+ /* Quick check for sizes we won't support inline. */
+ if (oprsz > MAX_UNROLL * 32 || maxsz > MAX_UNROLL * 32) {
+ goto do_ool;
+ }
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+ /* ??? For maxsz > oprsz, the host may be able to use an op-sized
+ operation, zeroing the balance of the register. We can then
+ use a cl-sized store to implement the clearing without an extra
+ store operation. This is true for aarch64 and x86_64 hosts. */
+
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_2_vec(g->vece, dofs, aofs, done, 32, TCG_TYPE_V256, g->fniv);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 16);
+ expand_2_vec(g->vece, dofs, aofs, done, 16, TCG_TYPE_V128, g->fniv);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (check_size_impl(oprsz, 8)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 8);
+ if (TCG_TARGET_HAS_v64 && !g->prefer_i64) {
+ expand_2_vec(g->vece, dofs, aofs, done, 8, TCG_TYPE_V64, g->fniv);
+ } else if (g->fni8) {
+ expand_2_i64(dofs, aofs, done, g->fni8);
+ } else {
+ done = 0;
+ }
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (g->fni4 && check_size_impl(oprsz, 4)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 4);
+ expand_2_i32(dofs, aofs, done, g->fni4);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (oprsz == 0) {
+ if (maxsz != 0) {
+ expand_clr(dofs, maxsz);
+ }
+ return;
+ }
+
+ do_ool:
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, 0, g->fno);
+}
+
+/* Expand a vector three-operand operation. */
+void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, maxsz);
+
+ /* Quick check for sizes we won't support inline. */
+ if (oprsz > MAX_UNROLL * 32 || maxsz > MAX_UNROLL * 32) {
+ goto do_ool;
+ }
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+ /* ??? For maxsz > oprsz, the host may be able to use an op-sized
+ operation, zeroing the balance of the register. We can then
+ use a cl-sized store to implement the clearing without an extra
+ store operation. This is true for aarch64 and x86_64 hosts. */
+
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_3_vec(g->vece, dofs, aofs, bofs, done, 32, TCG_TYPE_V256,
+ g->load_dest, g->fniv);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 16);
+ expand_3_vec(g->vece, dofs, aofs, bofs, done, 16, TCG_TYPE_V128,
+ g->load_dest, g->fniv);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (check_size_impl(oprsz, 8)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 8);
+ if (TCG_TARGET_HAS_v64 && !g->prefer_i64) {
+ expand_3_vec(g->vece, dofs, aofs, bofs, done, 8, TCG_TYPE_V64,
+ g->load_dest, g->fniv);
+ } else if (g->fni8) {
+ expand_3_i64(dofs, aofs, bofs, done, g->load_dest, g->fni8);
+ } else {
+ done = 0;
+ }
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (g->fni4 && check_size_impl(oprsz, 4)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 4);
+ expand_3_i32(dofs, aofs, bofs, done, g->load_dest, g->fni4);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (oprsz == 0) {
+ if (maxsz != 0) {
+ expand_clr(dofs, maxsz);
+ }
+ return;
+ }
+
+ do_ool:
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, g->fno);
+}
+
+/*
+ * Expand specific vector operations.
+ */
+
+static void vec_mov2(unsigned vece, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_mov_vec(a, b);
+}
+
+void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen2 g = {
+ .fni8 = tcg_gen_mov_i64,
+ .fniv = vec_mov2,
+ .fno = gen_helper_gvec_mov,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_2(dofs, aofs, opsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i32 in)
+{
+ typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32);
+ static dup_fn * const fns[3] = {
+ gen_helper_gvec_dup8,
+ gen_helper_gvec_dup16,
+ gen_helper_gvec_dup32
+ };
+
+ check_size_align(oprsz, maxsz, dofs);
+ tcg_debug_assert(vece <= MO_32);
+ do_dup_i32(vece, dofs, oprsz, maxsz, in, 0, fns[vece]);
+}
+
+void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, TCGv_i64 in)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ tcg_debug_assert(vece <= MO_64);
+ if (vece <= MO_32) {
+ /* This works for both host register sizes. */
+ tcg_gen_gvec_dup_i32(vece, dofs, oprsz, maxsz, (TCGv_i32)in);
+ } else {
+ do_dup_i64(vece, dofs, oprsz, maxsz, in, 0);
+ }
+}
+
+void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ tcg_debug_assert(vece <= MO_64);
+ if (vece <= MO_32) {
+ TCGv_i32 in = tcg_temp_new_i32();
+ switch (vece) {
+ case MO_8:
+ tcg_gen_ld8u_i32(in, cpu_env, aofs);
+ break;
+ case MO_16:
+ tcg_gen_ld16u_i32(in, cpu_env, aofs);
+ break;
+ case MO_32:
+ tcg_gen_ld_i32(in, cpu_env, aofs);
+ break;
+ }
+ tcg_gen_gvec_dup_i32(vece, dofs, oprsz, maxsz, in);
+ tcg_temp_free_i32(in);
+ } else {
+ TCGv_i64 in = tcg_temp_new_i64();
+ tcg_gen_ld_i64(in, cpu_env, aofs);
+ tcg_gen_gvec_dup_i64(MO_64, dofs, oprsz, maxsz, in);
+ tcg_temp_free_i64(in);
+ }
+}
+
+void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint64_t x)
+{
+ check_size_align(oprsz, maxsz, dofs);
+ do_dup_i64(MO_64, dofs, oprsz, maxsz, NULL, x);
+}
+
+void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint32_t x)
+{
+ if (TCG_TARGET_REG_BITS == 64) {
+ do_dup_i64(MO_64, dofs, oprsz, maxsz, NULL, deposit64(x, 32, 32, x));
+ } else {
+ do_dup_i32(MO_32, dofs, oprsz, maxsz, NULL, x, gen_helper_gvec_dup32);
+ }
+}
+
+void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint16_t x)
+{
+ tcg_gen_gvec_dup32i(dofs, oprsz, maxsz, 0x00010001 * x);
+}
+
+void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
+ uint32_t maxsz, uint8_t x)
+{
+ tcg_gen_gvec_dup32i(dofs, oprsz, maxsz, 0x01010101 * x);
+}
+
+void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen2 g = {
+ .fni8 = tcg_gen_not_i64,
+ .fniv = tcg_gen_not_vec,
+ .fno = gen_helper_gvec_not,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_2(dofs, aofs, opsz, maxsz, &g);
+}
+
+/* Perform a vector addition using normal addition and a mask. The mask
+ should be the sign bit of each lane. This 6-operation form is more
+ efficient than separate additions when there are 4 or more lanes in
+ the 64-bit operation. */
+static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_andc_i64(t1, a, m);
+ tcg_gen_andc_i64(t2, b, m);
+ tcg_gen_xor_i64(t3, a, b);
+ tcg_gen_add_i64(d, t1, t2);
+ tcg_gen_and_i64(t3, t3, m);
+ tcg_gen_xor_i64(d, d, t3);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP8(0x80));
+ gen_addv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP16(0x8000));
+ gen_addv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t1, a, ~0xffffffffull);
+ tcg_gen_add_i64(t2, a, b);
+ tcg_gen_add_i64(t1, t1, b);
+ tcg_gen_deposit_i64(d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = tcg_gen_vec_add8_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add8,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_add16_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add16,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_add_i32,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add32,
+ .opc = INDEX_op_add_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_add_i64,
+ .fniv = tcg_gen_add_vec,
+ .fno = gen_helper_gvec_add64,
+ .opc = INDEX_op_add_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g[vece]);
+}
+
+/* Perform a vector subtraction using normal subtraction and a mask.
+ Compare gen_addv_mask above. */
+static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_or_i64(t1, a, m);
+ tcg_gen_andc_i64(t2, b, m);
+ tcg_gen_eqv_i64(t3, a, b);
+ tcg_gen_sub_i64(d, t1, t2);
+ tcg_gen_and_i64(t3, t3, m);
+ tcg_gen_xor_i64(d, d, t3);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP8(0x80));
+ gen_subv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP16(0x8000));
+ gen_subv_mask(d, a, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t1, b, ~0xffffffffull);
+ tcg_gen_sub_i64(t2, a, b);
+ tcg_gen_sub_i64(t1, a, t1);
+ tcg_gen_deposit_i64(d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = tcg_gen_vec_sub8_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub8,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_sub16_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub16,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_sub_i32,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub32,
+ .opc = INDEX_op_sub_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_sub_i64,
+ .fniv = tcg_gen_sub_vec,
+ .fno = gen_helper_gvec_sub64,
+ .opc = INDEX_op_sub_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g[vece]);
+}
+
+/* Perform a vector negation using normal negation and a mask.
+ Compare gen_subv_mask above. */
+static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
+{
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+
+ tcg_gen_andc_i64(t3, m, b);
+ tcg_gen_andc_i64(t2, b, m);
+ tcg_gen_sub_i64(d, m, t2);
+ tcg_gen_xor_i64(d, d, t3);
+
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t3);
+}
+
+void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP8(0x80));
+ gen_negv_mask(d, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 m = tcg_const_i64(REP16(0x8000));
+ gen_negv_mask(d, b, m);
+ tcg_temp_free_i64(m);
+}
+
+void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(t1, b, ~0xffffffffull);
+ tcg_gen_neg_i64(t2, b);
+ tcg_gen_neg_i64(t1, t1);
+ tcg_gen_deposit_i64(d, t1, t2, 0, 32);
+
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen2 g[4] = {
+ { .fni8 = tcg_gen_vec_neg8_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg8,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_neg16_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg16,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_neg_i32,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg32,
+ .opc = INDEX_op_neg_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_neg_i64,
+ .fniv = tcg_gen_neg_vec,
+ .fno = gen_helper_gvec_neg64,
+ .opc = INDEX_op_neg_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2(dofs, aofs, opsz, maxsz, &g[vece]);
+}
+
+void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_and_i64,
+ .fniv = tcg_gen_and_vec,
+ .fno = gen_helper_gvec_and,
+ .opc = INDEX_op_and_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_or_i64,
+ .fniv = tcg_gen_or_vec,
+ .fno = gen_helper_gvec_or,
+ .opc = INDEX_op_or_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_xor_i64,
+ .fniv = tcg_gen_xor_vec,
+ .fno = gen_helper_gvec_xor,
+ .opc = INDEX_op_xor_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_andc_i64,
+ .fniv = tcg_gen_andc_vec,
+ .fno = gen_helper_gvec_andc,
+ .opc = INDEX_op_andc_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g);
+}
+
+void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g = {
+ .fni8 = tcg_gen_orc_i64,
+ .fniv = tcg_gen_orc_vec,
+ .fno = gen_helper_gvec_orc,
+ .opc = INDEX_op_orc_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ };
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g);
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index dc04c11860..5cfe4af6bd 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -104,7 +104,7 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
-static void tcg_gen_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
+static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
{
TCGTemp *rt = tcgv_vec_temp(r);
vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
@@ -113,14 +113,14 @@ static void tcg_gen_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
TCGv_vec tcg_const_zeros_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(ret, MO_REG, 0);
+ do_dupi_vec(ret, MO_REG, 0);
return ret;
}
TCGv_vec tcg_const_ones_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(ret, MO_REG, -1);
+ do_dupi_vec(ret, MO_REG, -1);
return ret;
}
@@ -139,9 +139,9 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
{
if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
- tcg_gen_dupi_vec(r, MO_32, a);
+ do_dupi_vec(r, MO_32, a);
} else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
- tcg_gen_dupi_vec(r, MO_64, a);
+ do_dupi_vec(r, MO_64, a);
} else {
TCGv_i64 c = tcg_const_i64(a);
tcg_gen_dup_i64_vec(MO_64, r, c);
@@ -151,17 +151,37 @@ void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
+ do_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffffffffu) * a);
}
void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
+ do_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xffff) * (a & 0xffff));
}
void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
{
- tcg_gen_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
+ do_dupi_vec(r, MO_REG, ((TCGArg)-1 / 0xff) * (a & 0xff));
+}
+
+void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
+{
+ switch (vece) {
+ case MO_8:
+ tcg_gen_dup8i_vec(r, a);
+ break;
+ case MO_16:
+ tcg_gen_dup16i_vec(r, a);
+ break;
+ case MO_32:
+ tcg_gen_dup32i_vec(r, a);
+ break;
+ case MO_64:
+ tcg_gen_dup64i_vec(r, a);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
void tcg_gen_movi_v64(TCGv_vec r, uint64_t a)
diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs
index 228cd84fa4..d381a02f34 100644
--- a/accel/tcg/Makefile.objs
+++ b/accel/tcg/Makefile.objs
@@ -1,6 +1,6 @@
obj-$(CONFIG_SOFTMMU) += tcg-all.o
obj-$(CONFIG_SOFTMMU) += cputlb.o
-obj-y += tcg-runtime.o
+obj-y += tcg-runtime.o tcg-runtime-gvec.o
obj-y += cpu-exec.o cpu-exec-common.o translate-all.o
obj-y += translator.o
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders Richard Henderson
@ 2017-12-06 10:21 ` Kirill Batuzov
2017-12-08 21:35 ` Richard Henderson
0 siblings, 1 reply; 36+ messages in thread
From: Kirill Batuzov @ 2017-12-06 10:21 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, 21 Nov 2017, Richard Henderson wrote:
> diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
> new file mode 100644
> index 0000000000..925c293f9c
> --- /dev/null
> +++ b/tcg/tcg-op-gvec.c
<...>
> +/* Set OPRSZ bytes at DOFS to replications of IN or IN_C. */
> +static void do_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, TCGv_i32 in, uint32_t in_c,
> + void (*ool)(TCGv_ptr, TCGv_i32, TCGv_i32))
> +{
> + TCGv_vec t_vec;
> + uint32_t i;
> +
> + if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
> + t_vec = tcg_temp_new_vec(TCG_TYPE_V256);
> + } else if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
> + t_vec = tcg_temp_new_vec(TCG_TYPE_V128);
> + } else if (TCG_TARGET_HAS_v64 && check_size_impl(oprsz, 8)) {
> + t_vec = tcg_temp_new_vec(TCG_TYPE_V64);
> + } else {
> + TCGv_i32 t_i32 = in ? in : tcg_const_i32(in_c);
> +
> + if (check_size_impl(oprsz, 4)) {
> + for (i = 0; i < oprsz; i += 4) {
> + tcg_gen_st_i32(t_i32, cpu_env, dofs + i);
> + }
You are ignoring VECE argument here and always duplicate a 32-bit value.
For this to be correct for smaller VECE, you need to prepare this 32-bit
value beforehand. The current code produces incorrect expansion:
IN:
0x004005e8: d2824682 movz x2, #0x1234
0x004005ec: 4e010c41 dup v1.16b, w2
OP:
---- 00000000004005e8 0000000000000000 0000000000000000
movi_i64 x2,$0x1234
---- 00000000004005ec 0000000000000000 0000000000000000
st_i32 x2,env,$0x8b0
st_i32 x2,env,$0x8b4
st_i32 x2,env,$0x8b8
st_i32 x2,env,$0x8bc
> + if (in == NULL) {
> + tcg_temp_free_i32(t_i32);
> + }
> + goto done;
> + } else {
> + TCGv_ptr a0 = tcg_temp_new_ptr();
> + TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
> +
> + tcg_gen_addi_ptr(a0, cpu_env, dofs);
> + ool(a0, desc, t_i32);
> +
> + tcg_temp_free_ptr(a0);
> + tcg_temp_free_i32(desc);
> + if (in == NULL) {
> + tcg_temp_free_i32(t_i32);
> + }
> + return;
> + }
> + }
> +
> + if (in) {
> + tcg_gen_dup_i32_vec(vece, t_vec, in);
> + } else {
> + tcg_gen_dup32i_vec(t_vec, in_c);
May be it'll be better to call this function tcg_gen_dupi_i32_vec?
This will go along with current naming conventions like tcg_gen_addi_i32.
> + }
> +
> + i = 0;
> + if (TCG_TARGET_HAS_v256) {
> + for (; i + 32 <= oprsz; i += 32) {
> + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V256);
> + }
> + }
> + if (TCG_TARGET_HAS_v128) {
> + for (; i + 16 <= oprsz; i += 16) {
> + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V128);
> + }
> + }
> + if (TCG_TARGET_HAS_v64) {
> + for (; i < oprsz; i += 8) {
> + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64);
> + }
> + }
> +
> + done:
> + tcg_debug_assert(i == oprsz);
> + if (i < maxsz) {
> + expand_clr(dofs + i, maxsz - i);
> + }
> +}
> +
<...>
(the following is context)
> +void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, TCGv_i32 in)
> +{
> + typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32);
> + static dup_fn * const fns[3] = {
> + gen_helper_gvec_dup8,
> + gen_helper_gvec_dup16,
> + gen_helper_gvec_dup32
> + };
> +
> + check_size_align(oprsz, maxsz, dofs);
> + tcg_debug_assert(vece <= MO_32);
> + do_dup_i32(vece, dofs, oprsz, maxsz, in, 0, fns[vece]);
> +}
> +
> +void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, TCGv_i64 in)
> +{
> + check_size_align(oprsz, maxsz, dofs);
> + tcg_debug_assert(vece <= MO_64);
> + if (vece <= MO_32) {
> + /* This works for both host register sizes. */
> + tcg_gen_gvec_dup_i32(vece, dofs, oprsz, maxsz, (TCGv_i32)in);
> + } else {
> + do_dup_i64(vece, dofs, oprsz, maxsz, in, 0);
> + }
> +}
> +
> +void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs,
> + uint32_t oprsz, uint32_t maxsz)
> +{
> + tcg_debug_assert(vece <= MO_64);
> + if (vece <= MO_32) {
> + TCGv_i32 in = tcg_temp_new_i32();
> + switch (vece) {
> + case MO_8:
> + tcg_gen_ld8u_i32(in, cpu_env, aofs);
> + break;
> + case MO_16:
> + tcg_gen_ld16u_i32(in, cpu_env, aofs);
> + break;
> + case MO_32:
> + tcg_gen_ld_i32(in, cpu_env, aofs);
> + break;
> + }
> + tcg_gen_gvec_dup_i32(vece, dofs, oprsz, maxsz, in);
> + tcg_temp_free_i32(in);
> + } else {
> + TCGv_i64 in = tcg_temp_new_i64();
> + tcg_gen_ld_i64(in, cpu_env, aofs);
> + tcg_gen_gvec_dup_i64(MO_64, dofs, oprsz, maxsz, in);
> + tcg_temp_free_i64(in);
> + }
> +}
> +
> +void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, uint64_t x)
> +{
> + check_size_align(oprsz, maxsz, dofs);
> + do_dup_i64(MO_64, dofs, oprsz, maxsz, NULL, x);
> +}
> +
> +void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, uint32_t x)
> +{
> + if (TCG_TARGET_REG_BITS == 64) {
> + do_dup_i64(MO_64, dofs, oprsz, maxsz, NULL, deposit64(x, 32, 32, x));
> + } else {
> + do_dup_i32(MO_32, dofs, oprsz, maxsz, NULL, x, gen_helper_gvec_dup32);
> + }
> +}
> +
> +void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, uint16_t x)
> +{
> + tcg_gen_gvec_dup32i(dofs, oprsz, maxsz, 0x00010001 * x);
> +}
> +
> +void tcg_gen_gvec_dup8i(uint32_t dofs, uint32_t oprsz,
> + uint32_t maxsz, uint8_t x)
> +{
> + tcg_gen_gvec_dup32i(dofs, oprsz, maxsz, 0x01010101 * x);
> +}
> +
--
Kirill
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders
2017-12-06 10:21 ` Kirill Batuzov
@ 2017-12-08 21:35 ` Richard Henderson
0 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-12-08 21:35 UTC (permalink / raw)
To: Kirill Batuzov; +Cc: qemu-devel
On 12/06/2017 02:21 AM, Kirill Batuzov wrote:
> IN:
> 0x004005e8: d2824682 movz x2, #0x1234
> 0x004005ec: 4e010c41 dup v1.16b, w2
>
> OP:
>
> ---- 00000000004005e8 0000000000000000 0000000000000000
> movi_i64 x2,$0x1234
>
> ---- 00000000004005ec 0000000000000000 0000000000000000
> st_i32 x2,env,$0x8b0
> st_i32 x2,env,$0x8b4
> st_i32 x2,env,$0x8b8
> st_i32 x2,env,$0x8bc
Fixed.
---- 0000000000400078 0000000000000000 0000000000000000
movi_i64 x2,$0x1234 sync: 0 dead: 0
---- 000000000040007c 0000000000000000 0000000000000000
movi_i32 tmp0,$0x34343434
st_i32 tmp0,env,$0x8b0
st_i32 tmp0,env,$0x8b4
st_i32 tmp0,env,$0x8b8
st_i32 tmp0,env,$0x8bc dead: 0
Thanks,
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v6 06/26] tcg: Allow multiple word entries into the constant pool
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (4 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 07/26] tcg: Add tcg_signed_cond Richard Henderson
` (24 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
This will be required for storing vector constants.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-pool.inc.c | 115 +++++++++++++++++++++++++++++++++++++++++++----------
1 file changed, 93 insertions(+), 22 deletions(-)
diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
index 8a85131405..0f76e7bee3 100644
--- a/tcg/tcg-pool.inc.c
+++ b/tcg/tcg-pool.inc.c
@@ -22,39 +22,110 @@
typedef struct TCGLabelPoolData {
struct TCGLabelPoolData *next;
- tcg_target_ulong data;
tcg_insn_unit *label;
- intptr_t addend;
- int type;
+ int addend : 32;
+ int rtype : 16;
+ int nlong : 16;
+ tcg_target_ulong data[];
} TCGLabelPoolData;
-static void new_pool_label(TCGContext *s, tcg_target_ulong data, int type,
- tcg_insn_unit *label, intptr_t addend)
+static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype,
+ tcg_insn_unit *label, int addend)
{
- TCGLabelPoolData *n = tcg_malloc(sizeof(*n));
- TCGLabelPoolData *i, **pp;
+ TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData)
+ + sizeof(tcg_target_ulong) * nlong);
- n->data = data;
n->label = label;
- n->type = type;
n->addend = addend;
+ n->rtype = rtype;
+ n->nlong = nlong;
+ return n;
+}
+
+static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n)
+{
+ TCGLabelPoolData *i, **pp;
+ int nlong = n->nlong;
/* Insertion sort on the pool. */
- for (pp = &s->pool_labels; (i = *pp) && i->data < data; pp = &i->next) {
- continue;
+ for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) {
+ if (nlong > i->nlong) {
+ break;
+ }
+ if (nlong < i->nlong) {
+ continue;
+ }
+ if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) {
+ break;
+ }
}
n->next = *pp;
*pp = n;
}
+/* The "usual" for generic integer code. */
+static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype,
+ tcg_insn_unit *label, int addend)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend);
+ n->data[0] = d;
+ new_pool_insert(s, n);
+}
+
+/* For v64 or v128, depending on the host. */
+static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label,
+ int addend, tcg_target_ulong d0,
+ tcg_target_ulong d1)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ new_pool_insert(s, n);
+}
+
+/* For v128 or v256, depending on the host. */
+static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label,
+ int addend, tcg_target_ulong d0,
+ tcg_target_ulong d1, tcg_target_ulong d2,
+ tcg_target_ulong d3)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ n->data[2] = d2;
+ n->data[3] = d3;
+ new_pool_insert(s, n);
+}
+
+/* For v256, for 32-bit host. */
+static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
+ int addend, tcg_target_ulong d0,
+ tcg_target_ulong d1, tcg_target_ulong d2,
+ tcg_target_ulong d3, tcg_target_ulong d4,
+ tcg_target_ulong d5, tcg_target_ulong d6,
+ tcg_target_ulong d7)
+{
+ TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend);
+ n->data[0] = d0;
+ n->data[1] = d1;
+ n->data[2] = d2;
+ n->data[3] = d3;
+ n->data[4] = d4;
+ n->data[5] = d5;
+ n->data[6] = d6;
+ n->data[7] = d7;
+ new_pool_insert(s, n);
+}
+
/* To be provided by cpu/tcg-target.inc.c. */
static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
static bool tcg_out_pool_finalize(TCGContext *s)
{
TCGLabelPoolData *p = s->pool_labels;
- tcg_target_ulong d, *a;
+ TCGLabelPoolData *l = NULL;
+ void *a;
if (p == NULL) {
return true;
@@ -62,24 +133,24 @@ static bool tcg_out_pool_finalize(TCGContext *s)
/* ??? Round up to qemu_icache_linesize, but then do not round
again when allocating the next TranslationBlock structure. */
- a = (void *)ROUND_UP((uintptr_t)s->code_ptr, sizeof(tcg_target_ulong));
+ a = (void *)ROUND_UP((uintptr_t)s->code_ptr,
+ sizeof(tcg_target_ulong) * p->nlong);
tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr);
s->data_gen_ptr = a;
- /* Ensure the first comparison fails. */
- d = p->data + 1;
-
for (; p != NULL; p = p->next) {
- if (p->data != d) {
- d = p->data;
- if (unlikely((void *)a > s->code_gen_highwater)) {
+ size_t size = sizeof(tcg_target_ulong) * p->nlong;
+ if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
+ if (unlikely(a > s->code_gen_highwater)) {
return false;
}
- *a++ = d;
+ memcpy(a, p->data, size);
+ a += size;
+ l = p;
}
- patch_reloc(p->label, p->type, (intptr_t)(a - 1), p->addend);
+ patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend);
}
- s->code_ptr = (void *)a;
+ s->code_ptr = a;
return true;
}
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 07/26] tcg: Add tcg_signed_cond
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (5 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 06/26] tcg: Allow multiple word entries into the constant pool Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 08/26] target/arm: Align vector registers Richard Henderson
` (23 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Complimenting the existing tcg_unsigned_cond.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 2acebd387a..49d4c5fe05 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -517,6 +517,12 @@ static inline TCGCond tcg_unsigned_cond(TCGCond c)
return c & 2 ? (TCGCond)(c ^ 6) : c;
}
+/* Create a "signed" version of an "unsigned" comparison. */
+static inline TCGCond tcg_signed_cond(TCGCond c)
+{
+ return c & 4 ? (TCGCond)(c ^ 6) : c;
+}
+
/* Must a comparison be considered unsigned? */
static inline bool is_unsigned_cond(TCGCond c)
{
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 08/26] target/arm: Align vector registers
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (6 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 07/26] tcg: Add tcg_signed_cond Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 09/26] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
` (22 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 89d49cdcb2..8238edaba9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -492,7 +492,7 @@ typedef struct CPUARMState {
* the two execution states, and means we do not need to explicitly
* map these registers when changing states.
*/
- float64 regs[64];
+ float64 regs[64] QEMU_ALIGNED(16);
uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 09/26] target/arm: Use vector infrastructure for aa64 add/sub/logic
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (7 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 08/26] target/arm: Align vector registers Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 10/26] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
` (21 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 207 +++++++++++++++++++++++++++++----------------
1 file changed, 134 insertions(+), 73 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ba94f7d045..572af456d1 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -21,6 +21,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "tcg-op.h"
+#include "tcg-op-gvec.h"
#include "qemu/log.h"
#include "arm_ldst.h"
#include "translate.h"
@@ -83,6 +84,10 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
+/* Note that the gvec expanders operate on offsets + sizes. */
+typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t);
+
/* initialize TCG globals. */
void a64_translate_init(void)
{
@@ -535,6 +540,21 @@ static inline int vec_reg_offset(DisasContext *s, int regno,
return offs;
}
+/* Return the offset info CPUARMState of the "whole" vector register Qn. */
+static inline int vec_full_reg_offset(DisasContext *s, int regno)
+{
+ assert_fp_access_checked(s);
+ return offsetof(CPUARMState, vfp.regs[regno * 2]);
+}
+
+/* Return the byte size of the "whole" vector register, VL / 8. */
+static inline int vec_full_reg_size(DisasContext *s)
+{
+ /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
+ In the meantime this is just the AdvSIMD length of 128. */
+ return 128 / 8;
+}
+
/* Return the offset into CPUARMState of a slice (from
* the least significant end) of FP register Qn (ie
* Dn, Sn, Hn or Bn).
@@ -9048,85 +9068,125 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
}
}
+static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ tcg_gen_xor_i64(rn, rn, rm);
+ tcg_gen_and_i64(rn, rn, rd);
+ tcg_gen_xor_i64(rd, rm, rn);
+}
+
+static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ tcg_gen_xor_i64(rn, rn, rd);
+ tcg_gen_and_i64(rn, rn, rm);
+ tcg_gen_xor_i64(rd, rd, rn);
+}
+
+static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
+{
+ tcg_gen_xor_i64(rn, rn, rd);
+ tcg_gen_andc_i64(rn, rn, rm);
+ tcg_gen_xor_i64(rd, rd, rn);
+}
+
+static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
+{
+ tcg_gen_xor_vec(vece, rn, rn, rm);
+ tcg_gen_and_vec(vece, rn, rn, rd);
+ tcg_gen_xor_vec(vece, rd, rm, rn);
+}
+
+static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
+{
+ tcg_gen_xor_vec(vece, rn, rn, rd);
+ tcg_gen_and_vec(vece, rn, rn, rm);
+ tcg_gen_xor_vec(vece, rd, rd, rn);
+}
+
+static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
+{
+ tcg_gen_xor_vec(vece, rn, rn, rd);
+ tcg_gen_andc_vec(vece, rn, rn, rm);
+ tcg_gen_xor_vec(vece, rd, rd, rn);
+}
+
/* Logic op (opcode == 3) subgroup of C3.6.16. */
static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
{
+ static const GVecGen3 bsl_op = {
+ .fni8 = gen_bsl_i64,
+ .fniv = gen_bsl_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true
+ };
+ static const GVecGen3 bit_op = {
+ .fni8 = gen_bit_i64,
+ .fniv = gen_bit_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true
+ };
+ static const GVecGen3 bif_op = {
+ .fni8 = gen_bif_i64,
+ .fniv = gen_bif_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true
+ };
+
int rd = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int rm = extract32(insn, 16, 5);
int size = extract32(insn, 22, 2);
bool is_u = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
- TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
- int pass;
+ GVecGen3Fn *gvec_fn;
+ const GVecGen3 *gvec_op;
if (!fp_access_check(s)) {
return;
}
- tcg_op1 = tcg_temp_new_i64();
- tcg_op2 = tcg_temp_new_i64();
- tcg_res[0] = tcg_temp_new_i64();
- tcg_res[1] = tcg_temp_new_i64();
-
- for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
- read_vec_element(s, tcg_op1, rn, pass, MO_64);
- read_vec_element(s, tcg_op2, rm, pass, MO_64);
-
- if (!is_u) {
- switch (size) {
- case 0: /* AND */
- tcg_gen_and_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 1: /* BIC */
- tcg_gen_andc_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 2: /* ORR */
- tcg_gen_or_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 3: /* ORN */
- tcg_gen_orc_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- }
- } else {
- if (size != 0) {
- /* B* ops need res loaded to operate on */
- read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
- }
-
- switch (size) {
- case 0: /* EOR */
- tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);
- break;
- case 1: /* BSL bitwise select */
- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_op2);
- tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_res[pass]);
- tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op1);
- break;
- case 2: /* BIT, bitwise insert if true */
- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
- tcg_gen_and_i64(tcg_op1, tcg_op1, tcg_op2);
- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
- break;
- case 3: /* BIF, bitwise insert if false */
- tcg_gen_xor_i64(tcg_op1, tcg_op1, tcg_res[pass]);
- tcg_gen_andc_i64(tcg_op1, tcg_op1, tcg_op2);
- tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
- break;
- }
- }
- }
+ switch (size + 4 * is_u) {
+ case 0: /* AND */
+ gvec_fn = tcg_gen_gvec_and;
+ goto do_fn;
+ case 1: /* BIC */
+ gvec_fn = tcg_gen_gvec_andc;
+ goto do_fn;
+ case 2: /* ORR */
+ gvec_fn = tcg_gen_gvec_or;
+ goto do_fn;
+ case 3: /* ORN */
+ gvec_fn = tcg_gen_gvec_orc;
+ goto do_fn;
+ case 4: /* EOR */
+ gvec_fn = tcg_gen_gvec_xor;
+ goto do_fn;
+ do_fn:
+ gvec_fn(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+
+ case 5: /* BSL bitwise select */
+ gvec_op = &bsl_op;
+ goto do_op;
+ case 6: /* BIT, bitwise insert if true */
+ gvec_op = &bit_op;
+ goto do_op;
+ case 7: /* BIF, bitwise insert if false */
+ gvec_op = &bif_op;
+ goto do_op;
+ do_op:
+ tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s), gvec_op);
+ return;
- write_vec_element(s, tcg_res[0], rd, 0, MO_64);
- if (!is_q) {
- tcg_gen_movi_i64(tcg_res[1], 0);
+ default:
+ g_assert_not_reached();
}
- write_vec_element(s, tcg_res[1], rd, 1, MO_64);
-
- tcg_temp_free_i64(tcg_op1);
- tcg_temp_free_i64(tcg_op2);
- tcg_temp_free_i64(tcg_res[0]);
- tcg_temp_free_i64(tcg_res[1]);
}
/* Helper functions for 32 bit comparisons */
@@ -9387,6 +9447,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
int pass;
+ GVecGen3Fn *gvec_op;
switch (opcode) {
case 0x13: /* MUL, PMUL */
@@ -9426,6 +9487,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
return;
}
+ switch (opcode) {
+ case 0x10: /* ADD, SUB */
+ gvec_op = u ? tcg_gen_gvec_sub : tcg_gen_gvec_add;
+ gvec_op(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
+
if (size == 3) {
assert(is_q);
for (pass = 0; pass < 2; pass++) {
@@ -9598,16 +9669,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][u];
break;
}
- case 0x10: /* ADD, SUB */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
- { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
- { tcg_gen_add_i32, tcg_gen_sub_i32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x11: /* CMTST, CMEQ */
{
static NeonGenTwoOpFn * const fns[3][2] = {
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 10/26] target/arm: Use vector infrastructure for aa64 mov/not/neg
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (8 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 09/26] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 11/26] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
` (20 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 43 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 572af456d1..bc14c28e71 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -85,6 +85,7 @@ typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
/* Note that the gvec expanders operate on offsets + sizes. */
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
@@ -4579,14 +4580,19 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
TCGv_i64 tcg_op;
TCGv_i64 tcg_res;
+ switch (opcode) {
+ case 0x0: /* FMOV */
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ 8, vec_full_reg_size(s));
+ return;
+ }
+
fpst = get_fpstatus_ptr();
tcg_op = read_fp_dreg(s, rn);
tcg_res = tcg_temp_new_i64();
switch (opcode) {
- case 0x0: /* FMOV */
- tcg_gen_mov_i64(tcg_res, tcg_op);
- break;
case 0x1: /* FABS */
gen_helper_vfp_absd(tcg_res, tcg_op);
break;
@@ -9153,6 +9159,12 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
gvec_fn = tcg_gen_gvec_andc;
goto do_fn;
case 2: /* ORR */
+ if (rn == rm) { /* MOV */
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
gvec_fn = tcg_gen_gvec_or;
goto do_fn;
case 3: /* ORN */
@@ -10032,6 +10044,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
+ GVecGen2Fn *gvec_fn;
switch (opcode) {
case 0x0: /* REV64, REV32 */
@@ -10040,8 +10053,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
case 0x5: /* CNT, NOT, RBIT */
if (u && size == 0) {
- /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
- size = 3;
+ /* NOT */
break;
} else if (u && size == 1) {
/* RBIT */
@@ -10293,6 +10305,27 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
tcg_rmode = NULL;
}
+ switch (opcode) {
+ case 0x5:
+ if (u && size == 0) { /* NOT */
+ gvec_fn = tcg_gen_gvec_not;
+ goto do_fn;
+ }
+ break;
+ case 0xb:
+ if (u) { /* NEG */
+ gvec_fn = tcg_gen_gvec_neg;
+ goto do_fn;
+ }
+ break;
+
+ do_fn:
+ gvec_fn(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
+
if (size == 3) {
/* All 64-bit element operations can be shared with scalar 2misc */
int pass;
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 11/26] target/arm: Use vector infrastructure for aa64 dup/movi
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (9 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 10/26] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 12/26] tcg/i386: Add vector operations Richard Henderson
` (19 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 83 +++++++++++++++++++---------------------------
1 file changed, 34 insertions(+), 49 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index bc14c28e71..55a4902fc2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5846,38 +5846,24 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
*
* size: encoded in imm5 (see ARM ARM LowestSetBit())
*/
+
static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
int imm5)
{
int size = ctz32(imm5);
- int esize = 8 << size;
- int elements = (is_q ? 128 : 64) / esize;
- int index, i;
- TCGv_i64 tmp;
+ int index = imm5 >> (size + 1);
if (size > 3 || (size == 3 && !is_q)) {
unallocated_encoding(s);
return;
}
-
if (!fp_access_check(s)) {
return;
}
- index = imm5 >> (size + 1);
-
- tmp = tcg_temp_new_i64();
- read_vec_element(s, tmp, rn, index, size);
-
- for (i = 0; i < elements; i++) {
- write_vec_element(s, tmp, rd, i, size);
- }
-
- if (!is_q) {
- clear_vec_high(s, rd);
- }
-
- tcg_temp_free_i64(tmp);
+ tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd),
+ vec_reg_offset(s, rn, index, size),
+ is_q ? 16 : 8, vec_full_reg_size(s));
}
/* DUP (element, scalar)
@@ -5926,9 +5912,7 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
int imm5)
{
int size = ctz32(imm5);
- int esize = 8 << size;
- int elements = (is_q ? 128 : 64)/esize;
- int i = 0;
+ uint32_t dofs, oprsz, maxsz;
if (size > 3 || ((size == 3) && !is_q)) {
unallocated_encoding(s);
@@ -5939,12 +5923,11 @@ static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
return;
}
- for (i = 0; i < elements; i++) {
- write_vec_element(s, cpu_reg(s, rn), rd, i, size);
- }
- if (!is_q) {
- clear_vec_high(s, rd);
- }
+ dofs = vec_full_reg_offset(s, rd);
+ oprsz = is_q ? 16 : 8;
+ maxsz = vec_full_reg_size(s);
+
+ tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn));
}
/* INS (Element)
@@ -6135,7 +6118,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
bool is_neg = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
uint64_t imm = 0;
- TCGv_i64 tcg_rd, tcg_imm;
int i;
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
@@ -6217,32 +6199,35 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
imm = ~imm;
}
- tcg_imm = tcg_const_i64(imm);
- tcg_rd = new_tmp_a64(s);
+ if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
+ /* MOVI or MVNI, with MVNI negation handled above. */
+ tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
+ vec_full_reg_size(s), imm);
+ } else {
+ TCGv_i64 tcg_imm = tcg_const_i64(imm);
+ TCGv_i64 tcg_rd = new_tmp_a64(s);
- for (i = 0; i < 2; i++) {
- int foffs = i ? fp_reg_hi_offset(s, rd) : fp_reg_offset(s, rd, MO_64);
+ for (i = 0; i < 2; i++) {
+ int foffs = vec_reg_offset(s, rd, i, MO_64);
- if (i == 1 && !is_q) {
- /* non-quad ops clear high half of vector */
- tcg_gen_movi_i64(tcg_rd, 0);
- } else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) {
- tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
- if (is_neg) {
- /* AND (BIC) */
- tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
+ if (i == 1 && !is_q) {
+ /* non-quad ops clear high half of vector */
+ tcg_gen_movi_i64(tcg_rd, 0);
} else {
- /* ORR */
- tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
+ tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
+ if (is_neg) {
+ /* AND (BIC) */
+ tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
+ } else {
+ /* ORR */
+ tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
+ }
}
- } else {
- /* MOVI */
- tcg_gen_mov_i64(tcg_rd, tcg_imm);
+ tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
}
- tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
- }
- tcg_temp_free_i64(tcg_imm);
+ tcg_temp_free_i64(tcg_imm);
+ }
}
/* AdvSIMD scalar copy
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 12/26] tcg/i386: Add vector operations
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (10 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 11/26] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 13/26] tcg: Add tcg_expand_vec_op and tcg-target.opc.h Richard Henderson
` (18 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
The x86 vector instruction set is extremely irregular. With newer
editions, Intel has filled in some of the blanks. However, we don't
get many 64-bit operations until SSE4.2, introduced in 2009.
The subsequent edition was for AVX1, introduced in 2011, which added
three-operand addressing, and adjusts how all instructions should be
encoded.
Given the relatively narrow 2 year window between possible to support
and desirable to support, and to vastly simplify code maintainence,
I am only planning to support AVX1 and later cpus.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 36 ++-
tcg/i386/tcg-target.inc.c | 561 ++++++++++++++++++++++++++++++++++++++++++----
2 files changed, 546 insertions(+), 51 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b89dababf4..f9d3fc4a93 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -30,10 +30,10 @@
#ifdef __x86_64__
# define TCG_TARGET_REG_BITS 64
-# define TCG_TARGET_NB_REGS 16
+# define TCG_TARGET_NB_REGS 32
#else
# define TCG_TARGET_REG_BITS 32
-# define TCG_TARGET_NB_REGS 8
+# define TCG_TARGET_NB_REGS 24
#endif
typedef enum {
@@ -56,6 +56,26 @@ typedef enum {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
+
+ TCG_REG_XMM0,
+ TCG_REG_XMM1,
+ TCG_REG_XMM2,
+ TCG_REG_XMM3,
+ TCG_REG_XMM4,
+ TCG_REG_XMM5,
+ TCG_REG_XMM6,
+ TCG_REG_XMM7,
+
+ /* 64-bit registers; likewise always define. */
+ TCG_REG_XMM8,
+ TCG_REG_XMM9,
+ TCG_REG_XMM10,
+ TCG_REG_XMM11,
+ TCG_REG_XMM12,
+ TCG_REG_XMM13,
+ TCG_REG_XMM14,
+ TCG_REG_XMM15,
+
TCG_REG_RAX = TCG_REG_EAX,
TCG_REG_RCX = TCG_REG_ECX,
TCG_REG_RDX = TCG_REG_EDX,
@@ -77,6 +97,8 @@ typedef enum {
extern bool have_bmi1;
extern bool have_popcnt;
+extern bool have_avx1;
+extern bool have_avx2;
/* optional instructions */
#define TCG_TARGET_HAS_div2_i32 1
@@ -146,6 +168,16 @@ extern bool have_popcnt;
#define TCG_TARGET_HAS_mulsh_i64 0
#endif
+/* We do not support older SSE systems, only beginning with AVX1. */
+#define TCG_TARGET_HAS_v64 have_avx1
+#define TCG_TARGET_HAS_v128 have_avx1
+#define TCG_TARGET_HAS_v256 have_avx2
+
+#define TCG_TARGET_HAS_andc_vec 1
+#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
((ofs) == 0 && (len) == 16))
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 63d27f10e7..e9a4d92598 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -28,10 +28,15 @@
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#if TCG_TARGET_REG_BITS == 64
"%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
- "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
#else
"%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
#endif
+ "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
+ "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
+#if TCG_TARGET_REG_BITS == 64
+ "%xmm8", "%xmm9", "%xmm10", "%xmm11",
+ "%xmm12", "%xmm13", "%xmm14", "%xmm15",
+#endif
};
#endif
@@ -61,6 +66,28 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_EDX,
TCG_REG_EAX,
#endif
+ TCG_REG_XMM0,
+ TCG_REG_XMM1,
+ TCG_REG_XMM2,
+ TCG_REG_XMM3,
+ TCG_REG_XMM4,
+ TCG_REG_XMM5,
+#ifndef _WIN64
+ /* The Win64 ABI has xmm6-xmm15 as caller-saves, and we do not save
+ any of them. Therefore only allow xmm0-xmm5 to be allocated. */
+ TCG_REG_XMM6,
+ TCG_REG_XMM7,
+#if TCG_TARGET_REG_BITS == 64
+ TCG_REG_XMM8,
+ TCG_REG_XMM9,
+ TCG_REG_XMM10,
+ TCG_REG_XMM11,
+ TCG_REG_XMM12,
+ TCG_REG_XMM13,
+ TCG_REG_XMM14,
+ TCG_REG_XMM15,
+#endif
+#endif
};
static const int tcg_target_call_iarg_regs[] = {
@@ -94,7 +121,7 @@ static const int tcg_target_call_oarg_regs[] = {
#define TCG_CT_CONST_I32 0x400
#define TCG_CT_CONST_WSZ 0x800
-/* Registers used with L constraint, which are the first argument
+/* Registers used with L constraint, which are the first argument
registers on x86_64, and two random call clobbered registers on
i386. */
#if TCG_TARGET_REG_BITS == 64
@@ -125,6 +152,8 @@ static bool have_cmov;
it there. Therefore we always define the variable. */
bool have_bmi1;
bool have_popcnt;
+bool have_avx1;
+bool have_avx2;
#ifdef CONFIG_CPUID_H
static bool have_movbe;
@@ -148,6 +177,8 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
if (value != (int32_t)value) {
tcg_abort();
}
+ /* FALLTHRU */
+ case R_386_32:
tcg_patch32(code_ptr, value);
break;
case R_386_PC8:
@@ -162,6 +193,14 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
}
}
+#if TCG_TARGET_REG_BITS == 64
+#define ALL_GENERAL_REGS 0x0000ffffu
+#define ALL_VECTOR_REGS 0xffff0000u
+#else
+#define ALL_GENERAL_REGS 0x000000ffu
+#define ALL_VECTOR_REGS 0x00ff0000u
+#endif
+
/* parse target specific constraints */
static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
@@ -192,21 +231,29 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
break;
case 'q':
+ /* A register that can be used as a byte operand. */
ct->ct |= TCG_CT_REG;
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
break;
case 'Q':
+ /* A register with an addressable second byte (e.g. %ah). */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xf;
break;
case 'r':
+ /* A general register. */
ct->ct |= TCG_CT_REG;
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
+ ct->u.regs |= ALL_GENERAL_REGS;
break;
case 'W':
/* With TZCNT/LZCNT, we can have operand-size as an input. */
ct->ct |= TCG_CT_CONST_WSZ;
break;
+ case 'x':
+ /* A vector register. */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= ALL_VECTOR_REGS;
+ break;
/* qemu_ld/st address constraint */
case 'L':
@@ -277,8 +324,9 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
# define P_REXB_RM 0
# define P_GS 0
#endif
-#define P_SIMDF3 0x10000 /* 0xf3 opcode prefix */
-#define P_SIMDF2 0x20000 /* 0xf2 opcode prefix */
+#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */
+#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */
+#define P_VEXL 0x80000 /* Set VEX.L = 1 */
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
@@ -310,11 +358,38 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_MOVL_Iv (0xb8)
#define OPC_MOVBE_GyMy (0xf0 | P_EXT38)
#define OPC_MOVBE_MyGy (0xf1 | P_EXT38)
+#define OPC_MOVD_VyEy (0x6e | P_EXT | P_DATA16)
+#define OPC_MOVD_EyVy (0x7e | P_EXT | P_DATA16)
+#define OPC_MOVDDUP (0x12 | P_EXT | P_SIMDF2)
+#define OPC_MOVDQA_VxWx (0x6f | P_EXT | P_DATA16)
+#define OPC_MOVDQA_WxVx (0x7f | P_EXT | P_DATA16)
+#define OPC_MOVDQU_VxWx (0x6f | P_EXT | P_SIMDF3)
+#define OPC_MOVDQU_WxVx (0x7f | P_EXT | P_SIMDF3)
+#define OPC_MOVQ_VqWq (0x7e | P_EXT | P_SIMDF3)
+#define OPC_MOVQ_WqVq (0xd6 | P_EXT | P_DATA16)
#define OPC_MOVSBL (0xbe | P_EXT)
#define OPC_MOVSWL (0xbf | P_EXT)
#define OPC_MOVSLQ (0x63 | P_REXW)
#define OPC_MOVZBL (0xb6 | P_EXT)
#define OPC_MOVZWL (0xb7 | P_EXT)
+#define OPC_PADDB (0xfc | P_EXT | P_DATA16)
+#define OPC_PADDW (0xfd | P_EXT | P_DATA16)
+#define OPC_PADDD (0xfe | P_EXT | P_DATA16)
+#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16)
+#define OPC_PAND (0xdb | P_EXT | P_DATA16)
+#define OPC_PANDN (0xdf | P_EXT | P_DATA16)
+#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16)
+#define OPC_POR (0xeb | P_EXT | P_DATA16)
+#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16)
+#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16)
+#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
+#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
+#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16)
+#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16)
+#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16)
+#define OPC_PXOR (0xef | P_EXT | P_DATA16)
#define OPC_POP_r32 (0x58)
#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3)
#define OPC_PUSH_r32 (0x50)
@@ -330,6 +405,11 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
#define OPC_TESTL (0x85)
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
+#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
+#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
+#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
#define OPC_GRP3_Ev (0xf7)
@@ -479,11 +559,20 @@ static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm)
tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
-static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
+static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
+ int rm, int index)
{
int tmp;
- if ((opc & (P_REXW | P_EXT | P_EXT38)) || (rm & 8)) {
+ /* Use the two byte form if possible, which cannot encode
+ VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
+ if ((opc & (P_EXT | P_EXT38 | P_REXW)) == P_EXT
+ && ((rm | index) & 8) == 0) {
+ /* Two byte VEX prefix. */
+ tcg_out8(s, 0xc5);
+
+ tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
+ } else {
/* Three byte VEX prefix. */
tcg_out8(s, 0xc4);
@@ -493,20 +582,17 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
} else if (opc & P_EXT) {
tmp = 1;
} else {
- tcg_abort();
+ g_assert_not_reached();
}
- tmp |= 0x40; /* VEX.X */
- tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */
- tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
+ tmp |= (r & 8 ? 0 : 0x80); /* VEX.R */
+ tmp |= (index & 8 ? 0 : 0x40); /* VEX.X */
+ tmp |= (rm & 8 ? 0 : 0x20); /* VEX.B */
tcg_out8(s, tmp);
- tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
- } else {
- /* Two byte VEX prefix. */
- tcg_out8(s, 0xc5);
-
- tmp = (r & 8 ? 0 : 0x80); /* VEX.R */
+ tmp = (opc & P_REXW ? 0x80 : 0); /* VEX.W */
}
+
+ tmp |= (opc & P_VEXL ? 0x04 : 0); /* VEX.L */
/* VEX.pp */
if (opc & P_DATA16) {
tmp |= 1; /* 0x66 */
@@ -518,6 +604,11 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
tmp |= (~v & 15) << 3; /* VEX.vvvv */
tcg_out8(s, tmp);
tcg_out8(s, opc);
+}
+
+static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
+{
+ tcg_out_vex_opc(s, opc, r, v, rm, 0);
tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
@@ -526,8 +617,8 @@ static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
mode for absolute addresses, ~RM is the size of the immediate operand
that will follow the instruction. */
-static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
- int index, int shift, intptr_t offset)
+static void tcg_out_sib_offset(TCGContext *s, int r, int rm, int index,
+ int shift, intptr_t offset)
{
int mod, len;
@@ -538,7 +629,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
intptr_t pc = (intptr_t)s->code_ptr + 5 + ~rm;
intptr_t disp = offset - pc;
if (disp == (int32_t)disp) {
- tcg_out_opc(s, opc, r, 0, 0);
tcg_out8(s, (LOWREGMASK(r) << 3) | 5);
tcg_out32(s, disp);
return;
@@ -548,7 +638,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
use of the MODRM+SIB encoding and is therefore larger than
rip-relative addressing. */
if (offset == (int32_t)offset) {
- tcg_out_opc(s, opc, r, 0, 0);
tcg_out8(s, (LOWREGMASK(r) << 3) | 4);
tcg_out8(s, (4 << 3) | 5);
tcg_out32(s, offset);
@@ -556,10 +645,9 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
}
/* ??? The memory isn't directly addressable. */
- tcg_abort();
+ g_assert_not_reached();
} else {
/* Absolute address. */
- tcg_out_opc(s, opc, r, 0, 0);
tcg_out8(s, (r << 3) | 5);
tcg_out32(s, offset);
return;
@@ -582,7 +670,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
that would be used for %esp is the escape to the two byte form. */
if (index < 0 && LOWREGMASK(rm) != TCG_REG_ESP) {
/* Single byte MODRM format. */
- tcg_out_opc(s, opc, r, rm, 0);
tcg_out8(s, mod | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
} else {
/* Two byte MODRM+SIB format. */
@@ -596,7 +683,6 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
tcg_debug_assert(index != TCG_REG_ESP);
}
- tcg_out_opc(s, opc, r, rm, index);
tcg_out8(s, mod | (LOWREGMASK(r) << 3) | 4);
tcg_out8(s, (shift << 6) | (LOWREGMASK(index) << 3) | LOWREGMASK(rm));
}
@@ -608,6 +694,21 @@ static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
}
}
+static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm,
+ int index, int shift, intptr_t offset)
+{
+ tcg_out_opc(s, opc, r, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
+ tcg_out_sib_offset(s, r, rm, index, shift, offset);
+}
+
+static void tcg_out_vex_modrm_sib_offset(TCGContext *s, int opc, int r, int v,
+ int rm, int index, int shift,
+ intptr_t offset)
+{
+ tcg_out_vex_opc(s, opc, r, v, rm < 0 ? 0 : rm, index < 0 ? 0 : index);
+ tcg_out_sib_offset(s, r, rm, index, shift, offset);
+}
+
/* A simplification of the above with no index or shift. */
static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
int rm, intptr_t offset)
@@ -615,6 +716,30 @@ static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r,
tcg_out_modrm_sib_offset(s, opc, r, rm, -1, 0, offset);
}
+static inline void tcg_out_vex_modrm_offset(TCGContext *s, int opc, int r,
+ int v, int rm, intptr_t offset)
+{
+ tcg_out_vex_modrm_sib_offset(s, opc, r, v, rm, -1, 0, offset);
+}
+
+/* Output an opcode with an expected reference to the constant pool. */
+static inline void tcg_out_modrm_pool(TCGContext *s, int opc, int r)
+{
+ tcg_out_opc(s, opc, r, 0, 0);
+ /* Absolute for 32-bit, pc-relative for 64-bit. */
+ tcg_out8(s, LOWREGMASK(r) << 3 | 5);
+ tcg_out32(s, 0);
+}
+
+/* Output an opcode with an expected reference to the constant pool. */
+static inline void tcg_out_vex_modrm_pool(TCGContext *s, int opc, int r)
+{
+ tcg_out_vex_opc(s, opc, r, 0, 0, 0);
+ /* Absolute for 32-bit, pc-relative for 64-bit. */
+ tcg_out8(s, LOWREGMASK(r) << 3 | 5);
+ tcg_out32(s, 0);
+}
+
/* Generate dest op= src. Uses the same ARITH_* codes as tgen_arithi. */
static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
{
@@ -625,12 +750,114 @@ static inline void tgen_arithr(TCGContext *s, int subop, int dest, int src)
tcg_out_modrm(s, OPC_ARITH_GvEv + (subop << 3) + ext, dest, src);
}
-static inline void tcg_out_mov(TCGContext *s, TCGType type,
- TCGReg ret, TCGReg arg)
+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ int rexw = 0;
+
+ if (arg == ret) {
+ return;
+ }
+ switch (type) {
+ case TCG_TYPE_I64:
+ rexw = P_REXW;
+ /* fallthru */
+ case TCG_TYPE_I32:
+ if (ret < 16) {
+ if (arg < 16) {
+ tcg_out_modrm(s, OPC_MOVL_GvEv + rexw, ret, arg);
+ } else {
+ tcg_out_vex_modrm(s, OPC_MOVD_EyVy + rexw, ret, 0, arg);
+ }
+ } else {
+ if (arg < 16) {
+ tcg_out_vex_modrm(s, OPC_MOVD_VyEy + rexw, ret, 0, arg);
+ } else {
+ tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
+ }
+ }
+ break;
+
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVQ_VqWq, ret, 0, arg);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx, ret, 0, arg);
+ break;
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16 && arg >= 16);
+ tcg_out_vex_modrm(s, OPC_MOVDQA_VxWx | P_VEXL, ret, 0, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg r, TCGReg a)
{
- if (arg != ret) {
- int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
- tcg_out_modrm(s, opc, ret, arg);
+ if (have_avx2) {
+ static const int dup_insn[4] = {
+ OPC_VPBROADCASTB, OPC_VPBROADCASTW,
+ OPC_VPBROADCASTD, OPC_VPBROADCASTQ,
+ };
+ int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+ tcg_out_vex_modrm(s, dup_insn[vece] + vex_l, r, 0, a);
+ } else {
+ switch (vece) {
+ case MO_8:
+ /* ??? With zero in a register, use PSHUFB. */
+ tcg_out_vex_modrm(s, OPC_PUNPCKLBW, r, 0, a);
+ a = r;
+ /* FALLTHRU */
+ case MO_16:
+ tcg_out_vex_modrm(s, OPC_PUNPCKLWD, r, 0, a);
+ a = r;
+ /* FALLTHRU */
+ case MO_32:
+ tcg_out_vex_modrm(s, OPC_PSHUFD, r, 0, a);
+ /* imm8 operand: all output lanes selected from input lane 0. */
+ tcg_out8(s, 0);
+ break;
+ case MO_64:
+ tcg_out_vex_modrm(s, OPC_PUNPCKLQDQ, r, 0, a);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+}
+
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
+
+ if (arg == 0) {
+ tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret);
+ return;
+ }
+ if (arg == -1) {
+ tcg_out_vex_modrm(s, OPC_PCMPEQB + vex_l, ret, ret, ret);
+ return;
+ }
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ if (have_avx2) {
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTQ + vex_l, ret);
+ } else {
+ tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret);
+ }
+ new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
+ } else if (have_avx2) {
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
+ new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
+ } else {
+ tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy, ret);
+ new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
+ tcg_out_dup_vec(s, type, MO_32, ret, ret);
}
}
@@ -639,6 +866,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
{
tcg_target_long diff;
+ switch (type) {
+ case TCG_TYPE_I32:
+#if TCG_TARGET_REG_BITS == 64
+ case TCG_TYPE_I64:
+#endif
+ if (ret < 16) {
+ break;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_dupi_vec(s, type, ret, arg);
+ return;
+ default:
+ g_assert_not_reached();
+ }
+
if (arg == 0) {
tgen_arithr(s, ARITH_XOR, ret, ret);
return;
@@ -667,6 +913,59 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out64(s, arg);
}
+static void tcg_out_movi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, const TCGArg *a)
+{
+ int n = (64 / TCG_TARGET_REG_BITS) << (type - TCG_TYPE_V64);
+ int opc, ofs, rel;
+
+ tcg_debug_assert(ret >= 16);
+ tcg_debug_assert(type >= TCG_TYPE_V64);
+
+ /* We assume that INDEX_op_dupi could not be used and therefore
+ we must use a constant pool entry. */
+
+ switch (type) {
+ case TCG_TYPE_V64:
+ opc = OPC_MOVQ_VqWq;
+ break;
+ case TCG_TYPE_V128:
+ opc = OPC_MOVDQU_VxWx;
+ break;
+ case TCG_TYPE_V256:
+ opc = OPC_MOVDQU_VxWx | P_VEXL;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_vex_modrm_pool(s, opc, ret);
+
+ if (TCG_TARGET_REG_BITS == 64) {
+ rel = R_386_PC32, ofs = -4;
+ } else {
+ rel = R_386_32, ofs = 0;
+ }
+ switch (n) {
+ case 1:
+ new_pool_label(s, a[0], rel, s->code_ptr - 4, rel);
+ break;
+ case 2:
+ new_pool_l2(s, rel, s->code_ptr - 4, ofs, a[0], a[1]);
+ break;
+ case 4:
+ new_pool_l4(s, rel, s->code_ptr - 4, ofs, a[0], a[1], a[2], a[3]);
+ break;
+#if TCG_TARGET_REG_BITS == 32
+ case 8:
+ new_pool_l8(s, rel, s->code_ptr - 4, ofs,
+ a[0], a[1], a[2], a[3], a[4], a[5], a[6], a[7]);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+}
+
static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
{
if (val == (int8_t)val) {
@@ -702,18 +1001,74 @@ static inline void tcg_out_pop(TCGContext *s, int reg)
tcg_out_opc(s, OPC_POP_r32 + LOWREGMASK(reg), 0, reg, 0);
}
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg arg1, intptr_t arg2)
{
- int opc = OPC_MOVL_GvEv + (type == TCG_TYPE_I64 ? P_REXW : 0);
- tcg_out_modrm_offset(s, opc, ret, arg1, arg2);
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv, ret, arg1, arg2);
+ } else {
+ tcg_out_vex_modrm_offset(s, OPC_MOVD_VyEy, ret, 0, arg1, arg2);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (ret < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_GvEv | P_REXW, ret, arg1, arg2);
+ break;
+ }
+ /* FALLTHRU */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVQ_VqWq, ret, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx, ret, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_VxWx | P_VEXL,
+ ret, 0, arg1, arg2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg arg1, intptr_t arg2)
{
- int opc = OPC_MOVL_EvGv + (type == TCG_TYPE_I64 ? P_REXW : 0);
- tcg_out_modrm_offset(s, opc, arg, arg1, arg2);
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (arg < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv, arg, arg1, arg2);
+ } else {
+ tcg_out_vex_modrm_offset(s, OPC_MOVD_EyVy, arg, 0, arg1, arg2);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (arg < 16) {
+ tcg_out_modrm_offset(s, OPC_MOVL_EvGv | P_REXW, arg, arg1, arg2);
+ break;
+ }
+ /* FALLTHRU */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVQ_WqVq, arg, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx, arg, 0, arg1, arg2);
+ break;
+ case TCG_TYPE_V256:
+ tcg_debug_assert(arg >= 16);
+ tcg_out_vex_modrm_offset(s, OPC_MOVDQU_WxVx | P_VEXL,
+ arg, 0, arg1, arg2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
@@ -725,6 +1080,8 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
return false;
}
rexw = P_REXW;
+ } else if (type != TCG_TYPE_I32) {
+ return false;
}
tcg_out_modrm_offset(s, OPC_MOVL_EvIz | rexw, 0, base, ofs);
tcg_out32(s, val);
@@ -2259,8 +2616,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
+ case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
+ case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -2269,6 +2628,73 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
#undef OP_32_64
}
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static int const add_insn[4] = {
+ OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
+ };
+ static int const sub_insn[4] = {
+ OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
+ };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ int insn;
+ TCGArg a0, a1, a2;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_add_vec:
+ insn = add_insn[vece];
+ goto gen_simd;
+ case INDEX_op_sub_vec:
+ insn = sub_insn[vece];
+ goto gen_simd;
+ case INDEX_op_and_vec:
+ insn = OPC_PAND;
+ goto gen_simd;
+ case INDEX_op_or_vec:
+ insn = OPC_POR;
+ goto gen_simd;
+ case INDEX_op_xor_vec:
+ insn = OPC_PXOR;
+ gen_simd:
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ break;
+
+ case INDEX_op_andc_vec:
+ insn = OPC_PANDN;
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a2, a1);
+ break;
+
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_movi_vec:
+ tcg_out_movi_vec(s, type, a0, args + 1);
+ break;
+ case INDEX_op_dup_vec:
+ tcg_out_dup_vec(s, type, vece, a0, a1);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
@@ -2292,6 +2718,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
= { .args_ct_str = { "r", "r", "L", "L" } };
static const TCGTargetOpDef L_L_L_L
= { .args_ct_str = { "L", "L", "L", "L" } };
+ static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
+ static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
+ static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
switch (op) {
case INDEX_op_goto_ptr:
@@ -2493,6 +2922,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return &s2;
}
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ return &x_r;
+
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ return &x_x_x;
+ case INDEX_op_dup_vec:
+ return &x_x;
+
default:
break;
}
@@ -2577,6 +3020,9 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_addi(s, TCG_REG_CALL_STACK, stack_addend);
+ if (have_avx2) {
+ tcg_out_vex_opc(s, OPC_VZEROUPPER, 0, 0, 0, 0);
+ }
for (i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) {
tcg_out_pop(s, tcg_target_callee_save_regs[i]);
}
@@ -2598,9 +3044,16 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
static void tcg_target_init(TCGContext *s)
{
#ifdef CONFIG_CPUID_H
- unsigned a, b, c, d;
+ unsigned a, b, c, d, b7 = 0;
int max = __get_cpuid_max(0, 0);
+ if (max >= 7) {
+ /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
+ __cpuid_count(7, 0, a, b7, c, d);
+ have_bmi1 = (b7 & bit_BMI) != 0;
+ have_bmi2 = (b7 & bit_BMI2) != 0;
+ }
+
if (max >= 1) {
__cpuid(1, a, b, c, d);
#ifndef have_cmov
@@ -2609,17 +3062,22 @@ static void tcg_target_init(TCGContext *s)
available, we'll use a small forward branch. */
have_cmov = (d & bit_CMOV) != 0;
#endif
+
/* MOVBE is only available on Intel Atom and Haswell CPUs, so we
need to probe for it. */
have_movbe = (c & bit_MOVBE) != 0;
have_popcnt = (c & bit_POPCNT) != 0;
- }
- if (max >= 7) {
- /* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
- __cpuid_count(7, 0, a, b, c, d);
- have_bmi1 = (b & bit_BMI) != 0;
- have_bmi2 = (b & bit_BMI2) != 0;
+ /* There are a number of things we must check before we can be
+ sure of not hitting invalid opcode. */
+ if (c & bit_OSXSAVE) {
+ unsigned xcrl, xcrh;
+ asm ("xgetbv" : "=a" (xcrl), "=d" (xcrh) : "c" (0));
+ if ((xcrl & 6) == 6) {
+ have_avx1 = (c & bit_AVX) != 0;
+ have_avx2 = (b7 & bit_AVX2) != 0;
+ }
+ }
}
max = __get_cpuid_max(0x8000000, 0);
@@ -2630,11 +3088,16 @@ static void tcg_target_init(TCGContext *s)
}
#endif /* CONFIG_CPUID_H */
+ tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
if (TCG_TARGET_REG_BITS == 64) {
- tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
- } else {
- tcg_target_available_regs[TCG_TYPE_I32] = 0xff;
+ tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
+ }
+ if (have_avx1) {
+ tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
+ tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
+ }
+ if (have_avx2) {
+ tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS;
}
tcg_target_call_clobber_regs = 0;
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 13/26] tcg: Add tcg_expand_vec_op and tcg-target.opc.h
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (11 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 12/26] tcg/i386: Add vector operations Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 14/26] tcg: Add generic vector ops for interleave Richard Henderson
` (17 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
These will be useful in the next few patches adding shifts,
permutes, and multiplication.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.opc.h | 3 +++
tcg/tcg-opc.h | 6 ++++++
tcg/tcg.h | 11 +++++++++++
tcg/i386/tcg-target.inc.c | 21 +++++++++++++++++++++
tcg/tcg.c | 6 +++---
5 files changed, 44 insertions(+), 3 deletions(-)
create mode 100644 tcg/i386/tcg-target.opc.h
diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h
new file mode 100644
index 0000000000..4816a6c3d4
--- /dev/null
+++ b/tcg/i386/tcg-target.opc.h
@@ -0,0 +1,3 @@
+/* Target-specific opcodes for host vector expansion. These will be
+ emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ consider these to be UNSPEC with names. */
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 4e62eda14b..b4e16cfbc3 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -229,6 +229,12 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
+
+#if TCG_TARGET_MAYBE_vec
+#include "tcg-target.opc.h"
+#endif
+
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 49d4c5fe05..2cba208b4c 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1207,6 +1207,17 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
void tcg_register_jit(void *buf, size_t buf_size);
+#if TCG_TARGET_MAYBE_vec
+/* Return zero if the tuple (opc, type, vece) is unsupportable;
+ return > 0 if it is directly supportable;
+ return < 0 if we must call tcg_expand_vec_op. */
+int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
+
+/* Expand the tuple (opc, type, vece) on the given arguments. */
+void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
+#endif
+
+
/*
* Memory helpers that will be used by TCG generated code.
*/
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index e9a4d92598..062cf16607 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2942,6 +2942,27 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return NULL;
}
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ return true;
+
+ default:
+ return false;
+ }
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+}
+
static const int tcg_target_callee_save_regs[] = {
#if TCG_TARGET_REG_BITS == 64
TCG_REG_RBP,
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 16b8faf66f..e725b1818f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1404,10 +1404,10 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
- case NB_OPS:
- break;
+ default:
+ tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
+ return true;
}
- g_assert_not_reached();
}
/* Note: we convert the 64 bit args to 32 bit and do some alignment
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 14/26] tcg: Add generic vector ops for interleave
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (12 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 13/26] tcg: Add tcg_expand_vec_op and tcg-target.opc.h Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 15/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn Richard Henderson
` (16 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Includes zip, unzip, and transform.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 15 ++
tcg/i386/tcg-target.h | 3 +
tcg/tcg-op-gvec.h | 17 +++
tcg/tcg-op.h | 6 +
tcg/tcg-opc.h | 7 +
tcg/tcg.h | 3 +
accel/tcg/tcg-runtime-gvec.c | 78 ++++++++++
tcg/tcg-op-gvec.c | 337 ++++++++++++++++++++++++++++++++++++++++++-
tcg/tcg-op-vec.c | 55 +++++++
tcg/tcg.c | 9 ++
tcg/README | 40 +++++
11 files changed, 562 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 76ee41ce58..c6de749134 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -163,3 +163,18 @@ DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_zip8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_zip16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_zip32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_zip64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_uzp8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_uzp16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_uzp32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_uzp64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_trn8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_trn16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_trn32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_trn64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index f9d3fc4a93..ff0ad7dcdb 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -177,6 +177,9 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_zip_vec 0
+#define TCG_TARGET_HAS_uzp_vec 0
+#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 95739946ff..64270a3c74 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -66,6 +66,8 @@ typedef struct {
gen_helper_gvec_2 *fno;
/* The opcode, if any, to which this corresponds. */
TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ uint32_t data;
/* The vector element size, if applicable. */
uint8_t vece;
/* Prefer i64 to v64. */
@@ -83,6 +85,8 @@ typedef struct {
gen_helper_gvec_3 *fno;
/* The opcode, if any, to which this corresponds. */
TCGOpcode opc;
+ /* The data argument to the out-of-line helper. */
+ uint32_t data;
/* The vector element size, if applicable. */
uint8_t vece;
/* Prefer i64 to v64. */
@@ -133,6 +137,19 @@ void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
+void tcg_gen_gvec_zipl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_ziph(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_uzpe(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_uzpo(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
+
/*
* 64-bit vector operations. Use these when the register has been allocated
* with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 5f49785cb3..733e29b5f8 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -927,6 +927,12 @@ void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_zipl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_ziph_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_uzpe_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index b4e16cfbc3..c911d62442 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -229,6 +229,13 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+DEF(zipl_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
+DEF(ziph_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
+DEF(uzpe_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
+DEF(uzpo_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
+DEF(trne_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+DEF(trno_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#if TCG_TARGET_MAYBE_vec
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 2cba208b4c..c6f7157c60 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -178,6 +178,9 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_zip_vec 0
+#define TCG_TARGET_HAS_uzp_vec 0
+#define TCG_TARGET_HAS_trn_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index cd1ce12b7e..628df811b2 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -293,3 +293,81 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
}
clear_high(d, oprsz, desc);
}
+
+/* The size of the alloca in the following is currently bounded to 2k. */
+
+#define DO_ZIP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t oprsz_2 = oprsz / 2; \
+ intptr_t i; \
+ /* We produce output faster than we consume input. \
+ Therefore we must be mindful of possible overlap. */ \
+ if (unlikely((a - d) < (uintptr_t)oprsz)) { \
+ void *a_new = alloca(oprsz_2); \
+ memcpy(a_new, a, oprsz_2); \
+ a = a_new; \
+ } \
+ if (unlikely((b - d) < (uintptr_t)oprsz)) { \
+ void *b_new = alloca(oprsz_2); \
+ memcpy(b_new, b, oprsz_2); \
+ b = b_new; \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
+ *(TYPE *)(d + 2 * i + 0) = *(TYPE *)(a + i); \
+ *(TYPE *)(d + 2 * i + sizeof(TYPE)) = *(TYPE *)(b + i); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_ZIP(gvec_zip8, uint8_t)
+DO_ZIP(gvec_zip16, uint16_t)
+DO_ZIP(gvec_zip32, uint32_t)
+DO_ZIP(gvec_zip64, uint64_t)
+
+#define DO_UZP(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t oprsz_2 = oprsz / 2; \
+ intptr_t odd_ofs = simd_data(desc); \
+ intptr_t i; \
+ if (unlikely((b - d) < (uintptr_t)oprsz)) { \
+ void *b_new = alloca(oprsz); \
+ memcpy(b_new, b, oprsz); \
+ b = b_new; \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
+ *(TYPE *)(d + i) = *(TYPE *)(a + 2 * i + odd_ofs); \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE)) { \
+ *(TYPE *)(d + oprsz_2 + i) = *(TYPE *)(b + 2 * i + odd_ofs); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_UZP(gvec_uzp8, uint8_t)
+DO_UZP(gvec_uzp16, uint16_t)
+DO_UZP(gvec_uzp32, uint32_t)
+DO_UZP(gvec_uzp64, uint64_t)
+
+#define DO_TRN(NAME, TYPE) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t odd_ofs = simd_data(desc); \
+ intptr_t i; \
+ for (i = 0; i < oprsz; i += 2 * sizeof(TYPE)) { \
+ TYPE ae = *(TYPE *)(a + i + odd_ofs); \
+ TYPE be = *(TYPE *)(b + i + odd_ofs); \
+ *(TYPE *)(d + i + 0) = ae; \
+ *(TYPE *)(d + i + sizeof(TYPE)) = be; \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_TRN(gvec_trn8, uint8_t)
+DO_TRN(gvec_trn16, uint16_t)
+DO_TRN(gvec_trn32, uint32_t)
+DO_TRN(gvec_trn64, uint64_t)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 925c293f9c..a64baa9dcf 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -466,7 +466,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
use a cl-sized store to implement the clearing without an extra
store operation. This is true for aarch64 and x86_64 hosts. */
- if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
expand_2_vec(g->vece, dofs, aofs, done, 32, TCG_TYPE_V256, g->fniv);
dofs += done;
@@ -475,7 +476,8 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
maxsz -= done;
}
- if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
uint32_t done = QEMU_ALIGN_DOWN(oprsz, 16);
expand_2_vec(g->vece, dofs, aofs, done, 16, TCG_TYPE_V128, g->fniv);
dofs += done;
@@ -486,7 +488,9 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
if (check_size_impl(oprsz, 8)) {
uint32_t done = QEMU_ALIGN_DOWN(oprsz, 8);
- if (TCG_TARGET_HAS_v64 && !g->prefer_i64) {
+ if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
expand_2_vec(g->vece, dofs, aofs, done, 8, TCG_TYPE_V64, g->fniv);
} else if (g->fni8) {
expand_2_i64(dofs, aofs, done, g->fni8);
@@ -516,7 +520,7 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
}
do_ool:
- tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, 0, g->fno);
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
}
/* Expand a vector three-operand operation. */
@@ -539,7 +543,8 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
use a cl-sized store to implement the clearing without an extra
store operation. This is true for aarch64 and x86_64 hosts. */
- if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)) {
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
expand_3_vec(g->vece, dofs, aofs, bofs, done, 32, TCG_TYPE_V256,
g->load_dest, g->fniv);
@@ -550,7 +555,8 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
maxsz -= done;
}
- if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)) {
+ if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
uint32_t done = QEMU_ALIGN_DOWN(oprsz, 16);
expand_3_vec(g->vece, dofs, aofs, bofs, done, 16, TCG_TYPE_V128,
g->load_dest, g->fniv);
@@ -563,7 +569,9 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
if (check_size_impl(oprsz, 8)) {
uint32_t done = QEMU_ALIGN_DOWN(oprsz, 8);
- if (TCG_TARGET_HAS_v64 && !g->prefer_i64) {
+ if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
expand_3_vec(g->vece, dofs, aofs, bofs, done, 8, TCG_TYPE_V64,
g->load_dest, g->fniv);
} else if (g->fni8) {
@@ -596,7 +604,7 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
}
do_ool:
- tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, g->fno);
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, g->data, g->fno);
}
/*
@@ -1015,3 +1023,316 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
};
tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g);
}
+
+static void do_zip(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz,
+ bool high)
+{
+ static gen_helper_gvec_3 * const zip_fns[4] = {
+ gen_helper_gvec_zip8,
+ gen_helper_gvec_zip16,
+ gen_helper_gvec_zip32,
+ gen_helper_gvec_zip64,
+ };
+
+ TCGType type;
+ uint32_t step, i, n;
+ TCGOpcode zip_op;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, oprsz);
+ tcg_debug_assert(vece <= MO_64);
+
+ /* Quick check for sizes we won't support inline. */
+ if (oprsz > 4 * 32 || maxsz > MAX_UNROLL * 32) {
+ goto do_ool;
+ }
+
+ zip_op = high ? INDEX_op_ziph_vec : INDEX_op_zipl_vec;
+
+ /* Since these operations don't operate in lock-step lanes,
+ we must care for overlap. */
+ if (TCG_TARGET_HAS_v256 && oprsz % 32 == 0 && oprsz / 32 <= 8
+ && tcg_can_emit_vec_op(zip_op, TCG_TYPE_V256, vece)) {
+ type = TCG_TYPE_V256;
+ step = 32;
+ n = oprsz / 32;
+ } else if (TCG_TARGET_HAS_v128 && oprsz % 16 == 0 && oprsz / 16 <= 8
+ && tcg_can_emit_vec_op(zip_op, TCG_TYPE_V128, vece)) {
+ type = TCG_TYPE_V128;
+ step = 16;
+ n = oprsz / 16;
+ } else if (TCG_TARGET_HAS_v64 && oprsz % 8 == 0 && oprsz / 8 <= 8
+ && tcg_can_emit_vec_op(zip_op, TCG_TYPE_V64, vece)) {
+ type = TCG_TYPE_V64;
+ step = 8;
+ n = oprsz / 8;
+ } else {
+ goto do_ool;
+ }
+
+ if (n == 1) {
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+
+ tcg_gen_ld_vec(t1, cpu_env, aofs);
+ tcg_gen_ld_vec(t2, cpu_env, bofs);
+ if (high) {
+ tcg_gen_ziph_vec(vece, t1, t1, t2);
+ } else {
+ tcg_gen_zipl_vec(vece, t1, t1, t2);
+ }
+ tcg_gen_st_vec(t1, cpu_env, dofs);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ } else {
+ TCGv_vec ta[4], tb[4], tmp;
+
+ if (high) {
+ aofs += oprsz / 2;
+ bofs += oprsz / 2;
+ }
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ ta[i] = tcg_temp_new_vec(type);
+ tb[i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(ta[i], cpu_env, aofs + i * step);
+ tcg_gen_ld_vec(tb[i], cpu_env, bofs + i * step);
+ }
+
+ tmp = tcg_temp_new_vec(type);
+ for (i = 0; i < n; ++i) {
+ if (i & 1) {
+ tcg_gen_ziph_vec(vece, tmp, ta[i / 2], tb[i / 2]);
+ } else {
+ tcg_gen_zipl_vec(vece, tmp, ta[i / 2], tb[i / 2]);
+ }
+ tcg_gen_st_vec(tmp, cpu_env, dofs + i * step);
+ }
+ tcg_temp_free_vec(tmp);
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ tcg_temp_free_vec(ta[i]);
+ tcg_temp_free_vec(tb[i]);
+ }
+ }
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+ return;
+
+ do_ool:
+ if (high) {
+ aofs += oprsz / 2;
+ bofs += oprsz / 2;
+ }
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, zip_fns[vece]);
+}
+
+void tcg_gen_gvec_zipl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_zip(vece, dofs, aofs, bofs, oprsz, maxsz, false);
+}
+
+void tcg_gen_gvec_ziph(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_zip(vece, dofs, aofs, bofs, oprsz, maxsz, true);
+}
+
+static void do_uzp(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz, bool odd)
+{
+ static gen_helper_gvec_3 * const uzp_fns[4] = {
+ gen_helper_gvec_uzp8,
+ gen_helper_gvec_uzp16,
+ gen_helper_gvec_uzp32,
+ gen_helper_gvec_uzp64,
+ };
+
+ TCGType type;
+ uint32_t step, i, n;
+ TCGv_vec t[8];
+ TCGOpcode uzp_op;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, oprsz);
+ tcg_debug_assert(vece <= MO_64);
+
+ /* Quick check for sizes we won't support inline. */
+ if (oprsz > 4 * 32 || maxsz > MAX_UNROLL * 32) {
+ goto do_ool;
+ }
+
+ uzp_op = odd ? INDEX_op_uzpo_vec : INDEX_op_uzpe_vec;
+
+ /* Since these operations don't operate in lock-step lanes,
+ we must care for overlap. */
+ if (TCG_TARGET_HAS_v256 && oprsz % 32 == 0 && oprsz / 32 <= 4
+ && tcg_can_emit_vec_op(uzp_op, TCG_TYPE_V256, vece)) {
+ type = TCG_TYPE_V256;
+ step = 32;
+ n = oprsz / 32;
+ } else if (TCG_TARGET_HAS_v128 && oprsz % 16 == 0 && oprsz / 16 <= 4
+ && tcg_can_emit_vec_op(uzp_op, TCG_TYPE_V128, vece)) {
+ type = TCG_TYPE_V128;
+ step = 16;
+ n = oprsz / 16;
+ } else if (TCG_TARGET_HAS_v64 && oprsz % 8 == 0 && oprsz / 8 <= 4
+ && tcg_can_emit_vec_op(uzp_op, TCG_TYPE_V64, vece)) {
+ type = TCG_TYPE_V64;
+ step = 8;
+ n = oprsz / 8;
+ } else {
+ goto do_ool;
+ }
+
+ for (i = 0; i < n; ++i) {
+ t[i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(t[i], cpu_env, aofs + i * step);
+ }
+ for (i = 0; i < n; ++i) {
+ t[n + i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(t[n + i], cpu_env, bofs + i * step);
+ }
+ for (i = 0; i < n; ++i) {
+ if (odd) {
+ tcg_gen_uzpo_vec(vece, t[2 * i], t[2 * i], t[2 * i + 1]);
+ } else {
+ tcg_gen_uzpe_vec(vece, t[2 * i], t[2 * i], t[2 * i + 1]);
+ }
+ tcg_gen_st_vec(t[2 * i], cpu_env, dofs + i * step);
+ tcg_temp_free_vec(t[2 * i]);
+ tcg_temp_free_vec(t[2 * i + 1]);
+ }
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+ return;
+
+ do_ool:
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz,
+ (1 << vece) * odd, uzp_fns[vece]);
+}
+
+void tcg_gen_gvec_uzpe(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_uzp(vece, dofs, aofs, bofs, oprsz, maxsz, false);
+}
+
+void tcg_gen_gvec_uzpo(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
+{
+ do_uzp(vece, dofs, aofs, bofs, oprsz, maxsz, true);
+}
+
+static void gen_trne8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0x00ff00ff00ff00ffull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shli_i64(b, b, 8);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trne16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0x0000ffff0000ffffull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shli_i64(b, b, 16);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trne32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_deposit_i64(d, a, b, 32, 32);
+}
+
+void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = gen_trne8_i64,
+ .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn8,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_8 },
+ { .fni8 = gen_trne16_i64,
+ .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn16,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_16 },
+ { .fni8 = gen_trne32_i64,
+ .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn32,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_32 },
+ { .fniv = tcg_gen_trne_vec,
+ .fno = gen_helper_gvec_trn64,
+ .opc = INDEX_op_trne_vec,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g[vece]);
+}
+
+static void gen_trno8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0xff00ff00ff00ff00ull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shri_i64(a, a, 8);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trno16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ uint64_t m = 0xffff0000ffff0000ull;
+ tcg_gen_andi_i64(a, a, m);
+ tcg_gen_andi_i64(b, b, m);
+ tcg_gen_shri_i64(a, a, 16);
+ tcg_gen_or_i64(d, a, b);
+}
+
+static void gen_trno32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_shri_i64(a, a, 32);
+ tcg_gen_deposit_i64(d, b, a, 0, 32);
+}
+
+void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fni8 = gen_trno8_i64,
+ .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn8,
+ .opc = INDEX_op_trno_vec,
+ .data = 1,
+ .vece = MO_8 },
+ { .fni8 = gen_trno16_i64,
+ .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn16,
+ .opc = INDEX_op_trno_vec,
+ .data = 2,
+ .vece = MO_16 },
+ { .fni8 = gen_trno32_i64,
+ .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn32,
+ .opc = INDEX_op_trno_vec,
+ .data = 4,
+ .vece = MO_32 },
+ { .fniv = tcg_gen_trno_vec,
+ .fno = gen_helper_gvec_trn64,
+ .opc = INDEX_op_trno_vec,
+ .data = 8,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g[vece]);
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 5cfe4af6bd..a5d0ff89c3 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -380,3 +380,58 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
tcg_temp_free_vec(t);
}
}
+
+static void do_interleave(TCGOpcode opc, unsigned vece,
+ TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGArg bi = temp_arg(bt);
+ TCGType type = rt->base_type;
+ unsigned vecl = type - TCG_TYPE_V64;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ tcg_debug_assert((8 << vece) <= (32 << vecl));
+ can = tcg_can_emit_vec_op(opc, type, vece);
+ if (can > 0) {
+ vec_gen_3(opc, type, vece, ri, ai, bi);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(opc, type, vece, ri, ai, bi);
+ }
+}
+
+void tcg_gen_zipl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_zipl_vec, vece, r, a, b);
+}
+
+void tcg_gen_ziph_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_ziph_vec, vece, r, a, b);
+}
+
+void tcg_gen_uzpe_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_uzpe_vec, vece, r, a, b);
+}
+
+void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_uzpo_vec, vece, r, a, b);
+}
+
+void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_trne_vec, vece, r, a, b);
+}
+
+void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ do_interleave(INDEX_op_trno_vec, vece, r, a, b);
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e725b1818f..ec7db4e82d 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1403,6 +1403,15 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ return have_vec && TCG_TARGET_HAS_zip_vec;
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ return have_vec && TCG_TARGET_HAS_uzp_vec;
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ return have_vec && TCG_TARGET_HAS_trn_vec;
default:
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
diff --git a/tcg/README b/tcg/README
index e14990fb9b..8ab8d3ab7e 100644
--- a/tcg/README
+++ b/tcg/README
@@ -561,6 +561,46 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Similarly, logical operations with and without compliment.
Note that VECE is unused.
+* zipl_vec v0, v1, v2
+* ziph_vec v0, v1, v2
+
+ "Zip" two vectors together, either the low half of v1/v2 or the high half.
+ The name comes from ARM ARM; the equivalent function in Intel terminology
+ is the less scrutable "punpck". The effect is
+
+ part = ("high" ? VECL/VECE/2 : 0);
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[2i + 0] = v1[i + part];
+ v0[2i + 1] = v2[i + part];
+ }
+
+* uzpe_vec v0, v1, v2
+* uzpo_vec v0, v1, v2
+
+ "Unzip" two vectors, either the even elements or the odd elements.
+ If v1 and v2 are the result of zipl and ziph, this performs the
+ inverse operation. The effect is
+
+ part = ("odd" ? 1 : 0)
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[i] = v1[2i + part];
+ }
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[i + VECL/VECE/2] = v1[2i + part];
+ }
+
+* trne_vec v0, v1, v2
+* trno_vec v1, v1, v2
+
+ "Transpose" two vectors, either the even elements or the odd elements.
+ The effect is
+
+ part = ("odd" ? 1 : 0)
+ for (i = 0; i < VECL/VECE/2; ++i) {
+ v0[2i + 0] = v1[2i + part];
+ v0[2i + 1] = v2[2i + part];
+ }
+
*********
Note 1: Some shortcuts are defined when the last operand is known to be
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 15/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (13 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 14/26] tcg: Add generic vector ops for interleave Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 16/26] tcg: Add generic vector ops for constant shifts Richard Henderson
` (15 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 103 +++++++++++++++------------------------------
1 file changed, 35 insertions(+), 68 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 55a4902fc2..8769b4505a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5576,11 +5576,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
int opcode = extract32(insn, 12, 2);
bool part = extract32(insn, 14, 1);
bool is_q = extract32(insn, 30, 1);
- int esize = 8 << size;
- int i, ofs;
- int datasize = is_q ? 128 : 64;
- int elements = datasize / esize;
- TCGv_i64 tcg_res, tcg_resl, tcg_resh;
+ GVecGen3Fn *gvec_fn;
if (opcode == 0 || (size == 3 && !is_q)) {
unallocated_encoding(s);
@@ -5591,60 +5587,24 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
return;
}
- tcg_resl = tcg_const_i64(0);
- tcg_resh = tcg_const_i64(0);
- tcg_res = tcg_temp_new_i64();
-
- for (i = 0; i < elements; i++) {
- switch (opcode) {
- case 1: /* UZP1/2 */
- {
- int midpoint = elements / 2;
- if (i < midpoint) {
- read_vec_element(s, tcg_res, rn, 2 * i + part, size);
- } else {
- read_vec_element(s, tcg_res, rm,
- 2 * (i - midpoint) + part, size);
- }
- break;
- }
- case 2: /* TRN1/2 */
- if (i & 1) {
- read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
- } else {
- read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
- }
- break;
- case 3: /* ZIP1/2 */
- {
- int base = part * elements / 2;
- if (i & 1) {
- read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
- } else {
- read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
- }
- break;
- }
- default:
- g_assert_not_reached();
- }
-
- ofs = i * esize;
- if (ofs < 64) {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
- tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
- } else {
- tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
- tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
- }
+ switch (opcode) {
+ case 1: /* UZP1/2 */
+ gvec_fn = part ? tcg_gen_gvec_uzpo : tcg_gen_gvec_uzpe;
+ break;
+ case 2: /* TRN1/2 */
+ gvec_fn = part ? tcg_gen_gvec_trno : tcg_gen_gvec_trne;
+ break;
+ case 3: /* ZIP1/2 */
+ gvec_fn = part ? tcg_gen_gvec_ziph : tcg_gen_gvec_zipl;
+ break;
+ default:
+ g_assert_not_reached();
}
- tcg_temp_free_i64(tcg_res);
-
- write_vec_element(s, tcg_resl, rd, 0, MO_64);
- tcg_temp_free_i64(tcg_resl);
- write_vec_element(s, tcg_resh, rd, 1, MO_64);
- tcg_temp_free_i64(tcg_resh);
+ gvec_fn(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
}
static void do_minmaxop(DisasContext *s, TCGv_i32 tcg_elt1, TCGv_i32 tcg_elt2,
@@ -7922,6 +7882,22 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
int destelt = is_q ? 2 : 0;
int passes = scalar ? 1 : 2;
+ if (opcode == 0x12 && !u) { /* XTN, XTN2 */
+ tcg_debug_assert(!scalar);
+ if (is_q) { /* XTN2 */
+ tcg_gen_gvec_uzpe(size, vec_reg_offset(s, rd, 1, MO_64),
+ vec_reg_offset(s, rn, 0, MO_64),
+ vec_reg_offset(s, rn, 1, MO_64),
+ 8, vec_full_reg_size(s) - 8);
+ } else {
+ tcg_gen_gvec_uzpe(size, vec_reg_offset(s, rd, 0, MO_64),
+ vec_reg_offset(s, rn, 0, MO_64),
+ vec_reg_offset(s, rn, 1, MO_64),
+ 8, vec_full_reg_size(s));
+ }
+ return;
+ }
+
if (scalar) {
tcg_res[1] = tcg_const_i32(0);
}
@@ -7939,23 +7915,14 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
tcg_res[pass] = tcg_temp_new_i32();
switch (opcode) {
- case 0x12: /* XTN, SQXTUN */
+ case 0x12: /* , SQXTUN */
{
- static NeonGenNarrowFn * const xtnfns[3] = {
- gen_helper_neon_narrow_u8,
- gen_helper_neon_narrow_u16,
- tcg_gen_extrl_i64_i32,
- };
static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
gen_helper_neon_unarrow_sat8,
gen_helper_neon_unarrow_sat16,
gen_helper_neon_unarrow_sat32,
};
- if (u) {
- genenvfn = sqxtunfns[size];
- } else {
- genfn = xtnfns[size];
- }
+ genenvfn = sqxtunfns[size];
break;
}
case 0x14: /* SQXTN, UQXTN */
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 16/26] tcg: Add generic vector ops for constant shifts
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (14 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 15/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 17/26] target/arm: Use vector infrastructure for aa64 " Richard Henderson
` (14 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Opcodes are added for scalar and vector shifts, but considering the
varied semantics of these do not expose them to the front ends. Do
go ahead and provide them in case they are needed for backend expansion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 15 +++
tcg/i386/tcg-target.h | 3 +
tcg/tcg-op-gvec.h | 35 ++++++
tcg/tcg-op.h | 5 +
tcg/tcg-opc.h | 12 ++
tcg/tcg.h | 3 +
accel/tcg/tcg-runtime-gvec.c | 149 ++++++++++++++++++++++
tcg/tcg-op-gvec.c | 291 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 40 ++++++
tcg/tcg.c | 12 ++
tcg/README | 29 +++++
11 files changed, 594 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index c6de749134..cb05a755b8 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -164,6 +164,21 @@ DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_shr8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shr16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shr32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_shr64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_sar8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(gvec_zip8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_zip16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_zip32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index ff0ad7dcdb..92d533eb92 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -177,6 +177,9 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_zip_vec 0
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 64270a3c74..de2c0e669a 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -77,6 +77,25 @@ typedef struct {
typedef struct {
/* Expand inline as a 64-bit or 32-bit integer.
Only one of these will be non-NULL. */
+ void (*fni8)(TCGv_i64, TCGv_i64, unsigned);
+ void (*fni4)(TCGv_i32, TCGv_i32, unsigned);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, unsigned);
+ /* Expand out-of-line helper w/descriptor. */
+ gen_helper_gvec_2 *fno;
+ /* The opcode, if any, to which this corresponds. */
+ TCGOpcode opc;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+ /* Load dest as a 3rd source operand. */
+ bool load_dest;
+} GVecGen2i;
+
+typedef struct {
+ /* Expand inline as a 64-bit or 32-bit integer.
+ Only one of these will be non-NULL. */
void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64);
void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32);
/* Expand inline with a host vector type. */
@@ -97,6 +116,8 @@ typedef struct {
void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
uint32_t opsz, uint32_t clsz, const GVecGen2 *);
+void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t opsz,
+ uint32_t clsz, unsigned c, const GVecGen2i *);
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t opsz, uint32_t clsz, const GVecGen3 *);
@@ -137,6 +158,13 @@ void tcg_gen_gvec_dup16i(uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
void tcg_gen_gvec_dup32i(uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
void tcg_gen_gvec_dup64i(uint32_t dofs, uint32_t s, uint32_t m, uint64_t x);
+void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz, unsigned shift);
+void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz, unsigned shift);
+void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz, unsigned shift);
+
void tcg_gen_gvec_zipl(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, uint32_t clsz);
void tcg_gen_gvec_ziph(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -167,3 +195,10 @@ void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
+
+void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned);
+void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, unsigned);
+void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned);
+void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, unsigned);
+void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned);
+void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, unsigned);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 733e29b5f8..83478ab006 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -927,6 +927,11 @@ void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+
+void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, unsigned i);
+void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, unsigned i);
+void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, unsigned i);
+
void tcg_gen_zipl_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_ziph_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_uzpe_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index c911d62442..a085fc077b 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -229,6 +229,18 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
+DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
+DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
+DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
+
+DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
+DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
+DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
+
+DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
+DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
+DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
+
DEF(zipl_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
DEF(ziph_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_zip_vec))
DEF(uzpe_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
diff --git a/tcg/tcg.h b/tcg/tcg.h
index c6f7157c60..5f414d880e 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -178,6 +178,9 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_zip_vec 0
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 628df811b2..fba62f1192 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -36,6 +36,11 @@ typedef uint16_t vec16 __attribute__((vector_size(16)));
typedef uint32_t vec32 __attribute__((vector_size(16)));
typedef uint64_t vec64 __attribute__((vector_size(16)));
+typedef int8_t svec8 __attribute__((vector_size(16)));
+typedef int16_t svec16 __attribute__((vector_size(16)));
+typedef int32_t svec32 __attribute__((vector_size(16)));
+typedef int64_t svec64 __attribute__((vector_size(16)));
+
static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc)
{
intptr_t maxsz = simd_maxsz(desc);
@@ -294,6 +299,150 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_shl8i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl16i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl32i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shl64i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) << shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr8i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr16i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr32i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_shr64i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar8i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(svec8 *)(d + i) = *(svec8 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar16i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(svec16 *)(d + i) = *(svec16 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar32i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(svec32 *)(d + i) = *(svec32 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ int shift = simd_data(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(svec64 *)(d + i) = *(svec64 *)(a + i) >> shift;
+ }
+ clear_high(d, oprsz, desc);
+}
+
/* The size of the alloca in the following is currently bounded to 2k. */
#define DO_ZIP(NAME, TYPE) \
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index a64baa9dcf..f8ccb137eb 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -342,6 +342,26 @@ static void expand_2_i32(uint32_t dofs, uint32_t aofs, uint32_t opsz,
tcg_temp_free_i32(t0);
}
+static void expand_2i_i32(uint32_t dofs, uint32_t aofs, uint32_t opsz,
+ unsigned c, bool load_dest,
+ void (*fni)(TCGv_i32, TCGv_i32, unsigned))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i32(t1, cpu_env, dofs + i);
+ }
+ fni(t1, t0, c);
+ tcg_gen_st_i32(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
static void expand_3_i32(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, bool load_dest,
@@ -381,6 +401,26 @@ static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t opsz,
tcg_temp_free_i64(t0);
}
+static void expand_2i_i64(uint32_t dofs, uint32_t aofs, uint32_t opsz,
+ unsigned c, bool load_dest,
+ void (*fni)(TCGv_i64, TCGv_i64, unsigned))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ if (load_dest) {
+ tcg_gen_ld_i64(t1, cpu_env, dofs + i);
+ }
+ fni(t1, t0, c);
+ tcg_gen_st_i64(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
static void expand_3_i64(uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, bool load_dest,
@@ -421,6 +461,29 @@ static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_temp_free_vec(t0);
}
+/* Expand OPSZ bytes worth of two-vector operands and an immediate operand
+ using host vectors. */
+static void expand_2i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t tysz, TCGType type,
+ unsigned c, bool load_dest,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec, unsigned))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ if (load_dest) {
+ tcg_gen_ld_vec(t1, cpu_env, dofs + i);
+ }
+ fni(vece, t1, t0, c);
+ tcg_gen_st_vec(t1, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t0);
+ tcg_temp_free_vec(t1);
+}
+
/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
static void expand_3_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz,
@@ -523,6 +586,85 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, g->data, g->fno);
}
+void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
+ uint32_t maxsz, unsigned c, const GVecGen2i *g)
+{
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, maxsz);
+
+ /* Quick check for sizes we won't support inline. */
+ if (oprsz > MAX_UNROLL * 32 || maxsz > MAX_UNROLL * 32) {
+ goto do_ool;
+ }
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+ /* ??? For maxsz > oprsz, the host may be able to use an op-sized
+ operation, zeroing the balance of the register. We can then
+ use a cl-sized store to implement the clearing without an extra
+ store operation. This is true for aarch64 and x86_64 hosts. */
+
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_2i_vec(g->vece, dofs, aofs, done, 32, TCG_TYPE_V256,
+ c, g->load_dest, g->fniv);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)
+ && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 16);
+ expand_2i_vec(g->vece, dofs, aofs, done, 16, TCG_TYPE_V128,
+ c, g->load_dest, g->fniv);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (check_size_impl(oprsz, 8)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 8);
+ if (TCG_TARGET_HAS_v64 && !g->prefer_i64
+ && (!g->opc
+ || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
+ expand_2i_vec(g->vece, dofs, aofs, done, 8, TCG_TYPE_V64,
+ c, g->load_dest, g->fniv);
+ } else if (g->fni8) {
+ expand_2i_i64(dofs, aofs, done, c, g->load_dest, g->fni8);
+ } else {
+ done = 0;
+ }
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (g->fni4 && check_size_impl(oprsz, 4)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 4);
+ expand_2i_i32(dofs, aofs, done, c, g->load_dest, g->fni4);
+ dofs += done;
+ aofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (oprsz == 0) {
+ if (maxsz != 0) {
+ expand_clr(dofs, maxsz);
+ }
+ return;
+ }
+
+ do_ool:
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, 0, g->fno);
+}
+
/* Expand a vector three-operand operation. */
void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
@@ -1024,6 +1166,155 @@ void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g);
}
+void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
+{
+ uint64_t mask = ((0xff << c) & 0xff) * (-1ull / 0xff);
+ tcg_gen_shli_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
+{
+ uint64_t mask = ((0xffff << c) & 0xffff) * (-1ull / 0xffff);
+ tcg_gen_shli_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz, unsigned shift)
+{
+ static const GVecGen2i g[4] = {
+ { .fni8 = tcg_gen_vec_shl8i_i64,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl8i,
+ .opc = INDEX_op_shli_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_shl16i_i64,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl16i,
+ .opc = INDEX_op_shli_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_shli_i32,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl32i,
+ .opc = INDEX_op_shli_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_shli_i64,
+ .fniv = tcg_gen_shli_vec,
+ .fno = gen_helper_gvec_shl64i,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+}
+
+void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
+{
+ uint64_t mask = (0xff >> c) * (-1ull / 0xff);
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
+{
+ uint64_t mask = (0xffff >> c) * (-1ull / 0xffff);
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(d, d, mask);
+}
+
+void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz, unsigned shift)
+{
+ static const GVecGen2i g[4] = {
+ { .fni8 = tcg_gen_vec_shr8i_i64,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr8i,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_shr16i_i64,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr16i,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_shri_i32,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr32i,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_shri_i64,
+ .fniv = tcg_gen_shri_vec,
+ .fno = gen_helper_gvec_shr64i,
+ .opc = INDEX_op_shri_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+}
+
+void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
+{
+ uint64_t s_mask = (0x80 >> c) * (-1ull / 0xff);
+ uint64_t c_mask = (0xff >> c) * (-1ull / 0xff);
+ TCGv_i64 s = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
+ tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
+ tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
+ tcg_gen_or_i64(d, d, s); /* include sign extension */
+ tcg_temp_free_i64(s);
+}
+
+void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
+{
+ uint64_t s_mask = (0x8000 >> c) * (-1ull / 0xffff);
+ uint64_t c_mask = (0xffff >> c) * (-1ull / 0xffff);
+ TCGv_i64 s = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(d, a, c);
+ tcg_gen_andi_i64(s, d, s_mask); /* isolate (shifted) sign bit */
+ tcg_gen_andi_i64(d, d, c_mask); /* clear out bits above sign */
+ tcg_gen_muli_i64(s, s, (2 << c) - 2); /* replicate isolated signs */
+ tcg_gen_or_i64(d, d, s); /* include sign extension */
+ tcg_temp_free_i64(s);
+}
+
+void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz, unsigned shift)
+{
+ static const GVecGen2i g[4] = {
+ { .fni8 = tcg_gen_vec_sar8i_i64,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar8i,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_8 },
+ { .fni8 = tcg_gen_vec_sar16i_i64,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar16i,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_sari_i32,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar32i,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_sari_i64,
+ .fniv = tcg_gen_sari_vec,
+ .fno = gen_helper_gvec_sar64i,
+ .opc = INDEX_op_sari_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+}
+
static void do_zip(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t oprsz, uint32_t maxsz,
bool high)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index a5d0ff89c3..a441193b8e 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -381,6 +381,46 @@ void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
}
}
+static void do_shifti(TCGOpcode opc, unsigned vece,
+ TCGv_vec r, TCGv_vec a, unsigned i)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGType type = rt->base_type;
+ unsigned vecl = type - TCG_TYPE_V64;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(i < (8 << vece));
+ can = tcg_can_emit_vec_op(opc, type, vece);
+ if (can > 0) {
+ vec_gen_3(opc, type, vece, ri, ai, i);
+ } else {
+ /* We leave the choice of expansion via scalar or vector shift
+ to the target. Often, but not always, dupi can feed a vector
+ shift easier than a scalar. */
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(opc, vecl, vece, ri, ai, i);
+ }
+}
+
+void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, unsigned i)
+{
+ do_shifti(INDEX_op_shli_vec, vece, r, a, i);
+}
+
+void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, unsigned i)
+{
+ do_shifti(INDEX_op_shri_vec, vece, r, a, i);
+}
+
+void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, unsigned i)
+{
+ do_shifti(INDEX_op_sari_vec, vece, r, a, i);
+}
+
static void do_interleave(TCGOpcode opc, unsigned vece,
TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
diff --git a/tcg/tcg.c b/tcg/tcg.c
index ec7db4e82d..4bde7d6afd 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1403,6 +1403,18 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ return have_vec && TCG_TARGET_HAS_shi_vec;
+ case INDEX_op_shls_vec:
+ case INDEX_op_shrs_vec:
+ case INDEX_op_sars_vec:
+ return have_vec && TCG_TARGET_HAS_shs_vec;
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ return have_vec && TCG_TARGET_HAS_shv_vec;
case INDEX_op_zipl_vec:
case INDEX_op_ziph_vec:
return have_vec && TCG_TARGET_HAS_zip_vec;
diff --git a/tcg/README b/tcg/README
index 8ab8d3ab7e..75db47922d 100644
--- a/tcg/README
+++ b/tcg/README
@@ -561,6 +561,35 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Similarly, logical operations with and without compliment.
Note that VECE is unused.
+* shli_vec v0, v1, i2
+* shls_vec v0, v1, s2
+
+ Shift all elements from v1 by a scalar i2/s2. I.e.
+
+ for (i = 0; i < VECL/VECE; ++i) {
+ v0[i] = v1[i] << s2;
+ }
+
+* shri_vec v0, v1, i2
+* sari_vec v0, v1, i2
+* shrs_vec v0, v1, s2
+* sars_vec v0, v1, s2
+
+ Similarly for logical and arithmetic right shift.
+
+* shlv_vec v0, v1, v2
+
+ Shift elements from v1 by elements from v2. I.e.
+
+ for (i = 0; i < VECL/VECE; ++i) {
+ v0[i] = v1[i] << v2[i];
+ }
+
+* shrv_vec v0, v1, v2
+* sarv_vec v0, v1, v2
+
+ Similarly for logical and arithmetic right shift.
+
* zipl_vec v0, v1, v2
* ziph_vec v0, v1, v2
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 17/26] target/arm: Use vector infrastructure for aa64 constant shifts
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (15 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 16/26] tcg: Add generic vector ops for constant shifts Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 18/26] tcg: Add generic vector ops for comparisons Richard Henderson
` (13 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 386 ++++++++++++++++++++++++++++++++++++++-------
tcg/tcg-op-gvec.c | 18 ++-
tcg/tcg-op-vec.c | 9 +-
3 files changed, 351 insertions(+), 62 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 8769b4505a..c47faa5633 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6432,17 +6432,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
}
}
-/* Common SHL/SLI - Shift left with an optional insert */
-static void handle_shli_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
- bool insert, int shift)
-{
- if (insert) { /* SLI */
- tcg_gen_deposit_i64(tcg_res, tcg_res, tcg_src, shift, 64 - shift);
- } else { /* SHL */
- tcg_gen_shli_i64(tcg_res, tcg_src, shift);
- }
-}
-
/* SRI: shift right with insert */
static void handle_shri_with_ins(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
int size, int shift)
@@ -6546,7 +6535,11 @@ static void handle_scalar_simd_shli(DisasContext *s, bool insert,
tcg_rn = read_fp_dreg(s, rn);
tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
- handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
+ if (insert) {
+ tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift);
+ } else {
+ tcg_gen_shli_i64(tcg_rd, tcg_rn, shift);
+ }
write_fp_dreg(s, rd, tcg_rd);
@@ -8283,16 +8276,195 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
}
+static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_vec_sar8i_i64(a, a, shift);
+ tcg_gen_vec_add8_i64(d, d, a);
+}
+
+static void gen_ssra16_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_vec_sar16i_i64(a, a, shift);
+ tcg_gen_vec_add16_i64(d, d, a);
+}
+
+static void gen_ssra32_i32(TCGv_i32 d, TCGv_i32 a, unsigned shift)
+{
+ tcg_gen_sari_i32(a, a, shift);
+ tcg_gen_add_i32(d, d, a);
+}
+
+static void gen_ssra64_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_sari_i64(a, a, shift);
+ tcg_gen_add_i64(d, d, a);
+}
+
+static void gen_ssra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, unsigned sh)
+{
+ tcg_gen_sari_vec(vece, a, a, sh);
+ tcg_gen_add_vec(vece, d, d, a);
+}
+
+static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_vec_shr8i_i64(a, a, shift);
+ tcg_gen_vec_add8_i64(d, d, a);
+}
+
+static void gen_usra16_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_vec_shr16i_i64(a, a, shift);
+ tcg_gen_vec_add16_i64(d, d, a);
+}
+
+static void gen_usra32_i32(TCGv_i32 d, TCGv_i32 a, unsigned shift)
+{
+ tcg_gen_shri_i32(a, a, shift);
+ tcg_gen_add_i32(d, d, a);
+}
+
+static void gen_usra64_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_shri_i64(a, a, shift);
+ tcg_gen_add_i64(d, d, a);
+}
+
+static void gen_usra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, unsigned sh)
+{
+ tcg_gen_shri_vec(vece, a, a, sh);
+ tcg_gen_add_vec(vece, d, d, a);
+}
+
+static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ uint64_t mask = (0xff >> shift) * (-1ull / 0xff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ uint64_t mask = (0xffff >> shift) * (-1ull / 0xffff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, unsigned shift)
+{
+ tcg_gen_shri_i32(a, a, shift);
+ tcg_gen_deposit_i32(d, d, a, 0, 32 - shift);
+}
+
+static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_shri_i64(a, a, shift);
+ tcg_gen_deposit_i64(d, d, a, 0, 64 - shift);
+}
+
+static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, unsigned sh)
+{
+ uint64_t mask = (2ull << ((8 << vece) - 1)) - 1;
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_temp_new_vec_matching(d);
+
+ tcg_gen_dupi_vec(vece, m, mask ^ (mask >> sh));
+ tcg_gen_shri_vec(vece, t, a, sh);
+ tcg_gen_and_vec(vece, d, d, m);
+ tcg_gen_or_vec(vece, d, d, t);
+
+ tcg_temp_free_vec(t);
+ tcg_temp_free_vec(m);
+}
+
/* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
int immh, int immb, int opcode, int rn, int rd)
{
+ static const GVecGen2i ssra_op[4] = {
+ { .fni8 = gen_ssra8_i64,
+ .fniv = gen_ssra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_8 },
+ { .fni8 = gen_ssra16_i64,
+ .fniv = gen_ssra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_16 },
+ { .fni4 = gen_ssra32_i32,
+ .fniv = gen_ssra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_32 },
+ { .fni8 = gen_ssra64_i64,
+ .fniv = gen_ssra_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opc = INDEX_op_sari_vec,
+ .vece = MO_64 },
+ };
+ static const GVecGen2i usra_op[4] = {
+ { .fni8 = gen_usra8_i64,
+ .fniv = gen_usra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_8, },
+ { .fni8 = gen_usra16_i64,
+ .fniv = gen_usra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_16, },
+ { .fni4 = gen_usra32_i32,
+ .fniv = gen_usra_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_32, },
+ { .fni8 = gen_usra64_i64,
+ .fniv = gen_usra_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_64, },
+ };
+ static const GVecGen2i sri_op[4] = {
+ { .fni8 = gen_shr8_ins_i64,
+ .fniv = gen_shr_ins_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_8 },
+ { .fni8 = gen_shr16_ins_i64,
+ .fniv = gen_shr_ins_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_16 },
+ { .fni4 = gen_shr32_ins_i32,
+ .fniv = gen_shr_ins_vec,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_32 },
+ { .fni8 = gen_shr64_ins_i64,
+ .fniv = gen_shr_ins_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .opc = INDEX_op_shri_vec,
+ .vece = MO_64 },
+ };
+
int size = 32 - clz32(immh) - 1;
int immhb = immh << 3 | immb;
int shift = 2 * (8 << size) - immhb;
bool accumulate = false;
- bool round = false;
- bool insert = false;
int dsize = is_q ? 128 : 64;
int esize = 8 << size;
int elements = dsize/esize;
@@ -8300,6 +8472,8 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
TCGv_i64 tcg_rn = new_tmp_a64(s);
TCGv_i64 tcg_rd = new_tmp_a64(s);
TCGv_i64 tcg_round;
+ uint64_t round_const;
+ const GVecGen2i *gvec_op;
int i;
if (extract32(immh, 3, 1) && !is_q) {
@@ -8318,64 +8492,141 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
switch (opcode) {
case 0x02: /* SSRA / USRA (accumulate) */
- accumulate = true;
- break;
+ if (is_u) {
+ /* Shift count same as element size produces zero to add. */
+ if (shift == 8 << size) {
+ goto done;
+ }
+ gvec_op = &usra_op[size];
+ } else {
+ /* Shift count same as element size produces all sign to add. */
+ if (shift == 8 << size) {
+ shift -= 1;
+ }
+ gvec_op = &ssra_op[size];
+ }
+ goto do_gvec;
+ case 0x08: /* SRI */
+ /* Shift count same as element size is valid but does nothing. */
+ if (shift == 8 << size) {
+ goto done;
+ }
+ gvec_op = &sri_op[size];
+ do_gvec:
+ tcg_gen_gvec_2i(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift, gvec_op);
+ return;
+
+ case 0x00: /* SSHR / USHR */
+ if (is_u) {
+ if (shift == 8 << size) {
+ /* Shift count the same size as element size produces zero. */
+ tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd),
+ is_q ? 16 : 8, vec_full_reg_size(s), 0);
+ } else {
+ tcg_gen_gvec_shri(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift);
+ }
+ } else {
+ /* Shift count the same size as element size produces all sign. */
+ if (shift == 8 << size) {
+ shift -= 1;
+ }
+ tcg_gen_gvec_sari(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift);
+ }
+ return;
+
case 0x04: /* SRSHR / URSHR (rounding) */
- round = true;
break;
case 0x06: /* SRSRA / URSRA (accum + rounding) */
- accumulate = round = true;
- break;
- case 0x08: /* SRI */
- insert = true;
+ accumulate = true;
break;
+ default:
+ g_assert_not_reached();
}
- if (round) {
- uint64_t round_const = 1ULL << (shift - 1);
- tcg_round = tcg_const_i64(round_const);
- } else {
- tcg_round = NULL;
- }
+ round_const = 1ULL << (shift - 1);
+ tcg_round = tcg_const_i64(round_const);
for (i = 0; i < elements; i++) {
read_vec_element(s, tcg_rn, rn, i, memop);
- if (accumulate || insert) {
+ if (accumulate) {
read_vec_element(s, tcg_rd, rd, i, memop);
}
- if (insert) {
- handle_shri_with_ins(tcg_rd, tcg_rn, size, shift);
- } else {
- handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
- accumulate, is_u, size, shift);
- }
+ handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
+ accumulate, is_u, size, shift);
write_vec_element(s, tcg_rd, rd, i, size);
}
+ tcg_temp_free_i64(tcg_round);
+ done:
if (!is_q) {
clear_vec_high(s, rd);
}
+}
- if (round) {
- tcg_temp_free_i64(tcg_round);
- }
+static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ uint64_t mask = ((0xff << shift) & 0xff) * (-1ull / 0xff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shli_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ uint64_t mask = ((0xffff << shift) & 0xffff) * (-1ull / 0xffff);
+ TCGv_i64 t = tcg_temp_new_i64();
+
+ tcg_gen_shli_i64(t, a, shift);
+ tcg_gen_andi_i64(t, t, mask);
+ tcg_gen_andi_i64(d, d, ~mask);
+ tcg_gen_or_i64(d, d, t);
+ tcg_temp_free_i64(t);
+}
+
+static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, unsigned shift)
+{
+ tcg_gen_deposit_i32(d, d, a, shift, 32 - shift);
+}
+
+static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, unsigned shift)
+{
+ tcg_gen_deposit_i64(d, d, a, shift, 64 - shift);
+}
+
+static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, unsigned sh)
+{
+ uint64_t mask = (1ull << sh) - 1;
+ TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_temp_new_vec_matching(d);
+
+ tcg_gen_dupi_vec(vece, m, mask);
+ tcg_gen_shli_vec(vece, t, a, sh);
+ tcg_gen_and_vec(vece, d, d, m);
+ tcg_gen_or_vec(vece, d, d, t);
+
+ tcg_temp_free_vec(t);
+ tcg_temp_free_vec(m);
}
/* SHL/SLI - Vector shift left */
static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
- int immh, int immb, int opcode, int rn, int rd)
+ int immh, int immb, int opcode, int rn, int rd)
{
int size = 32 - clz32(immh) - 1;
int immhb = immh << 3 | immb;
int shift = immhb - (8 << size);
- int dsize = is_q ? 128 : 64;
- int esize = 8 << size;
- int elements = dsize/esize;
- TCGv_i64 tcg_rn = new_tmp_a64(s);
- TCGv_i64 tcg_rd = new_tmp_a64(s);
- int i;
if (extract32(immh, 3, 1) && !is_q) {
unallocated_encoding(s);
@@ -8391,19 +8642,40 @@ static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
return;
}
- for (i = 0; i < elements; i++) {
- read_vec_element(s, tcg_rn, rn, i, size);
- if (insert) {
- read_vec_element(s, tcg_rd, rd, i, size);
- }
-
- handle_shli_with_ins(tcg_rd, tcg_rn, insert, shift);
-
- write_vec_element(s, tcg_rd, rd, i, size);
- }
-
- if (!is_q) {
- clear_vec_high(s, rd);
+ if (insert) {
+ static const GVecGen2i shi_op[4] = {
+ { .fni8 = gen_shl8_ins_i64,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_8 },
+ { .fni8 = gen_shl16_ins_i64,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_16 },
+ { .fni4 = gen_shl32_ins_i32,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_32 },
+ { .fni8 = gen_shl64_ins_i64,
+ .fniv = gen_shl_ins_vec,
+ .opc = INDEX_op_shli_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_64 },
+ };
+ tcg_gen_gvec_2i(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift, &shi_op[size]);
+ } else {
+ tcg_gen_gvec_shli(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), is_q ? 16 : 8,
+ vec_full_reg_size(s), shift);
}
}
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index f8ccb137eb..d91b424dfc 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1208,7 +1208,11 @@ void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs,
};
tcg_debug_assert(vece <= MO_64);
- tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+ if (shift == 0) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, opsz, clsz);
+ } else {
+ tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+ }
}
void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
@@ -1253,7 +1257,11 @@ void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs,
};
tcg_debug_assert(vece <= MO_64);
- tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+ if (shift == 0) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, opsz, clsz);
+ } else {
+ tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+ }
}
void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, unsigned c)
@@ -1312,7 +1320,11 @@ void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs,
};
tcg_debug_assert(vece <= MO_64);
- tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+ if (shift == 0) {
+ tcg_gen_gvec_mov(vece, dofs, aofs, opsz, clsz);
+ } else {
+ tcg_gen_gvec_2i(dofs, aofs, opsz, clsz, shift, &g[vece]);
+ }
}
static void do_zip(unsigned vece, uint32_t dofs, uint32_t aofs,
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index a441193b8e..502c5ba891 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -389,11 +389,16 @@ static void do_shifti(TCGOpcode opc, unsigned vece,
TCGArg ri = temp_arg(rt);
TCGArg ai = temp_arg(at);
TCGType type = rt->base_type;
- unsigned vecl = type - TCG_TYPE_V64;
int can;
tcg_debug_assert(at->base_type == type);
tcg_debug_assert(i < (8 << vece));
+
+ if (i == 0) {
+ tcg_gen_mov_vec(r, a);
+ return;
+ }
+
can = tcg_can_emit_vec_op(opc, type, vece);
if (can > 0) {
vec_gen_3(opc, type, vece, ri, ai, i);
@@ -402,7 +407,7 @@ static void do_shifti(TCGOpcode opc, unsigned vece,
to the target. Often, but not always, dupi can feed a vector
shift easier than a scalar. */
tcg_debug_assert(can < 0);
- tcg_expand_vec_op(opc, vecl, vece, ri, ai, i);
+ tcg_expand_vec_op(opc, type, vece, ri, ai, i);
}
}
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 18/26] tcg: Add generic vector ops for comparisons
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (16 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 17/26] target/arm: Use vector infrastructure for aa64 " Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 19/26] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
` (12 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 30 +++++++
tcg/i386/tcg-target.h | 1 +
tcg/tcg-op-gvec.h | 4 +
tcg/tcg-op.h | 3 +
tcg/tcg-opc.h | 2 +
tcg/tcg.h | 1 +
accel/tcg/tcg-runtime-gvec.c | 24 +++++
tcg/tcg-op-gvec.c | 202 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 23 +++++
tcg/tcg.c | 2 +
tcg/README | 4 +
11 files changed, 296 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index cb05a755b8..28abf30d76 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -193,3 +193,33 @@ DEF_HELPER_FLAGS_4(gvec_trn8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_eq64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_ne8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ne16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ne32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ne64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_lt8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_lt16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_lt32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_lt64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_le8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_le16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_le32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_le64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_ltu8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ltu16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ltu32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_ltu64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(gvec_leu8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_leu16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_leu32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_leu64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 92d533eb92..46c4dca7be 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -183,6 +183,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_zip_vec 0
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
+#define TCG_TARGET_HAS_cmp_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index de2c0e669a..308bdc13b4 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -178,6 +178,10 @@ void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
+ uint32_t aofs, uint32_t bofs,
+ uint32_t opsz, uint32_t clsz);
+
/*
* 64-bit vector operations. Use these when the register has been allocated
* with tcg_global_mem_new_i64, and so we cannot also address it via pointer.
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 83478ab006..b4f73c6048 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -939,6 +939,9 @@ void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
+ TCGv_vec a, TCGv_vec b);
+
void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index a085fc077b..d3fa014507 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -248,6 +248,8 @@ DEF(uzpo_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
DEF(trne_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
DEF(trno_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+DEF(cmp_vec, 1, 2, 1, IMPLVEC)
+
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#if TCG_TARGET_MAYBE_vec
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 5f414d880e..96760dd2d6 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -184,6 +184,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_zip_vec 0
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
+#define TCG_TARGET_HAS_cmp_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index fba62f1192..e0cde3216f 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -520,3 +520,27 @@ DO_TRN(gvec_trn8, uint8_t)
DO_TRN(gvec_trn16, uint16_t)
DO_TRN(gvec_trn32, uint32_t)
DO_TRN(gvec_trn64, uint64_t)
+
+#define DO_CMP1(NAME, TYPE, OP) \
+void HELPER(NAME)(void *d, void *a, void *b, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t i; \
+ for (i = 0; i < oprsz; i += sizeof(vec64)) { \
+ *(TYPE *)(d + i) = *(TYPE *)(a + i) OP *(TYPE *)(b + i); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+#define DO_CMP2(SZ) \
+ DO_CMP1(gvec_eq##SZ, vec##SZ, ==) \
+ DO_CMP1(gvec_ne##SZ, vec##SZ, !=) \
+ DO_CMP1(gvec_lt##SZ, svec##SZ, <) \
+ DO_CMP1(gvec_le##SZ, svec##SZ, <=) \
+ DO_CMP1(gvec_ltu##SZ, vec##SZ, <) \
+ DO_CMP1(gvec_leu##SZ, vec##SZ, <=)
+
+DO_CMP2(8)
+DO_CMP2(16)
+DO_CMP2(32)
+DO_CMP2(64)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index d91b424dfc..1cc28b459f 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1639,3 +1639,205 @@ void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_debug_assert(vece <= MO_64);
tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g[vece]);
}
+
+/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
+static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t opsz, TCGCond cond)
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 4) {
+ tcg_gen_ld_i32(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t1, cpu_env, bofs + i);
+ tcg_gen_setcond_i32(cond, t0, t0, t1);
+ tcg_gen_neg_i32(t0, t0);
+ tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t0);
+}
+
+static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t opsz, TCGCond cond)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += 8) {
+ tcg_gen_ld_i64(t0, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t1, cpu_env, bofs + i);
+ tcg_gen_setcond_i64(cond, t0, t0, t1);
+ tcg_gen_neg_i64(t0, t0);
+ tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t0);
+}
+
+static void expand_cmp_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t tysz,
+ TCGType type, TCGCond cond)
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < opsz; i += tysz) {
+ tcg_gen_ld_vec(t0, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t1, cpu_env, bofs + i);
+ tcg_gen_cmp_vec(cond, vece, t0, t0, t1);
+ tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t0);
+}
+
+void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
+ uint32_t aofs, uint32_t bofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ static gen_helper_gvec_3 * const eq_fn[4] = {
+ gen_helper_gvec_eq8, gen_helper_gvec_eq16,
+ gen_helper_gvec_eq32, gen_helper_gvec_eq64
+ };
+ static gen_helper_gvec_3 * const ne_fn[4] = {
+ gen_helper_gvec_ne8, gen_helper_gvec_ne16,
+ gen_helper_gvec_ne32, gen_helper_gvec_ne64
+ };
+ static gen_helper_gvec_3 * const lt_fn[4] = {
+ gen_helper_gvec_lt8, gen_helper_gvec_lt16,
+ gen_helper_gvec_lt32, gen_helper_gvec_lt64
+ };
+ static gen_helper_gvec_3 * const le_fn[4] = {
+ gen_helper_gvec_le8, gen_helper_gvec_le16,
+ gen_helper_gvec_le32, gen_helper_gvec_le64
+ };
+ static gen_helper_gvec_3 * const ltu_fn[4] = {
+ gen_helper_gvec_ltu8, gen_helper_gvec_ltu16,
+ gen_helper_gvec_ltu32, gen_helper_gvec_ltu64
+ };
+ static gen_helper_gvec_3 * const leu_fn[4] = {
+ gen_helper_gvec_leu8, gen_helper_gvec_leu16,
+ gen_helper_gvec_leu32, gen_helper_gvec_leu64
+ };
+ gen_helper_gvec_3 *fn;
+ uint32_t tmp;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs);
+ check_overlap_3(dofs, aofs, bofs, maxsz);
+
+ if (cond == TCG_COND_NEVER || cond == TCG_COND_ALWAYS) {
+ tcg_gen_gvec_dup32i(dofs, oprsz, maxsz, -(cond == TCG_COND_ALWAYS));
+ return;
+ }
+
+ /* Quick check for sizes we won't support inline. */
+ if (oprsz > MAX_UNROLL * 32 || maxsz > MAX_UNROLL * 32) {
+ goto do_ool;
+ }
+
+ /* Recall that ARM SVE allows vector sizes that are not a power of 2.
+ Expand with successively smaller host vector sizes. The intent is
+ that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
+ /* ??? For maxsz > oprsz, the host may be able to use an op-sized
+ operation, zeroing the balance of the register. We can then
+ use a cl-sized store to implement the clearing without an extra
+ store operation. This is true for aarch64 and x86_64 hosts. */
+
+ if (TCG_TARGET_HAS_v256 && check_size_impl(oprsz, 32)
+ && tcg_can_emit_vec_op(INDEX_op_cmp_vec, TCG_TYPE_V256, vece)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_cmp_vec(vece, dofs, aofs, bofs, done, 32, TCG_TYPE_V256, cond);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (TCG_TARGET_HAS_v128 && check_size_impl(oprsz, 16)
+ && tcg_can_emit_vec_op(INDEX_op_cmp_vec, TCG_TYPE_V128, vece)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 16);
+ expand_cmp_vec(vece, dofs, aofs, bofs, done, 16, TCG_TYPE_V128, cond);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (check_size_impl(oprsz, 8)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 8);
+ if (TCG_TARGET_HAS_v64
+ && (TCG_TARGET_REG_BITS == 32 || vece != MO_64)
+ && tcg_can_emit_vec_op(INDEX_op_cmp_vec, TCG_TYPE_V64, vece)) {
+ expand_cmp_vec(vece, dofs, aofs, bofs, done, 8, TCG_TYPE_V64, cond);
+ } else if (vece == MO_64) {
+ expand_cmp_i64(dofs, aofs, bofs, done, cond);
+ } else {
+ done = 0;
+ }
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (vece == MO_32 && check_size_impl(oprsz, 4)) {
+ uint32_t done = QEMU_ALIGN_DOWN(oprsz, 4);
+ expand_cmp_i32(dofs, aofs, bofs, done, cond);
+ dofs += done;
+ aofs += done;
+ bofs += done;
+ oprsz -= done;
+ maxsz -= done;
+ }
+
+ if (oprsz == 0) {
+ if (maxsz != 0) {
+ expand_clr(dofs, maxsz);
+ }
+ return;
+ }
+
+ do_ool:
+ switch (cond) {
+ case TCG_COND_EQ:
+ fn = eq_fn[vece];
+ break;
+ case TCG_COND_NE:
+ fn = ne_fn[vece];
+ break;
+ case TCG_COND_GT:
+ tmp = aofs, aofs = bofs, bofs = tmp;
+ /* fallthru */
+ case TCG_COND_LT:
+ fn = lt_fn[vece];
+ break;
+ case TCG_COND_GE:
+ tmp = aofs, aofs = bofs, bofs = tmp;
+ /* fallthru */
+ case TCG_COND_LE:
+ fn = le_fn[vece];
+ break;
+ case TCG_COND_GTU:
+ tmp = aofs, aofs = bofs, bofs = tmp;
+ /* fallthru */
+ case TCG_COND_LTU:
+ fn = ltu_fn[vece];
+ break;
+ case TCG_COND_GEU:
+ tmp = aofs, aofs = bofs, bofs = tmp;
+ /* fallthru */
+ case TCG_COND_LEU:
+ fn = leu_fn[vece];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn);
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 502c5ba891..2c636ebbd6 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -480,3 +480,26 @@ void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
do_interleave(INDEX_op_trno_vec, vece, r, a, b);
}
+
+void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
+ TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGArg bi = temp_arg(bt);
+ TCGType type = rt->base_type;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
+ if (can > 0) {
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
+ }
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 4bde7d6afd..f35d4a1a47 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1392,6 +1392,7 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
+ case INDEX_op_cmp_vec:
return have_vec;
case INDEX_op_dup2_vec:
return have_vec && TCG_TARGET_REG_BITS == 32;
@@ -1791,6 +1792,7 @@ void tcg_dump_ops(TCGContext *s)
case INDEX_op_brcond_i64:
case INDEX_op_setcond_i64:
case INDEX_op_movcond_i64:
+ case INDEX_op_cmp_vec:
if (op->args[k] < ARRAY_SIZE(cond_name)
&& cond_name[op->args[k]]) {
col += qemu_log(",%s", cond_name[op->args[k++]]);
diff --git a/tcg/README b/tcg/README
index 75db47922d..18b6bbd8f1 100644
--- a/tcg/README
+++ b/tcg/README
@@ -630,6 +630,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
v0[2i + 1] = v2[2i + part];
}
+* cmp_vec v0, v1, v2, cond
+
+ Compare vectors by element, storing -1 for true and 0 for false.
+
*********
Note 1: Some shortcuts are defined when the last operand is known to be
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 19/26] target/arm: Use vector infrastructure for aa64 compares
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (17 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 18/26] tcg: Add generic vector ops for comparisons Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 20/26] tcg/i386: Add vector operations/expansions for shift/cmp/interleave Richard Henderson
` (11 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 96 ++++++++++++++++++++++++++++++----------------
1 file changed, 62 insertions(+), 34 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c47faa5633..1ea7e37b03 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7115,6 +7115,28 @@ static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
}
}
+/* CMTST : test is "if (X & Y != 0)". */
+static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_and_i32(d, a, b);
+ tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0);
+ tcg_gen_neg_i32(d, d);
+}
+
+static void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_and_i64(d, a, b);
+ tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0);
+ tcg_gen_neg_i64(d, d);
+}
+
+static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_and_vec(vece, d, a, b);
+ tcg_gen_dupi_vec(vece, a, 0);
+ tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a);
+}
+
static void handle_3same_64(DisasContext *s, int opcode, bool u,
TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
{
@@ -7158,10 +7180,7 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u,
cond = TCG_COND_EQ;
goto do_cmop;
}
- /* CMTST : test is "if (X & Y != 0)". */
- tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
- tcg_gen_setcondi_i64(TCG_COND_NE, tcg_rd, tcg_rd, 0);
- tcg_gen_neg_i64(tcg_rd, tcg_rd);
+ gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm);
break;
case 0x8: /* SSHL, USHL */
if (u) {
@@ -9684,6 +9703,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
int rd = extract32(insn, 0, 5);
int pass;
GVecGen3Fn *gvec_op;
+ TCGCond cond;
switch (opcode) {
case 0x13: /* MUL, PMUL */
@@ -9731,6 +9751,44 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s));
return;
+ case 0x11:
+ if (u) { /* CMEQ */
+ cond = TCG_COND_EQ;
+ goto do_gvec_cmp;
+ } else { /* CMTST */
+ static const GVecGen3 cmtst_op[4] = {
+ { .fni4 = gen_helper_neon_tst_u8,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_8 },
+ { .fni4 = gen_helper_neon_tst_u16,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_16 },
+ { .fni4 = gen_cmtst_i32,
+ .fniv = gen_cmtst_vec,
+ .vece = MO_32 },
+ { .fni8 = gen_cmtst_i64,
+ .fniv = gen_cmtst_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+ tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s),
+ &cmtst_op[size]);
+ }
+ return;
+ case 0x06: /* CMGT, CMHI */
+ cond = u ? TCG_COND_GTU : TCG_COND_GT;
+ goto do_gvec_cmp;
+ case 0x07: /* CMGE, CMHS */
+ cond = u ? TCG_COND_GEU : TCG_COND_GE;
+ do_gvec_cmp:
+ tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
}
if (size == 3) {
@@ -9813,26 +9871,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genenvfn = fns[size][u];
break;
}
- case 0x6: /* CMGT, CMHI */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_u8 },
- { gen_helper_neon_cgt_s16, gen_helper_neon_cgt_u16 },
- { gen_helper_neon_cgt_s32, gen_helper_neon_cgt_u32 },
- };
- genfn = fns[size][u];
- break;
- }
- case 0x7: /* CMGE, CMHS */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_cge_s8, gen_helper_neon_cge_u8 },
- { gen_helper_neon_cge_s16, gen_helper_neon_cge_u16 },
- { gen_helper_neon_cge_s32, gen_helper_neon_cge_u32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x8: /* SSHL, USHL */
{
static NeonGenTwoOpFn * const fns[3][2] = {
@@ -9905,16 +9943,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][u];
break;
}
- case 0x11: /* CMTST, CMEQ */
- {
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_tst_u8, gen_helper_neon_ceq_u8 },
- { gen_helper_neon_tst_u16, gen_helper_neon_ceq_u16 },
- { gen_helper_neon_tst_u32, gen_helper_neon_ceq_u32 },
- };
- genfn = fns[size][u];
- break;
- }
case 0x13: /* MUL, PMUL */
if (u) {
/* PMUL */
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 20/26] tcg/i386: Add vector operations/expansions for shift/cmp/interleave
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (18 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 19/26] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication Richard Henderson
` (10 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 6 +-
tcg/i386/tcg-target.opc.h | 7 +
tcg/i386/tcg-target.inc.c | 595 +++++++++++++++++++++++++++++++++++++++++++++-
3 files changed, 598 insertions(+), 10 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 46c4dca7be..60d3684750 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -177,13 +177,13 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
-#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_zip_vec 0
+#define TCG_TARGET_HAS_zip_vec 1
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
-#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h
index 4816a6c3d4..77125ef818 100644
--- a/tcg/i386/tcg-target.opc.h
+++ b/tcg/i386/tcg-target.opc.h
@@ -1,3 +1,10 @@
/* Target-specific opcodes for host vector expansion. These will be
emitted by tcg_expand_vec_op. For those familiar with GCC internals,
consider these to be UNSPEC with names. */
+
+DEF(x86_shufps_vec, 1, 2, 1, IMPLVEC)
+DEF(x86_vpblendvb_vec, 1, 3, 0, IMPLVEC)
+DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
+DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
+DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
+DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 062cf16607..694d9e5cb5 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -324,6 +324,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
# define P_REXB_RM 0
# define P_GS 0
#endif
+#define P_EXT3A 0x10000 /* 0x0f 0x3a opcode prefix */
#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */
#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */
#define P_VEXL 0x80000 /* Set VEX.L = 1 */
@@ -333,6 +334,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_ARITH_GvEv (0x03) /* ... plus (ARITH_FOO << 3) */
#define OPC_ANDN (0xf2 | P_EXT38)
#define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
+#define OPC_BLENDPS (0x0c | P_EXT3A | P_DATA16)
#define OPC_BSF (0xbc | P_EXT)
#define OPC_BSR (0xbd | P_EXT)
#define OPC_BSWAP (0xc8 | P_EXT)
@@ -372,15 +374,33 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_MOVSLQ (0x63 | P_REXW)
#define OPC_MOVZBL (0xb6 | P_EXT)
#define OPC_MOVZWL (0xb7 | P_EXT)
+#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16)
+#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16)
+#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16)
+#define OPC_PACKUSWB (0x67 | P_EXT | P_DATA16)
#define OPC_PADDB (0xfc | P_EXT | P_DATA16)
#define OPC_PADDW (0xfd | P_EXT | P_DATA16)
#define OPC_PADDD (0xfe | P_EXT | P_DATA16)
#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16)
#define OPC_PAND (0xdb | P_EXT | P_DATA16)
#define OPC_PANDN (0xdf | P_EXT | P_DATA16)
+#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16)
#define OPC_PCMPEQB (0x74 | P_EXT | P_DATA16)
+#define OPC_PCMPEQW (0x75 | P_EXT | P_DATA16)
+#define OPC_PCMPEQD (0x76 | P_EXT | P_DATA16)
+#define OPC_PCMPEQQ (0x29 | P_EXT38 | P_DATA16)
+#define OPC_PCMPGTB (0x64 | P_EXT | P_DATA16)
+#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16)
+#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16)
+#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16)
#define OPC_POR (0xeb | P_EXT | P_DATA16)
+#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16)
#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16)
+#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2)
+#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3)
+#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
#define OPC_PSUBB (0xf8 | P_EXT | P_DATA16)
#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
@@ -389,6 +409,10 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16)
#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16)
#define OPC_PUNPCKLQDQ (0x6c | P_EXT | P_DATA16)
+#define OPC_PUNPCKHBW (0x68 | P_EXT | P_DATA16)
+#define OPC_PUNPCKHWD (0x69 | P_EXT | P_DATA16)
+#define OPC_PUNPCKHDQ (0x6a | P_EXT | P_DATA16)
+#define OPC_PUNPCKHQDQ (0x6d | P_EXT | P_DATA16)
#define OPC_PXOR (0xef | P_EXT | P_DATA16)
#define OPC_POP_r32 (0x58)
#define OPC_POPCNT (0xb8 | P_EXT | P_SIMDF3)
@@ -401,19 +425,26 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_SHIFT_Ib (0xc1)
#define OPC_SHIFT_cl (0xd3)
#define OPC_SARX (0xf7 | P_EXT38 | P_SIMDF3)
+#define OPC_SHUFPS (0xc6 | P_EXT)
#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
#define OPC_TESTL (0x85)
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
+#define OPC_UD2 (0x0b | P_EXT)
+#define OPC_VPBLENDD (0x02 | P_EXT3A | P_DATA16)
+#define OPC_VPBLENDVB (0x4c | P_EXT3A | P_DATA16)
#define OPC_VPBROADCASTB (0x78 | P_EXT38 | P_DATA16)
#define OPC_VPBROADCASTW (0x79 | P_EXT38 | P_DATA16)
#define OPC_VPBROADCASTD (0x58 | P_EXT38 | P_DATA16)
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
+#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_REXW)
+#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
#define OPC_GRP3_Ev (0xf7)
#define OPC_GRP5 (0xff)
+#define OPC_GRP14 (0x73 | P_EXT | P_DATA16)
/* Group 1 opcode extensions for 0x80-0x83.
These are also used as modifiers for OPC_ARITH. */
@@ -519,10 +550,12 @@ static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x)
tcg_out8(s, (uint8_t)(rex | 0x40));
}
- if (opc & (P_EXT | P_EXT38)) {
+ if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
tcg_out8(s, 0x0f);
if (opc & P_EXT38) {
tcg_out8(s, 0x38);
+ } else if (opc & P_EXT3A) {
+ tcg_out8(s, 0x3a);
}
}
@@ -539,10 +572,12 @@ static void tcg_out_opc(TCGContext *s, int opc)
} else if (opc & P_SIMDF2) {
tcg_out8(s, 0xf2);
}
- if (opc & (P_EXT | P_EXT38)) {
+ if (opc & (P_EXT | P_EXT38 | P_EXT3A)) {
tcg_out8(s, 0x0f);
if (opc & P_EXT38) {
tcg_out8(s, 0x38);
+ } else if (opc & P_EXT3A) {
+ tcg_out8(s, 0x3a);
}
}
tcg_out8(s, opc);
@@ -566,7 +601,7 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
/* Use the two byte form if possible, which cannot encode
VEX.W, VEX.B, VEX.X, or an m-mmmm field other than P_EXT. */
- if ((opc & (P_EXT | P_EXT38 | P_REXW)) == P_EXT
+ if ((opc & (P_EXT | P_EXT38 | P_EXT3A | P_REXW)) == P_EXT
&& ((rm | index) & 8) == 0) {
/* Two byte VEX prefix. */
tcg_out8(s, 0xc5);
@@ -577,7 +612,9 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
tcg_out8(s, 0xc4);
/* VEX.m-mmmm */
- if (opc & P_EXT38) {
+ if (opc & P_EXT3A) {
+ tmp = 3;
+ } else if (opc & P_EXT38) {
tmp = 2;
} else if (opc & P_EXT) {
tmp = 1;
@@ -2638,9 +2675,24 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const sub_insn[4] = {
OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
};
+ static int const shift_imm_insn[4] = {
+ OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib
+ };
+ static int const cmpeq_insn[4] = {
+ OPC_PCMPEQB, OPC_PCMPEQW, OPC_PCMPEQD, OPC_PCMPEQQ
+ };
+ static int const cmpgt_insn[4] = {
+ OPC_PCMPGTB, OPC_PCMPGTW, OPC_PCMPGTD, OPC_PCMPGTQ
+ };
+ static int const punpckl_insn[4] = {
+ OPC_PUNPCKLBW, OPC_PUNPCKLWD, OPC_PUNPCKLDQ, OPC_PUNPCKLQDQ
+ };
+ static int const punpckh_insn[4] = {
+ OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ
+ };
TCGType type = vecl + TCG_TYPE_V64;
- int insn;
+ int insn, sub;
TCGArg a0, a1, a2;
a0 = args[0];
@@ -2662,6 +2714,31 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
goto gen_simd;
case INDEX_op_xor_vec:
insn = OPC_PXOR;
+ goto gen_simd;
+ case INDEX_op_zipl_vec:
+ insn = punpckl_insn[vece];
+ goto gen_simd;
+ case INDEX_op_ziph_vec:
+ insn = punpckh_insn[vece];
+ goto gen_simd;
+ case INDEX_op_x86_packss_vec:
+ if (vece == MO_8) {
+ insn = OPC_PACKSSWB;
+ } else if (vece == MO_16) {
+ insn = OPC_PACKSSDW;
+ } else {
+ g_assert_not_reached();
+ }
+ goto gen_simd;
+ case INDEX_op_x86_packus_vec:
+ if (vece == MO_8) {
+ insn = OPC_PACKUSWB;
+ } else if (vece == MO_16) {
+ insn = OPC_PACKUSDW;
+ } else {
+ g_assert_not_reached();
+ }
+ goto gen_simd;
gen_simd:
if (type == TCG_TYPE_V256) {
insn |= P_VEXL;
@@ -2669,6 +2746,17 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_vex_modrm(s, insn, a0, a1, a2);
break;
+ case INDEX_op_cmp_vec:
+ sub = args[3];
+ if (sub == TCG_COND_EQ) {
+ insn = cmpeq_insn[vece];
+ } else if (sub == TCG_COND_GT) {
+ insn = cmpgt_insn[vece];
+ } else {
+ g_assert_not_reached();
+ }
+ goto gen_simd;
+
case INDEX_op_andc_vec:
insn = OPC_PANDN;
if (type == TCG_TYPE_V256) {
@@ -2677,6 +2765,25 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_vex_modrm(s, insn, a0, a2, a1);
break;
+ case INDEX_op_shli_vec:
+ sub = 6;
+ goto gen_shift;
+ case INDEX_op_shri_vec:
+ sub = 2;
+ goto gen_shift;
+ case INDEX_op_sari_vec:
+ tcg_debug_assert(vece != MO_64);
+ sub = 4;
+ gen_shift:
+ tcg_debug_assert(vece != MO_8);
+ insn = shift_imm_insn[vece];
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, sub, a0, a1);
+ tcg_out8(s, a2);
+ break;
+
case INDEX_op_ld_vec:
tcg_out_ld(s, type, a0, a1, a2);
break;
@@ -2690,6 +2797,42 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dup_vec(s, type, vece, a0, a1);
break;
+ case INDEX_op_x86_shufps_vec:
+ insn = OPC_SHUFPS;
+ sub = args[3];
+ goto gen_simd_imm8;
+ case INDEX_op_x86_blend_vec:
+ if (vece == MO_16) {
+ insn = OPC_PBLENDW;
+ } else if (vece == MO_32) {
+ insn = (have_avx2 ? OPC_VPBLENDD : OPC_BLENDPS);
+ } else {
+ g_assert_not_reached();
+ }
+ sub = args[3];
+ goto gen_simd_imm8;
+ gen_simd_imm8:
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ tcg_out8(s, sub);
+ break;
+
+ case INDEX_op_x86_vpblendvb_vec:
+ insn = OPC_VPBLENDVB;
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, a1, a2);
+ tcg_out8(s, args[3] << 4);
+ break;
+
+ case INDEX_op_x86_psrldq_vec:
+ tcg_out_vex_modrm(s, OPC_GRP14, 3, a0, a1);
+ tcg_out8(s, a2);
+ break;
+
default:
g_assert_not_reached();
}
@@ -2720,6 +2863,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
= { .args_ct_str = { "L", "L", "L", "L" } };
static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
+ static const TCGTargetOpDef x_x_x_x
+ = { .args_ct_str = { "x", "x", "x", "x" } };
static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
switch (op) {
@@ -2932,9 +3077,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ case INDEX_op_x86_shufps_vec:
+ case INDEX_op_x86_blend_vec:
+ case INDEX_op_x86_packss_vec:
+ case INDEX_op_x86_packus_vec:
return &x_x_x;
case INDEX_op_dup_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_x86_psrldq_vec:
return &x_x;
+ case INDEX_op_x86_vpblendvb_vec:
+ return &x_x_x_x;
default:
break;
@@ -2951,16 +3109,439 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
- return true;
+ return 1;
+ case INDEX_op_cmp_vec:
+ return -1;
+
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ /* We must expand the operation for MO_8. */
+ return vece == MO_8 ? -1 : 1;
+
+ case INDEX_op_sari_vec:
+ /* We must expand the operation for MO_8. */
+ if (vece == MO_8) {
+ return -1;
+ }
+ /* We can emulate this for MO_64, but it does not pay off
+ unless we're producing at least 4 values. */
+ if (vece == MO_64) {
+ return type >= TCG_TYPE_V256 ? -1 : 0;
+ }
+ return 1;
+
+ case INDEX_op_zipl_vec:
+ /* We could support v256, but with 3 insns per opcode.
+ It is better to expand with v128 instead. */
+ return type <= TCG_TYPE_V128;
+ case INDEX_op_ziph_vec:
+ if (type == TCG_TYPE_V64) {
+ return -1;
+ }
+ return type == TCG_TYPE_V128;
+
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ /* ??? Not implemented for V256. */
+ return -(type <= TCG_TYPE_V128);
default:
- return false;
+ return 0;
}
}
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
+ va_list va;
+ TCGArg a1, a2;
+ TCGv_vec v0, v1, v2, t1, t2;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+
+ switch (opc) {
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ tcg_debug_assert(vece == MO_8);
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ /* Unpack to W, shift, and repack. Tricky bits:
+ (1) Use punpck*bw x,x to produce DDCCBBAA,
+ i.e. duplicate in other half of the 16-bit lane.
+ (2) For right-shift, add 8 so that the high half of
+ the lane becomes zero. For left-shift, we must
+ shift up and down again.
+ (3) Step 2 leaves high half zero such that PACKUSWB
+ (pack with unsigned saturation) does not modify
+ the quantity. */
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_zipl_vec, type, MO_8, tcgv_vec_arg(t1), a1, a1);
+ vec_gen_3(INDEX_op_ziph_vec, type, MO_8, tcgv_vec_arg(t2), a1, a1);
+ if (opc == INDEX_op_shri_vec) {
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
+ } else {
+ vec_gen_3(INDEX_op_shli_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), 8);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), 8);
+ }
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
+ case INDEX_op_sari_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ if (vece == MO_8) {
+ /* Unpack to W, shift, and repack, as above. */
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_zipl_vec, type, MO_8, tcgv_vec_arg(t1), a1, a1);
+ vec_gen_3(INDEX_op_ziph_vec, type, MO_8, tcgv_vec_arg(t2), a1, a1);
+ vec_gen_3(INDEX_op_sari_vec, type, MO_16,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), a2 + 8);
+ vec_gen_3(INDEX_op_sari_vec, type, MO_16,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2 + 8);
+ vec_gen_3(INDEX_op_x86_packss_vec, type, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ }
+ tcg_debug_assert(vece == MO_64);
+ /* MO_64: If the shift is <= 32, we can emulate the sign extend by
+ performing an arithmetic 32-bit shift and overwriting the high
+ half of the result (note that the ISA says shift of 32 is valid). */
+ if (a2 <= 32) {
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_sari_vec, type, MO_32, tcgv_vec_arg(t1), a1, a2);
+ vec_gen_3(INDEX_op_sari_vec, type, MO_64, a0, a1, a2);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ a0, a0, tcgv_vec_arg(t1), 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ }
+ /* Otherwise we will need to use a compare vs 0 to produce the
+ sign-extend, shift and merge. */
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_const_zeros_vec(type);
+ vec_gen_4(INDEX_op_cmp_vec, type, MO_64,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2), a1, TCG_COND_GT);
+ tcg_temp_free_vec(t2);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_64, a0, a1, a2);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_64,
+ tcgv_vec_arg(t1), tcgv_vec_arg(t1), 64 - a2);
+ vec_gen_3(INDEX_op_or_vec, type, MO_64, a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+
+ case INDEX_op_ziph_vec:
+ tcg_debug_assert(type == TCG_TYPE_V64);
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, vece, a0, a1, a2);
+ vec_gen_3(INDEX_op_x86_psrldq_vec, TCG_TYPE_V128, MO_64, a0, a0, 8);
+ break;
+
+ case INDEX_op_uzpe_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ v1 = temp_tcgv_vec(arg_temp(a1));
+ v2 = temp_tcgv_vec(arg_temp(a2));
+
+ if (type == TCG_TYPE_V128) {
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_dup16i_vec(t2, 0x00ff);
+ tcg_gen_and_vec(MO_16, t1, v2, t2);
+ tcg_gen_and_vec(MO_16, v0, v1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_dup32i_vec(t2, 0x0000ffff);
+ tcg_gen_and_vec(MO_32, t1, v2, t2);
+ tcg_gen_and_vec(MO_32, v0, v1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_16,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_32:
+ vec_gen_4(INDEX_op_x86_shufps_vec, type, MO_32,
+ a0, a1, a2, 0x88);
+ break;
+ case MO_64:
+ tcg_gen_zipl_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ tcg_debug_assert(type == TCG_TYPE_V64);
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup16i_vec(t2, 0x00ff);
+ tcg_gen_and_vec(MO_16, t1, t1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup32i_vec(t2, 0x0000ffff);
+ tcg_gen_and_vec(MO_32, t1, t1, t2);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_16,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_32:
+ tcg_gen_zipl_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ break;
+
+ case INDEX_op_uzpo_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ v1 = temp_tcgv_vec(arg_temp(a1));
+ v2 = temp_tcgv_vec(arg_temp(a2));
+
+ if (type == TCG_TYPE_V128) {
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_shri_vec(MO_16, t1, v2, 8);
+ tcg_gen_shri_vec(MO_16, v0, v1, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_8,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ tcg_gen_shri_vec(MO_32, t1, v2, 16);
+ tcg_gen_shri_vec(MO_32, v0, v1, 16);
+ vec_gen_3(INDEX_op_x86_packus_vec, type, MO_16,
+ a0, a0, tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ vec_gen_4(INDEX_op_x86_shufps_vec, type, MO_32,
+ a0, a1, a2, 0xdd);
+ break;
+ case MO_64:
+ tcg_gen_ziph_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ } else {
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_64,
+ tcgv_vec_arg(t1), a1, a2);
+ tcg_gen_shri_vec(MO_32, t1, t1, 16);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_16,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ tcg_gen_ziph_vec(vece, v0, v1, v2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ }
+ break;
+
+ case INDEX_op_trne_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_16,
+ tcgv_vec_arg(t1), a2, 8);
+ tcg_gen_dup16i_vec(t2, 0xff00);
+ vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, MO_8,
+ a0, a1, tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_32,
+ tcgv_vec_arg(t1), a2, 16);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_16,
+ a0, a1, tcgv_vec_arg(t1), 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shli_vec, type, MO_64,
+ tcgv_vec_arg(t1), a2, 32);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ a0, a1, tcgv_vec_arg(t1), 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_64:
+ vec_gen_3(INDEX_op_zipl_vec, type, MO_64, a0, a1, a2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_trno_vec:
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ switch (vece) {
+ case MO_8:
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_16,
+ tcgv_vec_arg(t1), a1, 8);
+ tcg_gen_dup16i_vec(t2, 0xff00);
+ vec_gen_4(INDEX_op_x86_vpblendvb_vec, type, MO_8,
+ a0, tcgv_vec_arg(t1), a2, tcgv_vec_arg(t2));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+ case MO_16:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_32,
+ tcgv_vec_arg(t1), a1, 16);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_16,
+ a0, tcgv_vec_arg(t1), a2, 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_32:
+ t1 = tcg_temp_new_vec(type);
+ vec_gen_3(INDEX_op_shri_vec, type, MO_64,
+ tcgv_vec_arg(t1), a1, 32);
+ vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32,
+ a0, tcgv_vec_arg(t1), a2, 0xaa);
+ tcg_temp_free_vec(t1);
+ break;
+ case MO_64:
+ vec_gen_3(INDEX_op_ziph_vec, type, MO_64, a0, a1, a2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_cmp_vec:
+ {
+ enum {
+ NEED_SWAP = 1,
+ NEED_INV = 2,
+ NEED_BIAS = 4
+ };
+ static const uint8_t fixups[16] = {
+ [0 ... 15] = -1,
+ [TCG_COND_EQ] = 0,
+ [TCG_COND_NE] = NEED_INV,
+ [TCG_COND_GT] = 0,
+ [TCG_COND_LT] = NEED_SWAP,
+ [TCG_COND_LE] = NEED_INV,
+ [TCG_COND_GE] = NEED_SWAP | NEED_INV,
+ [TCG_COND_GTU] = NEED_BIAS,
+ [TCG_COND_LTU] = NEED_BIAS | NEED_SWAP,
+ [TCG_COND_LEU] = NEED_BIAS | NEED_INV,
+ [TCG_COND_GEU] = NEED_BIAS | NEED_SWAP | NEED_INV,
+ };
+
+ TCGCond cond;
+ uint8_t fixup;
+
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ cond = va_arg(va, TCGArg);
+ fixup = fixups[cond & 15];
+ tcg_debug_assert(fixup != 0xff);
+
+ if (fixup & NEED_INV) {
+ cond = tcg_invert_cond(cond);
+ }
+ if (fixup & NEED_SWAP) {
+ TCGArg t;
+ t = a1, a1 = a2, a2 = t;
+ cond = tcg_swap_cond(cond);
+ }
+
+ t1 = t2 = NULL;
+ if (fixup & NEED_BIAS) {
+ t1 = tcg_temp_new_vec(type);
+ t2 = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
+ tcg_gen_sub_vec(vece, t1, temp_tcgv_vec(arg_temp(a1)), t2);
+ tcg_gen_sub_vec(vece, t2, temp_tcgv_vec(arg_temp(a2)), t2);
+ a1 = tcgv_vec_arg(t1);
+ a2 = tcgv_vec_arg(t2);
+ cond = tcg_signed_cond(cond);
+ }
+
+ tcg_debug_assert(cond == TCG_COND_EQ || cond == TCG_COND_GT);
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, a0, a1, a2, cond);
+
+ if (fixup & NEED_BIAS) {
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ }
+ if (fixup & NEED_INV) {
+ tcg_gen_not_vec(vece, v0, v0);
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ va_end(va);
}
static const int tcg_target_callee_save_regs[] = {
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (19 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 20/26] tcg/i386: Add vector operations/expansions for shift/cmp/interleave Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-12-05 11:33 ` Kirill Batuzov
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 22/26] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
` (9 subsequent siblings)
30 siblings, 1 reply; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 5 +++++
tcg/i386/tcg-target.h | 1 +
tcg/tcg-op-gvec.h | 2 ++
tcg/tcg-op.h | 1 +
tcg/tcg-opc.h | 1 +
tcg/tcg.h | 1 +
accel/tcg/tcg-runtime-gvec.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-gvec.c | 29 +++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 22 ++++++++++++++++++++++
tcg/tcg.c | 2 ++
tcg/README | 4 ++++
11 files changed, 112 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index 28abf30d76..c4a2e6b215 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -152,6 +152,11 @@ DEF_HELPER_FLAGS_4(gvec_sub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_sub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(gvec_mul64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_3(gvec_neg8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 60d3684750..949d138c9d 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -184,6 +184,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
+#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index 308bdc13b4..ad5e22e1bf 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -134,6 +134,8 @@ void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, uint32_t clsz);
void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t clsz);
void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, uint32_t clsz);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index b4f73c6048..3296a7baa5 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -920,6 +920,7 @@ void tcg_gen_movi_v128(TCGv_vec, uint64_t, uint64_t);
void tcg_gen_movi_v256(TCGv_vec, uint64_t, uint64_t, uint64_t, uint64_t);
void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index d3fa014507..b21a30273c 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -220,6 +220,7 @@ DEF(st_vec, 0, 2, 1, IMPLVEC)
DEF(add_vec, 1, 2, 0, IMPLVEC)
DEF(sub_vec, 1, 2, 0, IMPLVEC)
+DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
DEF(and_vec, 1, 2, 0, IMPLVEC)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 96760dd2d6..a729e66b66 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -185,6 +185,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_mul_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index e0cde3216f..9406ccd769 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -141,6 +141,50 @@ void HELPER(gvec_sub64)(void *d, void *a, void *b, uint32_t desc)
clear_high(d, oprsz, desc);
}
+void HELPER(gvec_mul8)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec8)) {
+ *(vec8 *)(d + i) = *(vec8 *)(a + i) * *(vec8 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mul16)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec16)) {
+ *(vec16 *)(d + i) = *(vec16 *)(a + i) * *(vec16 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mul32)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec32)) {
+ *(vec32 *)(d + i) = *(vec32 *)(a + i) * *(vec32 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_mul64)(void *d, void *a, void *b, uint32_t desc)
+{
+ intptr_t oprsz = simd_oprsz(desc);
+ intptr_t i;
+
+ for (i = 0; i < oprsz; i += sizeof(vec64)) {
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) * *(vec64 *)(b + i);
+ }
+ clear_high(d, oprsz, desc);
+}
+
void HELPER(gvec_neg8)(void *d, void *a, uint32_t desc)
{
intptr_t oprsz = simd_oprsz(desc);
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 1cc28b459f..3f567f0027 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1026,6 +1026,35 @@ void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g[vece]);
}
+void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t opsz, uint32_t maxsz)
+{
+ static const GVecGen3 g[4] = {
+ { .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul8,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_8 },
+ { .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul16,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_16 },
+ { .fni4 = tcg_gen_mul_i32,
+ .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul32,
+ .opc = INDEX_op_mul_vec,
+ .vece = MO_32 },
+ { .fni8 = tcg_gen_mul_i64,
+ .fniv = tcg_gen_mul_vec,
+ .fno = gen_helper_gvec_mul64,
+ .opc = INDEX_op_mul_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .vece = MO_64 },
+ };
+
+ tcg_debug_assert(vece <= MO_64);
+ tcg_gen_gvec_3(dofs, aofs, bofs, opsz, maxsz, &g[vece]);
+}
+
/* Perform a vector negation using normal negation and a mask.
Compare gen_subv_mask above. */
static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 2c636ebbd6..160db2e26e 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -503,3 +503,25 @@ void tcg_gen_cmp_vec(TCGCond cond, unsigned vece,
tcg_expand_vec_op(INDEX_op_cmp_vec, type, vece, ri, ai, bi, cond);
}
}
+
+void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGTemp *bt = tcgv_vec_temp(b);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGArg bi = temp_arg(bt);
+ TCGType type = rt->base_type;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ tcg_debug_assert(bt->base_type == type);
+ can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
+ if (can > 0) {
+ vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(INDEX_op_mul_vec, type, vece, ri, ai, bi);
+ }
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f35d4a1a47..b0a7cb7d38 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1404,6 +1404,8 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
+ case INDEX_op_mul_vec:
+ return have_vec && TCG_TARGET_HAS_mul_vec;
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
diff --git a/tcg/README b/tcg/README
index 18b6bbd8f1..17695ff7f6 100644
--- a/tcg/README
+++ b/tcg/README
@@ -547,6 +547,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Similarly, v0 = v1 - v2.
+* mul_vec v0, v1, v2
+
+ Similarly, v0 = v1 * v2.
+
* neg_vec v0, v1
Similarly, v0 = -v1.
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication Richard Henderson
@ 2017-12-05 11:33 ` Kirill Batuzov
2017-12-08 21:36 ` Richard Henderson
0 siblings, 1 reply; 36+ messages in thread
From: Kirill Batuzov @ 2017-12-05 11:33 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Tue, 21 Nov 2017, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
> +{
> + TCGTemp *rt = tcgv_vec_temp(r);
> + TCGTemp *at = tcgv_vec_temp(a);
> + TCGTemp *bt = tcgv_vec_temp(b);
> + TCGArg ri = temp_arg(rt);
> + TCGArg ai = temp_arg(at);
> + TCGArg bi = temp_arg(bt);
> + TCGType type = rt->base_type;
> + int can;
> +
> + tcg_debug_assert(at->base_type == type);
> + tcg_debug_assert(bt->base_type == type);
> + can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
Should be INDEX_op_mul_vec in the line above.
> + if (can > 0) {
> + vec_gen_3(INDEX_op_mul_vec, type, vece, ri, ai, bi);
> + } else {
> + tcg_debug_assert(can < 0);
> + tcg_expand_vec_op(INDEX_op_mul_vec, type, vece, ri, ai, bi);
> + }
> +}
--
Kirill
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication
2017-12-05 11:33 ` Kirill Batuzov
@ 2017-12-08 21:36 ` Richard Henderson
0 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-12-08 21:36 UTC (permalink / raw)
To: Kirill Batuzov; +Cc: qemu-devel
On 12/05/2017 03:33 AM, Kirill Batuzov wrote:
> On Tue, 21 Nov 2017, Richard Henderson wrote:
>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>
>> +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
>> +{
>> + TCGTemp *rt = tcgv_vec_temp(r);
>> + TCGTemp *at = tcgv_vec_temp(a);
>> + TCGTemp *bt = tcgv_vec_temp(b);
>> + TCGArg ri = temp_arg(rt);
>> + TCGArg ai = temp_arg(at);
>> + TCGArg bi = temp_arg(bt);
>> + TCGType type = rt->base_type;
>> + int can;
>> +
>> + tcg_debug_assert(at->base_type == type);
>> + tcg_debug_assert(bt->base_type == type);
>> + can = tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece);
>
> Should be INDEX_op_mul_vec in the line above.
Fixed, thanks.
r~
^ permalink raw reply [flat|nested] 36+ messages in thread
* [Qemu-devel] [PATCH v6 22/26] target/arm: Use vector infrastructure for aa64 multiplies
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (20 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 23/26] tcg: Add generic vector ops for extension Richard Henderson
` (8 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 171 ++++++++++++++++++++++++++++++++++++---------
1 file changed, 138 insertions(+), 33 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1ea7e37b03..c47d9caa49 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -9691,6 +9691,66 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
}
}
+static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u8(a, a, b);
+ gen_helper_neon_add_u8(d, d, a);
+}
+
+static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u16(a, a, b);
+ gen_helper_neon_add_u16(d, d, a);
+}
+
+static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_mul_i32(a, a, b);
+ tcg_gen_add_i32(d, d, a);
+}
+
+static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_mul_i64(a, a, b);
+ tcg_gen_add_i64(d, d, a);
+}
+
+static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_mul_vec(vece, a, a, b);
+ tcg_gen_add_vec(vece, d, d, a);
+}
+
+static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u8(a, a, b);
+ gen_helper_neon_sub_u8(d, d, a);
+}
+
+static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ gen_helper_neon_mul_u16(a, a, b);
+ gen_helper_neon_sub_u16(d, d, a);
+}
+
+static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ tcg_gen_mul_i32(a, a, b);
+ tcg_gen_sub_i32(d, d, a);
+}
+
+static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
+{
+ tcg_gen_mul_i64(a, a, b);
+ tcg_gen_sub_i64(d, d, a);
+}
+
+static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
+{
+ tcg_gen_mul_vec(vece, a, a, b);
+ tcg_gen_sub_vec(vece, d, d, a);
+}
+
/* Integer op subgroup of C3.6.16. */
static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
{
@@ -9702,7 +9762,8 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
int pass;
- GVecGen3Fn *gvec_op;
+ GVecGen3Fn *gvec_fn;
+ const GVecGen3 *gvec_op;
TCGCond cond;
switch (opcode) {
@@ -9745,12 +9806,70 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
switch (opcode) {
case 0x10: /* ADD, SUB */
- gvec_op = u ? tcg_gen_gvec_sub : tcg_gen_gvec_add;
- gvec_op(size, vec_full_reg_offset(s, rd),
+ gvec_fn = u ? tcg_gen_gvec_sub : tcg_gen_gvec_add;
+ do_gvec:
+ gvec_fn(size, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm),
is_q ? 16 : 8, vec_full_reg_size(s));
return;
+ case 0x13: /* MUL, PMUL */
+ if (!u) { /* MUL */
+ gvec_fn = tcg_gen_gvec_mul;
+ goto do_gvec;
+ }
+ break;
+ case 0x12: /* MLA, MLS */
+ {
+ static const GVecGen3 mla_op[4] = {
+ { .fni4 = gen_mla8_i32,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_8 },
+ { .fni4 = gen_mla16_i32,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_16 },
+ { .fni4 = gen_mla32_i32,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_32 },
+ { .fni8 = gen_mla64_i64,
+ .fniv = gen_mla_vec,
+ .opc = INDEX_op_mul_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_64 },
+ };
+ static const GVecGen3 mls_op[4] = {
+ { .fni4 = gen_mls8_i32,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_8 },
+ { .fni4 = gen_mls16_i32,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_16 },
+ { .fni4 = gen_mls32_i32,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .load_dest = true,
+ .vece = MO_32 },
+ { .fni8 = gen_mls64_i64,
+ .fniv = gen_mls_vec,
+ .opc = INDEX_op_mul_vec,
+ .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .load_dest = true,
+ .vece = MO_64 },
+ };
+ gvec_op = (u ? &mls_op[size] : &mla_op[size]);
+ }
+ goto do_gvec_op;
case 0x11:
if (u) { /* CMEQ */
cond = TCG_COND_EQ;
@@ -9771,12 +9890,13 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};
- tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rn),
- vec_full_reg_offset(s, rm),
- is_q ? 16 : 8, vec_full_reg_size(s),
- &cmtst_op[size]);
+ gvec_op = &cmtst_op[size];
}
+ do_gvec_op:
+ tcg_gen_gvec_3(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ is_q ? 16 : 8, vec_full_reg_size(s), gvec_op);
return;
case 0x06: /* CMGT, CMHI */
cond = u ? TCG_COND_GTU : TCG_COND_GT;
@@ -9944,23 +10064,10 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
break;
}
case 0x13: /* MUL, PMUL */
- if (u) {
- /* PMUL */
- assert(size == 0);
- genfn = gen_helper_neon_mul_p8;
- break;
- }
- /* fall through : MUL */
- case 0x12: /* MLA, MLS */
- {
- static NeonGenTwoOpFn * const fns[3] = {
- gen_helper_neon_mul_u8,
- gen_helper_neon_mul_u16,
- tcg_gen_mul_i32,
- };
- genfn = fns[size];
+ assert(u); /* PMUL */
+ assert(size == 0);
+ genfn = gen_helper_neon_mul_p8;
break;
- }
case 0x16: /* SQDMULH, SQRDMULH */
{
static NeonGenTwoOpEnvFn * const fns[2][2] = {
@@ -9981,18 +10088,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn(tcg_res, tcg_op1, tcg_op2);
}
- if (opcode == 0xf || opcode == 0x12) {
- /* SABA, UABA, MLA, MLS: accumulating ops */
- static NeonGenTwoOpFn * const fns[3][2] = {
- { gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
- { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
- { tcg_gen_add_i32, tcg_gen_sub_i32 },
+ if (opcode == 0xf) {
+ /* SABA, UABA: accumulating ops */
+ static NeonGenTwoOpFn * const fns[3] = {
+ gen_helper_neon_add_u8,
+ gen_helper_neon_add_u16,
+ tcg_gen_add_i32,
};
- bool is_sub = (opcode == 0x12 && u); /* MLS */
- genfn = fns[size][is_sub];
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
- genfn(tcg_res, tcg_op1, tcg_res);
+ fns[size](tcg_res, tcg_op1, tcg_res);
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 23/26] tcg: Add generic vector ops for extension
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (21 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 22/26] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 24/26] target/arm: Use vector infrastructure for aa64 widening shifts Richard Henderson
` (7 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tcg-runtime.h | 8 +++
tcg/i386/tcg-target.h | 2 +
tcg/tcg-op-gvec.h | 9 +++
tcg/tcg-op.h | 5 ++
tcg/tcg-opc.h | 5 ++
tcg/tcg.h | 2 +
accel/tcg/tcg-runtime-gvec.c | 26 ++++++++
tcg/tcg-op-gvec.c | 138 +++++++++++++++++++++++++++++++++++++++++++
tcg/tcg-op-vec.c | 39 ++++++++++++
tcg/tcg.c | 6 ++
tcg/README | 13 ++++
11 files changed, 253 insertions(+)
diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
index c4a2e6b215..d1b3542946 100644
--- a/accel/tcg/tcg-runtime.h
+++ b/accel/tcg/tcg-runtime.h
@@ -199,6 +199,14 @@ DEF_HELPER_FLAGS_4(gvec_trn16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_trn64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_extu8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_extu16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_extu32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(gvec_exts8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_exts16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_exts32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 949d138c9d..fedc3449c1 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -185,6 +185,8 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_extl_vec 0
+#define TCG_TARGET_HAS_exth_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h
index ad5e22e1bf..188c3368bd 100644
--- a/tcg/tcg-op-gvec.h
+++ b/tcg/tcg-op-gvec.h
@@ -180,6 +180,15 @@ void tcg_gen_gvec_trne(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_trno(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t bofs, uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_extul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_extuh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_extsl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz);
+void tcg_gen_gvec_extsh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t opsz, uint32_t clsz);
+
void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
uint32_t aofs, uint32_t bofs,
uint32_t opsz, uint32_t clsz);
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 3296a7baa5..a722c400c2 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -940,6 +940,11 @@ void tcg_gen_uzpo_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trne_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_trno_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
+void tcg_gen_extul_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_extuh_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_extsl_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+void tcg_gen_extsh_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
+
void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
TCGv_vec a, TCGv_vec b);
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index b21a30273c..3dfd872a0f 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -249,6 +249,11 @@ DEF(uzpo_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_uzp_vec))
DEF(trne_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
DEF(trno_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_trn_vec))
+DEF(extul_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_extl_vec))
+DEF(extuh_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_exth_vec))
+DEF(extsl_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_extl_vec))
+DEF(extsh_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_exth_vec))
+
DEF(cmp_vec, 1, 2, 1, IMPLVEC)
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index a729e66b66..b3dae8bcde 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -186,6 +186,8 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_HAS_cmp_vec 0
#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_extl_vec 0
+#define TCG_TARGET_HAS_exth_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index 9406ccd769..ff26be0744 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -588,3 +588,29 @@ DO_CMP2(8)
DO_CMP2(16)
DO_CMP2(32)
DO_CMP2(64)
+
+#define DO_EXT(NAME, TYPE1, TYPE2) \
+void HELPER(NAME)(void *d, void *a, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc); \
+ intptr_t oprsz_2 = oprsz / 2; \
+ intptr_t i; \
+ /* We produce output faster than we consume input. \
+ Therefore we must be mindful of possible overlap. */ \
+ if (unlikely((a - d) < (uintptr_t)oprsz)) { \
+ void *a_new = alloca(oprsz_2); \
+ memcpy(a_new, a, oprsz_2); \
+ a = a_new; \
+ } \
+ for (i = 0; i < oprsz_2; i += sizeof(TYPE1)) { \
+ *(TYPE2 *)(d + 2 * i) = *(TYPE1 *)(a + i); \
+ } \
+ clear_high(d, oprsz, desc); \
+}
+
+DO_EXT(gvec_extu8, uint8_t, uint16_t)
+DO_EXT(gvec_extu16, uint16_t, uint32_t)
+DO_EXT(gvec_extu32, uint32_t, uint64_t)
+DO_EXT(gvec_exts8, int8_t, int16_t)
+DO_EXT(gvec_exts16, int16_t, int32_t)
+DO_EXT(gvec_exts32, int32_t, int64_t)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 3f567f0027..ad674693c5 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1870,3 +1870,141 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs,
}
tcg_gen_gvec_3_ool(dofs, aofs, bofs, oprsz, maxsz, 0, fn);
}
+
+static void do_ext(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz, bool high, bool is_sign)
+{
+ static gen_helper_gvec_2 * const extu_fn[3] = {
+ gen_helper_gvec_extu8, gen_helper_gvec_extu16, gen_helper_gvec_extu32
+ };
+ static gen_helper_gvec_2 * const exts_fn[3] = {
+ gen_helper_gvec_exts8, gen_helper_gvec_exts16, gen_helper_gvec_exts32
+ };
+
+ TCGType type;
+ uint32_t step, i, n;
+ TCGOpcode opc;
+
+ check_size_align(oprsz, maxsz, dofs | aofs);
+ check_overlap_2(dofs, aofs, oprsz);
+ tcg_debug_assert(vece < MO_64);
+
+ /* Quick check for sizes we won't support inline. */
+ if (oprsz > 4 * 32 || maxsz > MAX_UNROLL * 32) {
+ goto do_ool;
+ }
+
+ opc = is_sign ? (high ? INDEX_op_extsh_vec : INDEX_op_extsl_vec)
+ : (high ? INDEX_op_extuh_vec : INDEX_op_extul_vec);
+
+ /* Since these operations don't operate in lock-step lanes,
+ we must care for overlap. */
+ if (TCG_TARGET_HAS_v256 && oprsz % 32 == 0 && oprsz / 32 <= 8
+ && tcg_can_emit_vec_op(opc, TCG_TYPE_V256, vece)) {
+ type = TCG_TYPE_V256;
+ step = 32;
+ n = oprsz / 32;
+ } else if (TCG_TARGET_HAS_v128 && oprsz % 16 == 0 && oprsz / 16 <= 8
+ && tcg_can_emit_vec_op(opc, TCG_TYPE_V128, vece)) {
+ type = TCG_TYPE_V128;
+ step = 16;
+ n = oprsz / 16;
+ } else if (TCG_TARGET_HAS_v64 && oprsz % 8 == 0 && oprsz / 8 <= 8
+ && tcg_can_emit_vec_op(opc, TCG_TYPE_V64, vece)) {
+ type = TCG_TYPE_V64;
+ step = 8;
+ n = oprsz / 8;
+ } else {
+ goto do_ool;
+ }
+
+ if (n == 1) {
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+
+ tcg_gen_ld_vec(t1, cpu_env, aofs);
+ if (high) {
+ if (is_sign) {
+ tcg_gen_extsh_vec(vece, t1, t1);
+ } else {
+ tcg_gen_extuh_vec(vece, t1, t1);
+ }
+ } else {
+ if (is_sign) {
+ tcg_gen_extsl_vec(vece, t1, t1);
+ } else {
+ tcg_gen_extul_vec(vece, t1, t1);
+ }
+ }
+ tcg_gen_st_vec(t1, cpu_env, dofs);
+ tcg_temp_free_vec(t1);
+ } else {
+ TCGv_vec ta[4], tmp;
+
+ if (high) {
+ aofs += oprsz / 2;
+ }
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ ta[i] = tcg_temp_new_vec(type);
+ tcg_gen_ld_vec(ta[i], cpu_env, aofs + i * step);
+ }
+
+ tmp = tcg_temp_new_vec(type);
+ for (i = 0; i < n; ++i) {
+ if (i & 1) {
+ if (is_sign) {
+ tcg_gen_extsh_vec(vece, tmp, ta[i / 2]);
+ } else {
+ tcg_gen_extuh_vec(vece, tmp, ta[i / 2]);
+ }
+ } else {
+ if (is_sign) {
+ tcg_gen_extsl_vec(vece, tmp, ta[i / 2]);
+ } else {
+ tcg_gen_extul_vec(vece, tmp, ta[i / 2]);
+ }
+ }
+ tcg_gen_st_vec(tmp, cpu_env, dofs + i * step);
+ }
+ tcg_temp_free_vec(tmp);
+
+ for (i = 0; i < (n / 2 + n % 2); ++i) {
+ tcg_temp_free_vec(ta[i]);
+ }
+ }
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+ return;
+
+ do_ool:
+ if (high) {
+ aofs += oprsz / 2;
+ }
+ tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, 0,
+ is_sign ? exts_fn[vece] : extu_fn[vece]);
+}
+
+void tcg_gen_gvec_extul(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, false, false);
+}
+
+void tcg_gen_gvec_extuh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, true, false);
+}
+
+void tcg_gen_gvec_extsl(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, false, true);
+}
+
+void tcg_gen_gvec_extsh(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t oprsz, uint32_t maxsz)
+{
+ do_ext(vece, dofs, aofs, oprsz, maxsz, true, true);
+}
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 160db2e26e..c685bb985a 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -525,3 +525,42 @@ void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
tcg_expand_vec_op(INDEX_op_mul_vec, type, vece, ri, ai, bi);
}
}
+
+static void do_ext(TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ TCGTemp *rt = tcgv_vec_temp(r);
+ TCGTemp *at = tcgv_vec_temp(a);
+ TCGArg ri = temp_arg(rt);
+ TCGArg ai = temp_arg(at);
+ TCGType type = rt->base_type;
+ int can;
+
+ tcg_debug_assert(at->base_type == type);
+ can = tcg_can_emit_vec_op(opc, type, vece);
+ if (can > 0) {
+ vec_gen_2(opc, type, vece, ri, ai);
+ } else {
+ tcg_debug_assert(can < 0);
+ tcg_expand_vec_op(opc, type, vece, ri, ai);
+ }
+}
+
+void tcg_gen_extul_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extul_vec, vece, r, a);
+}
+
+void tcg_gen_extuh_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extuh_vec, vece, r, a);
+}
+
+void tcg_gen_extsl_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extsl_vec, vece, r, a);
+}
+
+void tcg_gen_extsh_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+ do_ext(INDEX_op_extsh_vec, vece, r, a);
+}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index b0a7cb7d38..0130c42994 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1427,6 +1427,12 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_trne_vec:
case INDEX_op_trno_vec:
return have_vec && TCG_TARGET_HAS_trn_vec;
+ case INDEX_op_extul_vec:
+ case INDEX_op_extsl_vec:
+ return have_vec && TCG_TARGET_HAS_extl_vec;
+ case INDEX_op_extuh_vec:
+ case INDEX_op_extsh_vec:
+ return have_vec && TCG_TARGET_HAS_exth_vec;
default:
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
diff --git a/tcg/README b/tcg/README
index 17695ff7f6..56c70764bc 100644
--- a/tcg/README
+++ b/tcg/README
@@ -634,6 +634,19 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
v0[2i + 1] = v2[2i + part];
}
+* extul_vec v0, v1
+
+ Extend unsigned the low VECL/VECE/2 elements of v1 into v0.
+
+* extuh_vec v0, v1
+
+ Similarly for the high VECL/VECE/2 elements.
+
+* extsl_vec v0, v1
+* extsh_vec v0, v1
+
+ Similarly with signed extension.
+
* cmp_vec v0, v1, v2, cond
Compare vectors by element, storing -1 for true and 0 for false.
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 24/26] target/arm: Use vector infrastructure for aa64 widening shifts
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (22 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 23/26] tcg: Add generic vector ops for extension Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 25/26] tcg/i386: Add vector operations/expansions for mul/extend Richard Henderson
` (6 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c47d9caa49..1f7e9c4e19 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -8705,12 +8705,7 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
int size = 32 - clz32(immh) - 1;
int immhb = immh << 3 | immb;
int shift = immhb - (8 << size);
- int dsize = 64;
- int esize = 8 << size;
- int elements = dsize/esize;
- TCGv_i64 tcg_rn = new_tmp_a64(s);
- TCGv_i64 tcg_rd = new_tmp_a64(s);
- int i;
+ GVecGen2Fn *gvec_fn;
if (size >= 3) {
unallocated_encoding(s);
@@ -8721,18 +8716,18 @@ static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
return;
}
- /* For the LL variants the store is larger than the load,
- * so if rd == rn we would overwrite parts of our input.
- * So load everything right now and use shifts in the main loop.
- */
- read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);
-
- for (i = 0; i < elements; i++) {
- tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);
- ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0);
- tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
- write_vec_element(s, tcg_rd, rd, i, size + 1);
+ if (is_u) {
+ gvec_fn = is_q ? tcg_gen_gvec_extuh : tcg_gen_gvec_extul;
+ } else {
+ gvec_fn = is_q ? tcg_gen_gvec_extsh : tcg_gen_gvec_extsl;
}
+ gvec_fn(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), 16, 16);
+
+ /* Perform the shift in the wider format. */
+ tcg_gen_gvec_shli(size + 1, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rd),
+ 16, vec_full_reg_size(s), shift);
}
/* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 25/26] tcg/i386: Add vector operations/expansions for mul/extend
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (23 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 24/26] target/arm: Use vector infrastructure for aa64 widening shifts Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 26/26] tcg/aarch64: Add vector operations Richard Henderson
` (5 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 4 +-
tcg/i386/tcg-target.opc.h | 1 +
tcg/i386/tcg-target.inc.c | 186 ++++++++++++++++++++++++++++++++++++++++++----
3 files changed, 174 insertions(+), 17 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index fedc3449c1..e77b95cc2c 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -184,8 +184,8 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_uzp_vec 0
#define TCG_TARGET_HAS_trn_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
-#define TCG_TARGET_HAS_mul_vec 0
-#define TCG_TARGET_HAS_extl_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_extl_vec 1
#define TCG_TARGET_HAS_exth_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h
index 77125ef818..5f05df65e0 100644
--- a/tcg/i386/tcg-target.opc.h
+++ b/tcg/i386/tcg-target.opc.h
@@ -8,3 +8,4 @@ DEF(x86_blend_vec, 1, 2, 1, IMPLVEC)
DEF(x86_packss_vec, 1, 2, 0, IMPLVEC)
DEF(x86_packus_vec, 1, 2, 0, IMPLVEC)
DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
+DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 694d9e5cb5..e61aeebf3e 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -393,6 +393,14 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_PCMPGTW (0x65 | P_EXT | P_DATA16)
#define OPC_PCMPGTD (0x66 | P_EXT | P_DATA16)
#define OPC_PCMPGTQ (0x37 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16)
+#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXBW (0x30 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXWD (0x33 | P_EXT38 | P_DATA16)
+#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16)
+#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16)
+#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16)
#define OPC_POR (0xeb | P_EXT | P_DATA16)
#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16)
#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16)
@@ -2675,6 +2683,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const sub_insn[4] = {
OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
};
+ static int const mul_insn[4] = {
+ OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
+ };
static int const shift_imm_insn[4] = {
OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib
};
@@ -2690,6 +2701,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const punpckh_insn[4] = {
OPC_PUNPCKHBW, OPC_PUNPCKHWD, OPC_PUNPCKHDQ, OPC_PUNPCKHQDQ
};
+ static int const packss_insn[4] = {
+ OPC_PACKSSWB, OPC_PACKSSDW, OPC_UD2, OPC_UD2
+ };
+ static int const packus_insn[4] = {
+ OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
+ };
+ static int const pmovsx_insn[3] = {
+ OPC_PMOVSXBW, OPC_PMOVSXWD, OPC_PMOVSXDQ
+ };
+ static int const pmovzx_insn[3] = {
+ OPC_PMOVZXBW, OPC_PMOVZXWD, OPC_PMOVZXDQ
+ };
TCGType type = vecl + TCG_TYPE_V64;
int insn, sub;
@@ -2706,6 +2729,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
insn = sub_insn[vece];
goto gen_simd;
+ case INDEX_op_mul_vec:
+ insn = mul_insn[vece];
+ goto gen_simd;
case INDEX_op_and_vec:
insn = OPC_PAND;
goto gen_simd;
@@ -2722,30 +2748,33 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = punpckh_insn[vece];
goto gen_simd;
case INDEX_op_x86_packss_vec:
- if (vece == MO_8) {
- insn = OPC_PACKSSWB;
- } else if (vece == MO_16) {
- insn = OPC_PACKSSDW;
- } else {
- g_assert_not_reached();
- }
+ insn = packss_insn[vece];
goto gen_simd;
case INDEX_op_x86_packus_vec:
- if (vece == MO_8) {
- insn = OPC_PACKUSWB;
- } else if (vece == MO_16) {
- insn = OPC_PACKUSDW;
- } else {
- g_assert_not_reached();
- }
+ insn = packus_insn[vece];
goto gen_simd;
gen_simd:
+ tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
insn |= P_VEXL;
}
tcg_out_vex_modrm(s, insn, a0, a1, a2);
break;
+ case INDEX_op_extsl_vec:
+ insn = pmovsx_insn[vece];
+ goto gen_simd2;
+ case INDEX_op_extul_vec:
+ insn = pmovzx_insn[vece];
+ goto gen_simd2;
+ gen_simd2:
+ tcg_debug_assert(vece < MO_64);
+ if (type == TCG_TYPE_V256) {
+ insn |= P_VEXL;
+ }
+ tcg_out_vex_modrm(s, insn, a0, 0, a1);
+ break;
+
case INDEX_op_cmp_vec:
sub = args[3];
if (sub == TCG_COND_EQ) {
@@ -2811,6 +2840,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
sub = args[3];
goto gen_simd_imm8;
+ case INDEX_op_x86_vperm2i128_vec:
+ insn = OPC_VPERM2I128;
+ sub = args[3];
+ goto gen_simd_imm8;
gen_simd_imm8:
if (type == TCG_TYPE_V256) {
insn |= P_VEXL;
@@ -3073,6 +3106,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
@@ -3084,11 +3118,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_x86_blend_vec:
case INDEX_op_x86_packss_vec:
case INDEX_op_x86_packus_vec:
+ case INDEX_op_x86_vperm2i128_vec:
return &x_x_x;
case INDEX_op_dup_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extul_vec:
case INDEX_op_x86_psrldq_vec:
return &x_x;
case INDEX_op_x86_vpblendvb_vec:
@@ -3109,8 +3146,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extul_vec:
return 1;
case INDEX_op_cmp_vec:
+ case INDEX_op_extsh_vec:
+ case INDEX_op_extuh_vec:
return -1;
case INDEX_op_shli_vec:
@@ -3130,6 +3171,16 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
}
return 1;
+ case INDEX_op_mul_vec:
+ if (vece == MO_8) {
+ /* We can expand the operation for MO_8. */
+ return -1;
+ }
+ if (vece == MO_64) {
+ return 0;
+ }
+ return 1;
+
case INDEX_op_zipl_vec:
/* We could support v256, but with 3 insns per opcode.
It is better to expand with v128 instead. */
@@ -3157,7 +3208,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
{
va_list va;
TCGArg a1, a2;
- TCGv_vec v0, v1, v2, t1, t2;
+ TCGv_vec v0, v1, v2, t1, t2, t3, t4;
va_start(va, a0);
v0 = temp_tcgv_vec(arg_temp(a0));
@@ -3248,6 +3299,91 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
tcg_temp_free_vec(t1);
break;
+ case INDEX_op_mul_vec:
+ tcg_debug_assert(vece == MO_8);
+ a1 = va_arg(va, TCGArg);
+ a2 = va_arg(va, TCGArg);
+ switch (type) {
+ case TCG_TYPE_V64:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup16i_vec(t2, 0);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t1), a1, tcgv_vec_arg(t2));
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t2), a2);
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ break;
+
+ case TCG_TYPE_V128:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t3 = tcg_temp_new_vec(TCG_TYPE_V128);
+ t4 = tcg_temp_new_vec(TCG_TYPE_V128);
+ tcg_gen_dup16i_vec(t4, 0);
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t1), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t4), a2);
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t3), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V128, MO_8,
+ tcgv_vec_arg(t4), tcgv_vec_arg(t4), a2);
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_mul_vec(MO_16, t3, t3, t4);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ tcg_gen_shri_vec(MO_16, t3, t3, 8);
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t3));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t4);
+ break;
+
+ case TCG_TYPE_V256:
+ t1 = tcg_temp_new_vec(TCG_TYPE_V256);
+ t2 = tcg_temp_new_vec(TCG_TYPE_V256);
+ t3 = tcg_temp_new_vec(TCG_TYPE_V256);
+ t4 = tcg_temp_new_vec(TCG_TYPE_V256);
+ tcg_gen_dup16i_vec(t4, 0);
+ /* a1: A[0-7] ... D[0-7]; a2: W[0-7] ... Z[0-7]
+ t1: extends of B[0-7], D[0-7]
+ t2: extends of X[0-7], Z[0-7]
+ t3: extends of A[0-7], C[0-7]
+ t4: extends of W[0-7], Y[0-7]. */
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t1), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_zipl_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t2), tcgv_vec_arg(t4), a2);
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t3), a1, tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_ziph_vec, TCG_TYPE_V256, MO_8,
+ tcgv_vec_arg(t4), tcgv_vec_arg(t4), a2);
+ /* t1: BX DZ; t2: AW CY. */
+ tcg_gen_mul_vec(MO_16, t1, t1, t2);
+ tcg_gen_mul_vec(MO_16, t3, t3, t4);
+ tcg_gen_shri_vec(MO_16, t1, t1, 8);
+ tcg_gen_shri_vec(MO_16, t3, t3, 8);
+ /* a0: AW BX CY DZ. */
+ vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V256, MO_8,
+ a0, tcgv_vec_arg(t1), tcgv_vec_arg(t3));
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t4);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
case INDEX_op_ziph_vec:
tcg_debug_assert(type == TCG_TYPE_V64);
a1 = va_arg(va, TCGArg);
@@ -3256,6 +3392,26 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
vec_gen_3(INDEX_op_x86_psrldq_vec, TCG_TYPE_V128, MO_64, a0, a0, 8);
break;
+ case INDEX_op_extsh_vec:
+ case INDEX_op_extuh_vec:
+ a1 = va_arg(va, TCGArg);
+ switch (type) {
+ case TCG_TYPE_V64:
+ vec_gen_3(INDEX_op_x86_psrldq_vec, type, MO_64, a0, a1, 4);
+ break;
+ case TCG_TYPE_V128:
+ vec_gen_3(INDEX_op_x86_psrldq_vec, type, MO_64, a0, a1, 8);
+ break;
+ case TCG_TYPE_V256:
+ vec_gen_4(INDEX_op_x86_vperm2i128_vec, type, 4, a0, a1, a1, 0x81);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ vec_gen_2(opc == INDEX_op_extsh_vec ? INDEX_op_extsl_vec
+ : INDEX_op_extul_vec, type, vece, a0, a0);
+ break;
+
case INDEX_op_uzpe_vec:
a1 = va_arg(va, TCGArg);
a2 = va_arg(va, TCGArg);
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* [Qemu-devel] [PATCH v6 26/26] tcg/aarch64: Add vector operations
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (24 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 25/26] tcg/i386: Add vector operations/expansions for mul/extend Richard Henderson
@ 2017-11-21 21:25 ` Richard Henderson
2017-11-21 22:10 ` [Qemu-devel] [PATCH v6 00/26] tcg: generic " no-reply
` (4 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: Richard Henderson @ 2017-11-21 21:25 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 30 +-
tcg/aarch64/tcg-target.opc.h | 3 +
tcg/aarch64/tcg-target.inc.c | 674 ++++++++++++++++++++++++++++++++++++++++---
3 files changed, 660 insertions(+), 47 deletions(-)
create mode 100644 tcg/aarch64/tcg-target.opc.h
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index c2525066ab..46434ecca4 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -31,13 +31,22 @@ typedef enum {
TCG_REG_SP = 31,
TCG_REG_XZR = 31,
+ TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
+ TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+
/* Aliases. */
TCG_REG_FP = TCG_REG_X29,
TCG_REG_LR = TCG_REG_X30,
TCG_AREG0 = TCG_REG_X19,
} TCGReg;
-#define TCG_TARGET_NB_REGS 32
+#define TCG_TARGET_NB_REGS 64
/* used for function call generation */
#define TCG_REG_CALL_STACK TCG_REG_SP
@@ -113,6 +122,25 @@ typedef enum {
#define TCG_TARGET_HAS_mulsh_i64 1
#define TCG_TARGET_HAS_direct_jump 1
+#define TCG_TARGET_HAS_v64 1
+#define TCG_TARGET_HAS_v128 1
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 1
+#define TCG_TARGET_HAS_orc_vec 1
+#define TCG_TARGET_HAS_not_vec 1
+#define TCG_TARGET_HAS_neg_vec 1
+#define TCG_TARGET_HAS_shi_vec 1
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_zip_vec 1
+#define TCG_TARGET_HAS_uzp_vec 1
+#define TCG_TARGET_HAS_trn_vec 1
+#define TCG_TARGET_HAS_cmp_vec 1
+#define TCG_TARGET_HAS_mul_vec 1
+#define TCG_TARGET_HAS_extl_vec 1
+#define TCG_TARGET_HAS_exth_vec 1
+
#define TCG_TARGET_DEFAULT_MO (0)
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h
new file mode 100644
index 0000000000..4816a6c3d4
--- /dev/null
+++ b/tcg/aarch64/tcg-target.opc.h
@@ -0,0 +1,3 @@
+/* Target-specific opcodes for host vector expansion. These will be
+ emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ consider these to be UNSPEC with names. */
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 150530f30e..b2ce818d7c 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -20,10 +20,15 @@ QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
#ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "%x0", "%x1", "%x2", "%x3", "%x4", "%x5", "%x6", "%x7",
- "%x8", "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15",
- "%x16", "%x17", "%x18", "%x19", "%x20", "%x21", "%x22", "%x23",
- "%x24", "%x25", "%x26", "%x27", "%x28", "%fp", "%x30", "%sp",
+ "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
+ "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
+ "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
+ "x24", "x25", "x26", "x27", "x28", "fp", "x30", "sp",
+
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "fp", "v30", "v31",
};
#endif /* CONFIG_DEBUG_TCG */
@@ -43,6 +48,14 @@ static const int tcg_target_reg_alloc_order[] = {
/* X19 reserved for AREG0 */
/* X29 reserved as fp */
/* X30 reserved as temporary */
+
+ TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ /* V8 - V15 are call-saved, and skipped. */
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
};
static const int tcg_target_call_iarg_regs[8] = {
@@ -54,6 +67,7 @@ static const int tcg_target_call_oarg_regs[1] = {
};
#define TCG_REG_TMP TCG_REG_X30
+#define TCG_VEC_TMP TCG_REG_V31
#ifndef CONFIG_SOFTMMU
/* Note that XZR cannot be encoded in the address base register slot,
@@ -119,9 +133,13 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
const char *ct_str, TCGType type)
{
switch (*ct_str++) {
- case 'r':
+ case 'r': /* general registers */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffffu;
+ ct->u.regs |= 0xffffffffu;
+ break;
+ case 'w': /* advsimd registers */
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs |= 0xffffffff00000000ull;
break;
case 'l': /* qemu_ld / qemu_st address, data_reg */
ct->ct |= TCG_CT_REG;
@@ -178,6 +196,98 @@ static inline bool is_limm(uint64_t val)
return (val & (val - 1)) == 0;
}
+static bool is_fimm(uint64_t v64, int *op, int *cmode, int *imm8)
+{
+ int i;
+
+ *op = 0;
+ if (v64 == (-1ull / 0xff) * (v64 & 0xff)) {
+ *cmode = 0xe;
+ *imm8 = v64 & 0xff;
+ return true;
+ }
+ if (v64 == (-1ull / 0xffff) * (v64 & 0xffff)) {
+ uint64_t v16 = v64 & 0xffff;
+
+ if (v16 == (v64 & 0xff)) {
+ *cmode = 0x8;
+ *imm8 = v64 & 0xff;
+ return true;
+ } else if (v16 == (v64 & 0xff00)) {
+ *cmode = 0xa;
+ *imm8 = v16 >> 8;
+ return true;
+ }
+ }
+ if (v64 == deposit64(v64, 32, 32, v64)) {
+ uint64_t v32 = (uint32_t)v64;
+
+ if (v32 == (v64 & 0xff)) {
+ *cmode = 0x0;
+ *imm8 = v64 & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff00)) {
+ *cmode = 0x2;
+ *imm8 = (v64 >> 8) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff0000)) {
+ *cmode = 0x4;
+ *imm8 = (v64 >> 16) & 0xff;
+ return true;
+ } else if (v32 == (v32 & 0xff000000)) {
+ *cmode = 0x6;
+ *imm8 = v32 >> 24;
+ return true;
+ } else if ((v32 & 0xffff00ff) == 0xff) {
+ *cmode = 0xc;
+ *imm8 = (v64 >> 8) & 0xff;
+ return true;
+ } else if ((v32 & 0xff00ffff) == 0xffff) {
+ *cmode = 0xd;
+ *imm8 = (v64 >> 16) & 0xff;
+ return true;
+ } else if (extract32(v32, 0, 19) == 0
+ && (extract32(v32, 25, 6) == 0x20
+ || extract32(v32, 25, 6) == 0x1f)) {
+ *cmode = 0xf;
+ *imm8 = (extract32(v32, 31, 1) << 7)
+ | (extract32(v32, 25, 1) << 6)
+ | extract32(v32, 19, 6);
+ return true;
+ }
+ }
+ if (extract64(v64, 0, 48) == 0
+ && (extract64(v64, 54, 9) == 0x100
+ || extract64(v64, 54, 9) == 0x0ff)) {
+ *cmode = 0xf;
+ *op = 1;
+ *imm8 = (extract64(v64, 63, 1) << 7)
+ | (extract64(v64, 54, 1) << 6)
+ | extract64(v64, 48, 6);
+ return true;
+ }
+ for (i = 0; i < 64; i += 8) {
+ uint64_t byte = extract64(v64, i, 8);
+ if (byte != 0 && byte != 0xff) {
+ break;
+ }
+ }
+ if (i == 64) {
+ *cmode = 0xe;
+ *op = 1;
+ *imm8 = (extract64(v64, 0, 1) << 0)
+ | (extract64(v64, 8, 1) << 1)
+ | (extract64(v64, 16, 1) << 2)
+ | (extract64(v64, 24, 1) << 3)
+ | (extract64(v64, 32, 1) << 4)
+ | (extract64(v64, 40, 1) << 5)
+ | (extract64(v64, 48, 1) << 6)
+ | (extract64(v64, 56, 1) << 7);
+ return true;
+ }
+ return false;
+}
+
static int tcg_target_const_match(tcg_target_long val, TCGType type,
const TCGArgConstraint *arg_ct)
{
@@ -271,6 +381,9 @@ typedef enum {
/* Load literal for loading the address at pc-relative offset */
I3305_LDR = 0x58000000,
+ I3305_LDR_v64 = 0x5c000000,
+ I3305_LDR_v128 = 0x9c000000,
+
/* Load/store register. Described here as 3.3.12, but the helper
that emits them can transform to 3.3.10 or 3.3.13. */
I3312_STRB = 0x38000000 | LDST_ST << 22 | MO_8 << 30,
@@ -290,6 +403,15 @@ typedef enum {
I3312_LDRSHX = 0x38000000 | LDST_LD_S_X << 22 | MO_16 << 30,
I3312_LDRSWX = 0x38000000 | LDST_LD_S_X << 22 | MO_32 << 30,
+ I3312_LDRVS = 0x3c000000 | LDST_LD << 22 | MO_32 << 30,
+ I3312_STRVS = 0x3c000000 | LDST_ST << 22 | MO_32 << 30,
+
+ I3312_LDRVD = 0x3c000000 | LDST_LD << 22 | MO_64 << 30,
+ I3312_STRVD = 0x3c000000 | LDST_ST << 22 | MO_64 << 30,
+
+ I3312_LDRVQ = 0x3c000000 | 3 << 22 | 0 << 30,
+ I3312_STRVQ = 0x3c000000 | 2 << 22 | 0 << 30,
+
I3312_TO_I3310 = 0x00200800,
I3312_TO_I3313 = 0x01000000,
@@ -374,8 +496,58 @@ typedef enum {
I3510_EON = 0x4a200000,
I3510_ANDS = 0x6a000000,
- NOP = 0xd503201f,
+ /* AdvSIMD zip.uzp/trn */
+ I3603_ZIP1 = 0x0e003800,
+ I3603_UZP1 = 0x0e001800,
+ I3603_TRN1 = 0x0e002800,
+ I3603_ZIP2 = 0x0e007800,
+ I3603_UZP2 = 0x0e005800,
+ I3603_TRN2 = 0x0e006800,
+
+ /* AdvSIMD copy */
+ I3605_DUP = 0x0e000400,
+ I3605_INS = 0x4e001c00,
+ I3605_UMOV = 0x0e003c00,
+
+ /* AdvSIMD modified immediate */
+ I3606_MOVI = 0x0f000400,
+
+ /* AdvSIMD shift by immediate */
+ I3614_SSHR = 0x0f000400,
+ I3614_SSRA = 0x0f001400,
+ I3614_SHL = 0x0f005400,
+ I3614_SSHLL = 0x0f00a400,
+ I3614_USHR = 0x2f000400,
+ I3614_USRA = 0x2f001400,
+ I3614_USHLL = 0x2f00a400,
+
+ /* AdvSIMD three same. */
+ I3616_ADD = 0x0e208400,
+ I3616_AND = 0x0e201c00,
+ I3616_BIC = 0x0e601c00,
+ I3616_EOR = 0x2e201c00,
+ I3616_MUL = 0x0e209c00,
+ I3616_ORR = 0x0ea01c00,
+ I3616_ORN = 0x0ee01c00,
+ I3616_SUB = 0x2e208400,
+ I3616_CMGT = 0x0e203400,
+ I3616_CMGE = 0x0e203c00,
+ I3616_CMTST = 0x0e208c00,
+ I3616_CMHI = 0x2e203400,
+ I3616_CMHS = 0x2e203c00,
+ I3616_CMEQ = 0x2e208c00,
+
+ /* AdvSIMD two-reg misc. */
+ I3617_CMGT0 = 0x0e208800,
+ I3617_CMEQ0 = 0x0e209800,
+ I3617_CMLT0 = 0x0e20a800,
+ I3617_CMGE0 = 0x2e208800,
+ I3617_CMLE0 = 0x2e20a800,
+ I3617_NOT = 0x2e205800,
+ I3617_NEG = 0x2e20b800,
+
/* System instructions. */
+ NOP = 0xd503201f,
DMB_ISH = 0xd50338bf,
DMB_LD = 0x00000100,
DMB_ST = 0x00000200,
@@ -520,26 +692,71 @@ static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
}
+static void tcg_out_insn_3603(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22) | (rd & 0x1f)
+ | (rn & 0x1f) << 5 | (rm & 0x1f) << 16);
+}
+
+static void tcg_out_insn_3605(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, TCGReg rn, int dst_idx, int src_idx)
+{
+ /* Note that bit 11 set means general register input. Therefore
+ we can handle both register sets with one function. */
+ tcg_out32(s, insn | q << 30 | (dst_idx << 16) | (src_idx << 11)
+ | (rd & 0x1f) | (~rn & 0x20) << 6 | (rn & 0x1f) << 5);
+}
+
+static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, bool op, int cmode, uint8_t imm8)
+{
+ tcg_out32(s, insn | q << 30 | op << 29 | cmode << 12 | (rd & 0x1f)
+ | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5);
+}
+
+static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q,
+ TCGReg rd, TCGReg rn, unsigned immhb)
+{
+ tcg_out32(s, insn | q << 30 | immhb << 16
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3616(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn, TCGReg rm)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22) | (rm & 0x1f) << 16
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
+static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
+ unsigned size, TCGReg rd, TCGReg rn)
+{
+ tcg_out32(s, insn | q << 30 | (size << 22)
+ | (rn & 0x1f) << 5 | (rd & 0x1f));
+}
+
static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
TCGReg rd, TCGReg base, TCGType ext,
TCGReg regoff)
{
/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
- 0x4000 | ext << 13 | base << 5 | rd);
+ 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
}
static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
TCGReg rd, TCGReg rn, intptr_t offset)
{
- tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | rd);
+ tcg_out32(s, insn | (offset & 0x1ff) << 12 | rn << 5 | (rd & 0x1f));
}
static void tcg_out_insn_3313(TCGContext *s, AArch64Insn insn,
TCGReg rd, TCGReg rn, uintptr_t scaled_uimm)
{
/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
- tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10 | rn << 5 | rd);
+ tcg_out32(s, insn | I3312_TO_I3313 | scaled_uimm << 10
+ | rn << 5 | (rd & 0x1f));
}
/* Register to register move using ORR (shifted register with no shift). */
@@ -585,6 +802,35 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
}
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
+ TCGReg rd, uint64_t v64)
+{
+ int op, cmode, imm8;
+
+ if (is_fimm(v64, &op, &cmode, &imm8)) {
+ tcg_out_insn(s, 3606, MOVI, type == TCG_TYPE_V128, rd, op, cmode, imm8);
+ } else if (type == TCG_TYPE_V128) {
+ new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, v64, v64);
+ tcg_out_insn(s, 3305, LDR_v128, 0, rd);
+ } else {
+ new_pool_label(s, v64, R_AARCH64_CONDBR19, s->code_ptr, 0);
+ tcg_out_insn(s, 3305, LDR_v64, 0, rd);
+ }
+}
+
+static void tcg_out_movi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, const TCGArg *a)
+{
+ if (type == TCG_TYPE_V128) {
+ /* We assume that INDEX_op_dupi could not be used and
+ therefore we must use a constant pool entry. */
+ new_pool_l2(s, R_AARCH64_CONDBR19, s->code_ptr, 0, a[0], a[1]);
+ tcg_out_insn(s, 3305, LDR_v128, 0, ret);
+ } else {
+ tcg_out_dupi_vec(s, TCG_TYPE_V64, ret, a[0]);
+ }
+}
+
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_target_long value)
{
@@ -594,6 +840,22 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
int s0, s1;
AArch64Insn opc;
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_debug_assert(rd < 32);
+ break;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_debug_assert(rd >= 32);
+ tcg_out_dupi_vec(s, type, rd, value);
+ return;
+
+ default:
+ g_assert_not_reached();
+ }
+
/* For 32-bit values, discard potential garbage in value. For 64-bit
values within [2**31, 2**32-1], we can create smaller sequences by
interpreting this as a negative 32-bit number, while ensuring that
@@ -669,15 +931,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
/* Define something more legible for general use. */
#define tcg_out_ldst_r tcg_out_insn_3310
-static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,
- TCGReg rd, TCGReg rn, intptr_t offset)
+static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
+ TCGReg rn, intptr_t offset, int lgsize)
{
- TCGMemOp size = (uint32_t)insn >> 30;
-
/* If the offset is naturally aligned and in range, then we can
use the scaled uimm12 encoding */
- if (offset >= 0 && !(offset & ((1 << size) - 1))) {
- uintptr_t scaled_uimm = offset >> size;
+ if (offset >= 0 && !(offset & ((1 << lgsize) - 1))) {
+ uintptr_t scaled_uimm = offset >> lgsize;
if (scaled_uimm <= 0xfff) {
tcg_out_insn_3313(s, insn, rd, rn, scaled_uimm);
return;
@@ -695,32 +955,102 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn,
tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
}
-static inline void tcg_out_mov(TCGContext *s,
- TCGType type, TCGReg ret, TCGReg arg)
+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- if (ret != arg) {
- tcg_out_movr(s, type, ret, arg);
+ if (ret == arg) {
+ return;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ if (ret < 32 && arg < 32) {
+ tcg_out_movr(s, type, ret, arg);
+ break;
+ } else if (ret < 32) {
+ tcg_out_insn(s, 3605, UMOV, type, ret, arg, 0, 0);
+ break;
+ } else if (arg < 32) {
+ tcg_out_insn(s, 3605, INS, 0, ret, arg, 4 << type, 0);
+ break;
+ }
+ /* FALLTHRU */
+
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 32 && arg >= 32);
+ tcg_out_insn(s, 3616, ORR, 0, 0, ret, arg, arg);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 32 && arg >= 32);
+ tcg_out_insn(s, 3616, ORR, 1, 0, ret, arg, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
}
}
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg base, intptr_t ofs)
{
- tcg_out_ldst(s, type == TCG_TYPE_I32 ? I3312_LDRW : I3312_LDRX,
- arg, arg1, arg2);
+ AArch64Insn insn;
+ int lgsz;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ insn = (ret < 32 ? I3312_LDRW : I3312_LDRVS);
+ lgsz = 2;
+ break;
+ case TCG_TYPE_I64:
+ insn = (ret < 32 ? I3312_LDRX : I3312_LDRVD);
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V64:
+ insn = I3312_LDRVD;
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V128:
+ insn = I3312_LDRVQ;
+ lgsz = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_ldst(s, insn, ret, base, ofs, lgsz);
}
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src,
+ TCGReg base, intptr_t ofs)
{
- tcg_out_ldst(s, type == TCG_TYPE_I32 ? I3312_STRW : I3312_STRX,
- arg, arg1, arg2);
+ AArch64Insn insn;
+ int lgsz;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ insn = (src < 32 ? I3312_STRW : I3312_STRVS);
+ lgsz = 2;
+ break;
+ case TCG_TYPE_I64:
+ insn = (src < 32 ? I3312_STRX : I3312_STRVD);
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V64:
+ insn = I3312_STRVD;
+ lgsz = 3;
+ break;
+ case TCG_TYPE_V128:
+ insn = I3312_STRVQ;
+ lgsz = 4;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ tcg_out_ldst(s, insn, src, base, ofs, lgsz);
}
static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
TCGReg base, intptr_t ofs)
{
- if (val == 0) {
+ if (type <= TCG_TYPE_I64 && val == 0) {
tcg_out_st(s, type, TCG_REG_XZR, base, ofs);
return true;
}
@@ -1210,14 +1540,15 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, TCGMemOp opc,
/* Merge "low bits" from tlb offset, load the tlb comparator into X0.
X0 = load [X2 + (tlb_offset & 0x000fff)] */
tcg_out_ldst(s, TARGET_LONG_BITS == 32 ? I3312_LDRW : I3312_LDRX,
- TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff);
+ TCG_REG_X0, TCG_REG_X2, tlb_offset & 0xfff,
+ TARGET_LONG_BITS == 32 ? 2 : 3);
/* Load the tlb addend. Do that early to avoid stalling.
X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */
tcg_out_ldst(s, I3312_LDRX, TCG_REG_X1, TCG_REG_X2,
(tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) -
(is_read ? offsetof(CPUTLBEntry, addr_read)
- : offsetof(CPUTLBEntry, addr_write)));
+ : offsetof(CPUTLBEntry, addr_write)), 3);
/* Perform the address comparison. */
tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
@@ -1435,49 +1766,49 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
- tcg_out_ldst(s, I3312_LDRB, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRB, a0, a1, a2, 0);
break;
case INDEX_op_ld8s_i32:
- tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSBW, a0, a1, a2, 0);
break;
case INDEX_op_ld8s_i64:
- tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSBX, a0, a1, a2, 0);
break;
case INDEX_op_ld16u_i32:
case INDEX_op_ld16u_i64:
- tcg_out_ldst(s, I3312_LDRH, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRH, a0, a1, a2, 1);
break;
case INDEX_op_ld16s_i32:
- tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSHW, a0, a1, a2, 1);
break;
case INDEX_op_ld16s_i64:
- tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSHX, a0, a1, a2, 1);
break;
case INDEX_op_ld_i32:
case INDEX_op_ld32u_i64:
- tcg_out_ldst(s, I3312_LDRW, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRW, a0, a1, a2, 2);
break;
case INDEX_op_ld32s_i64:
- tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRSWX, a0, a1, a2, 2);
break;
case INDEX_op_ld_i64:
- tcg_out_ldst(s, I3312_LDRX, a0, a1, a2);
+ tcg_out_ldst(s, I3312_LDRX, a0, a1, a2, 3);
break;
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
- tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRB, REG0(0), a1, a2, 0);
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
- tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRH, REG0(0), a1, a2, 1);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
- tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRW, REG0(0), a1, a2, 2);
break;
case INDEX_op_st_i64:
- tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2);
+ tcg_out_ldst(s, I3312_STRX, REG0(0), a1, a2, 3);
break;
case INDEX_op_add_i32:
@@ -1776,25 +2107,230 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
+ case INDEX_op_mov_vec:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_movi_i64:
+ case INDEX_op_dupi_vec:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
- tcg_abort();
+ g_assert_not_reached();
}
#undef REG0
}
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static const AArch64Insn cmp_insn[16] = {
+ [TCG_COND_EQ] = I3616_CMEQ,
+ [TCG_COND_GT] = I3616_CMGT,
+ [TCG_COND_GE] = I3616_CMGE,
+ [TCG_COND_GTU] = I3616_CMHI,
+ [TCG_COND_GEU] = I3616_CMHS,
+ };
+ static const AArch64Insn cmp0_insn[16] = {
+ [TCG_COND_EQ] = I3617_CMEQ0,
+ [TCG_COND_GT] = I3617_CMGT0,
+ [TCG_COND_GE] = I3617_CMGE0,
+ [TCG_COND_LT] = I3617_CMLT0,
+ [TCG_COND_LE] = I3617_CMLE0,
+ };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ unsigned is_q = vecl;
+ TCGArg a0, a1, a2;
+
+ a0 = args[0];
+ a1 = args[1];
+ a2 = args[2];
+
+ switch (opc) {
+ case INDEX_op_movi_vec:
+ tcg_out_movi_vec(s, type, a0, args + 1);
+ break;
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ break;
+ case INDEX_op_add_vec:
+ tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_sub_vec:
+ tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_mul_vec:
+ tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_neg_vec:
+ tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1);
+ break;
+ case INDEX_op_and_vec:
+ tcg_out_insn(s, 3616, AND, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_or_vec:
+ tcg_out_insn(s, 3616, ORR, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_xor_vec:
+ tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_andc_vec:
+ tcg_out_insn(s, 3616, BIC, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_orc_vec:
+ tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2);
+ break;
+ case INDEX_op_not_vec:
+ tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1);
+ break;
+ case INDEX_op_dup_vec:
+ tcg_out_insn(s, 3605, DUP, is_q, a0, a1, 1 << vece, 0);
+ break;
+ case INDEX_op_shli_vec:
+ tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece));
+ break;
+ case INDEX_op_shri_vec:
+ tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2);
+ break;
+ case INDEX_op_sari_vec:
+ tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2);
+ break;
+ case INDEX_op_cmp_vec:
+ {
+ TCGCond cond = args[3];
+ AArch64Insn insn;
+
+ if (cond == TCG_COND_NE) {
+ if (const_args[2]) {
+ tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1);
+ } else {
+ tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2);
+ tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0);
+ }
+ } else {
+ if (const_args[2]) {
+ insn = cmp0_insn[cond];
+ if (insn) {
+ tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
+ break;
+ }
+ tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0);
+ a2 = TCG_VEC_TMP;
+ }
+ insn = cmp_insn[cond];
+ if (insn == 0) {
+ TCGArg t;
+ t = a1, a1 = a2, a2 = t;
+ cond = tcg_swap_cond(cond);
+ insn = cmp_insn[cond];
+ tcg_debug_assert(insn != 0);
+ }
+ tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2);
+ }
+ }
+ break;
+ case INDEX_op_zipl_vec:
+ tcg_out_insn(s, 3603, ZIP1, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_ziph_vec:
+ tcg_out_insn(s, 3603, ZIP2, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_uzpe_vec:
+ tcg_out_insn(s, 3603, UZP1, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_uzpo_vec:
+ tcg_out_insn(s, 3603, UZP2, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_trne_vec:
+ tcg_out_insn(s, 3603, TRN1, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_trno_vec:
+ tcg_out_insn(s, 3603, TRN2, is_q, vece, a0, a1, a2);
+ break;
+ case INDEX_op_extul_vec:
+ tcg_out_insn(s, 3614, USHLL, 0, a0, a1, 0 + (8 << vece));
+ break;
+ case INDEX_op_extuh_vec:
+ if (is_q) {
+ tcg_out_insn(s, 3614, USHLL, 1, a0, a1, 0 + (8 << vece));
+ } else {
+ tcg_out_insn(s, 3614, USHLL, 0, a0, a1, 0 + (8 << vece));
+ tcg_out_insn(s, 3605, INS, 0, a0, a0, 8, 16);
+ }
+ break;
+ case INDEX_op_extsl_vec:
+ tcg_out_insn(s, 3614, SSHLL, 0, a0, a1, 0 + (8 << vece));
+ break;
+ case INDEX_op_extsh_vec:
+ if (is_q) {
+ tcg_out_insn(s, 3614, SSHLL, 1, a0, a1, 0 + (8 << vece));
+ } else {
+ tcg_out_insn(s, 3614, SSHLL, 0, a0, a1, 0 + (8 << vece));
+ tcg_out_insn(s, 3605, INS, 0, a0, a0, 8, 16);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_not_vec:
+ case INDEX_op_cmp_vec:
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_extul_vec:
+ case INDEX_op_extuh_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extsh_vec:
+ return 1;
+
+ default:
+ return 0;
+ }
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+}
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
+ static const TCGTargetOpDef w = { .args_ct_str = { "w" } };
static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
+ static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
+ static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
+ static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
+ static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
+ static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
@@ -1938,6 +2474,41 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub2_i64:
return &add2;
+ case INDEX_op_movi_vec:
+ return &w;
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_zipl_vec:
+ case INDEX_op_ziph_vec:
+ case INDEX_op_uzpe_vec:
+ case INDEX_op_uzpo_vec:
+ case INDEX_op_trne_vec:
+ case INDEX_op_trno_vec:
+ return &w_w_w;
+ case INDEX_op_not_vec:
+ case INDEX_op_neg_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
+ case INDEX_op_extul_vec:
+ case INDEX_op_extuh_vec:
+ case INDEX_op_extsl_vec:
+ case INDEX_op_extsh_vec:
+ return &w_w;
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ return &w_r;
+ case INDEX_op_dup_vec:
+ return &w_wr;
+ case INDEX_op_cmp_vec:
+ return &w_w_wZ;
+
default:
return NULL;
}
@@ -1947,8 +2518,10 @@ static void tcg_target_init(TCGContext *s)
{
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
- tcg_target_call_clobber_regs = 0xfffffffu;
+ tcg_target_call_clobber_regs = -1ull;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21);
@@ -1960,12 +2533,21 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+ tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP);
}
/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */
--
2.13.6
^ permalink raw reply related [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (25 preceding siblings ...)
2017-11-21 21:25 ` [Qemu-devel] [PATCH v6 26/26] tcg/aarch64: Add vector operations Richard Henderson
@ 2017-11-21 22:10 ` no-reply
2017-11-21 22:19 ` no-reply
` (3 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: no-reply @ 2017-11-21 22:10 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel
Hi,
This series failed build test on s390x host. Please find the details below.
Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
Type: series
Message-id: 20171121212534.5177-1-richard.henderson@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that has the patches applied on top of "base"
# branch
set -e
echo "=== ENV ==="
env
echo "=== PACKAGES ==="
rpm -qa
echo "=== TEST BEGIN ==="
CC=$HOME/bin/cc
INSTALL=$PWD/install
BUILD=$PWD/build
echo -n "Using CC: "
realpath $CC
mkdir -p $BUILD $INSTALL
SRC=$PWD
cd $BUILD
$SRC/configure --cc=$CC --prefix=$INSTALL
make -j4
# XXX: we need reliable clean up
# make check -j4 V=1
make install
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20171121212534.5177-1-richard.henderson@linaro.org -> patchew/20171121212534.5177-1-richard.henderson@linaro.org
Switched to a new branch 'test'
25cb597 tcg/aarch64: Add vector operations
3f5327e tcg/i386: Add vector operations/expansions for mul/extend
9842ec4 target/arm: Use vector infrastructure for aa64 widening shifts
5baa8f3 tcg: Add generic vector ops for extension
f31da52 target/arm: Use vector infrastructure for aa64 multiplies
32e5841 tcg: Add generic vector ops for multiplication
02b126c tcg/i386: Add vector operations/expansions for shift/cmp/interleave
bd28e62 target/arm: Use vector infrastructure for aa64 compares
c1bffde tcg: Add generic vector ops for comparisons
c6dfe9f target/arm: Use vector infrastructure for aa64 constant shifts
692cd85 tcg: Add generic vector ops for constant shifts
77a9e02 target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
8b8ba00 tcg: Add generic vector ops for interleave
e5c9bc0 tcg: Add tcg_expand_vec_op and tcg-target.opc.h
8f26874 tcg/i386: Add vector operations
2895593 target/arm: Use vector infrastructure for aa64 dup/movi
75b6cdb target/arm: Use vector infrastructure for aa64 mov/not/neg
01af1be target/arm: Use vector infrastructure for aa64 add/sub/logic
f368c49 target/arm: Align vector registers
0870bb2 tcg: Add tcg_signed_cond
0ac77ec tcg: Allow multiple word entries into the constant pool
729ef74 tcg: Add generic vector expanders
b0b5925 tcg: Add types and basic operations for host vectors
cfb2262 tcg: Generalize TCGOp parameters
17d3aaf tcg: Dynamically allocate TCGOps
795ee71 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*
=== OUTPUT BEGIN ===
=== ENV ===
XDG_SESSION_ID=101459
SHELL=/bin/sh
USER=fam
PATCHEW=/home/fam/patchew/patchew-cli -s http://patchew.org --nodebug
PATH=/usr/bin:/bin
PWD=/var/tmp/patchew-tester-tmp-w75fwes8/src
LANG=en_US.UTF-8
HOME=/home/fam
SHLVL=2
LOGNAME=fam
DBUS_SESSION_BUS_ADDRESS=unix:path=/run/user/1012/bus
XDG_RUNTIME_DIR=/run/user/1012
_=/usr/bin/env
=== PACKAGES ===
gpg-pubkey-873529b8-54e386ff
xz-libs-5.2.2-2.fc24.s390x
libxshmfence-1.2-3.fc24.s390x
giflib-4.1.6-15.fc24.s390x
trousers-lib-0.3.13-6.fc24.s390x
ncurses-base-6.0-6.20160709.fc25.noarch
gmp-6.1.1-1.fc25.s390x
libidn-1.33-1.fc25.s390x
slang-2.3.0-7.fc25.s390x
pkgconfig-0.29.1-1.fc25.s390x
alsa-lib-1.1.1-2.fc25.s390x
yum-metadata-parser-1.1.4-17.fc25.s390x
python3-slip-dbus-0.6.4-4.fc25.noarch
python2-cssselect-0.9.2-1.fc25.noarch
createrepo_c-libs-0.10.0-6.fc25.s390x
initscripts-9.69-1.fc25.s390x
parted-3.2-21.fc25.s390x
flex-2.6.0-3.fc25.s390x
colord-libs-1.3.4-1.fc25.s390x
python-osbs-client-0.33-3.fc25.noarch
perl-Pod-Simple-3.35-1.fc25.noarch
python2-simplejson-3.10.0-1.fc25.s390x
brltty-5.4-2.fc25.s390x
librados2-10.2.4-2.fc25.s390x
tcp_wrappers-7.6-83.fc25.s390x
libcephfs_jni1-10.2.4-2.fc25.s390x
nettle-devel-3.3-1.fc25.s390x
bzip2-devel-1.0.6-21.fc25.s390x
libuuid-2.28.2-2.fc25.s390x
python3-dnf-1.1.10-6.fc25.noarch
texlive-kpathsea-doc-svn41139-33.fc25.1.noarch
openssh-7.4p1-4.fc25.s390x
texlive-kpathsea-bin-svn40473-33.20160520.fc25.1.s390x
texlive-graphics-svn41015-33.fc25.1.noarch
texlive-dvipdfmx-def-svn40328-33.fc25.1.noarch
texlive-mfware-svn40768-33.fc25.1.noarch
texlive-texlive-scripts-svn41433-33.fc25.1.noarch
texlive-euro-svn22191.1.1-33.fc25.1.noarch
texlive-etex-svn37057.0-33.fc25.1.noarch
texlive-iftex-svn29654.0.2-33.fc25.1.noarch
texlive-palatino-svn31835.0-33.fc25.1.noarch
texlive-texlive-docindex-svn41430-33.fc25.1.noarch
texlive-xunicode-svn30466.0.981-33.fc25.1.noarch
texlive-koma-script-svn41508-33.fc25.1.noarch
texlive-pst-grad-svn15878.1.06-33.fc25.1.noarch
texlive-pst-blur-svn15878.2.0-33.fc25.1.noarch
texlive-jknapltx-svn19440.0-33.fc25.1.noarch
texinfo-6.1-4.fc25.s390x
openssl-devel-1.0.2k-1.fc25.s390x
jansson-2.10-2.fc25.s390x
fedora-repos-25-4.noarch
perl-Errno-1.25-387.fc25.s390x
acl-2.2.52-13.fc25.s390x
systemd-pam-231-17.fc25.s390x
NetworkManager-libnm-1.4.4-5.fc25.s390x
poppler-0.45.0-5.fc25.s390x
ccache-3.3.4-1.fc25.s390x
valgrind-3.12.0-9.fc25.s390x
perl-open-1.10-387.fc25.noarch
libgcc-6.4.1-1.fc25.s390x
libsoup-2.56.1-1.fc25.s390x
libstdc++-devel-6.4.1-1.fc25.s390x
libobjc-6.4.1-1.fc25.s390x
python2-rpm-4.13.0.1-2.fc25.s390x
python2-gluster-3.10.5-1.fc25.s390x
rpm-build-4.13.0.1-2.fc25.s390x
glibc-static-2.24-10.fc25.s390x
lz4-1.8.0-1.fc25.s390x
xapian-core-libs-1.2.24-1.fc25.s390x
elfutils-libelf-devel-0.169-1.fc25.s390x
nss-softokn-3.32.0-1.2.fc25.s390x
pango-1.40.9-1.fc25.s390x
glibc-debuginfo-common-2.24-10.fc25.s390x
libaio-0.3.110-6.fc24.s390x
libfontenc-1.1.3-3.fc24.s390x
lzo-2.08-8.fc24.s390x
isl-0.14-5.fc24.s390x
libXau-1.0.8-6.fc24.s390x
linux-atm-libs-2.5.1-14.fc24.s390x
libXext-1.3.3-4.fc24.s390x
libXxf86vm-1.1.4-3.fc24.s390x
bison-3.0.4-4.fc24.s390x
perl-srpm-macros-1-20.fc25.noarch
gawk-4.1.3-8.fc25.s390x
libwayland-client-1.12.0-1.fc25.s390x
perl-Exporter-5.72-366.fc25.noarch
perl-version-0.99.17-1.fc25.s390x
fftw-libs-double-3.3.5-3.fc25.s390x
libssh2-1.8.0-1.fc25.s390x
ModemManager-glib-1.6.4-1.fc25.s390x
newt-python3-0.52.19-2.fc25.s390x
python-munch-2.0.4-3.fc25.noarch
python-bugzilla-1.2.2-4.fc25.noarch
libedit-3.1-16.20160618cvs.fc25.s390x
createrepo_c-0.10.0-6.fc25.s390x
device-mapper-multipath-libs-0.4.9-83.fc25.s390x
yum-3.4.3-510.fc25.noarch
mozjs17-17.0.0-16.fc25.s390x
libselinux-2.5-13.fc25.s390x
python2-pyparsing-2.1.10-1.fc25.noarch
cairo-gobject-1.14.8-1.fc25.s390x
xorg-x11-proto-devel-7.7-20.fc25.noarch
brlapi-0.6.5-2.fc25.s390x
librados-devel-10.2.4-2.fc25.s390x
libXinerama-devel-1.1.3-6.fc24.s390x
lua-posix-33.3.1-3.fc25.s390x
usbredir-devel-0.7.1-2.fc24.s390x
python3-dnf-plugins-core-0.1.21-5.fc25.noarch
texlive-pdftex-doc-svn41149-33.fc25.1.noarch
openssh-clients-7.4p1-4.fc25.s390x
iptables-1.6.0-3.fc25.s390x
texlive-texlive.infra-svn41280-33.fc25.1.noarch
texlive-graphics-cfg-svn40269-33.fc25.1.noarch
texlive-bibtex-svn40768-33.fc25.1.noarch
texlive-mfware-bin-svn40473-33.20160520.fc25.1.s390x
texlive-texlive-scripts-bin-svn29741.0-33.20160520.fc25.1.noarch
texlive-sauerj-svn15878.0-33.fc25.1.noarch
texlive-enctex-svn34957.0-33.fc25.1.noarch
texlive-ifetex-svn24853.1.2-33.fc25.1.noarch
texlive-ntgclass-svn15878.2.1a-33.fc25.1.noarch
texlive-tex-gyre-math-svn41264-33.fc25.1.noarch
texlive-bera-svn20031.0-33.fc25.1.noarch
texlive-ms-svn29849.0-33.fc25.1.noarch
texlive-pst-fill-svn15878.1.01-33.fc25.1.noarch
texlive-ctable-svn38672-33.fc25.1.noarch
texlive-extsizes-svn17263.1.4a-33.fc25.1.noarch
texlive-collection-latexrecommended-svn35765.0-33.20160520.fc25.1.noarch
perl-Filter-1.57-1.fc25.s390x
python2-rpm-macros-3-12.fc25.noarch
gdbm-1.13-1.fc25.s390x
libtasn1-4.12-1.fc25.s390x
fedora-release-25-2.noarch
gdb-headless-7.12.1-48.fc25.s390x
perl-macros-5.24.2-387.fc25.s390x
pcre-devel-8.41-1.fc25.s390x
libX11-1.6.5-1.fc25.s390x
coreutils-8.25-17.fc25.s390x
python2-openidc-client-0-3.20170523git77cb3ee.fc25.noarch
systemtap-client-3.1-5.fc25.s390x
firewalld-0.4.4.5-1.fc25.noarch
glibc-2.24-10.fc25.s390x
libglvnd-egl-0.2.999-24.20170818git8d4d03f.fc25.s390x
libkadm5-1.14.4-8.fc25.s390x
glusterfs-fuse-3.10.5-1.fc25.s390x
libgfortran-6.4.1-1.fc25.s390x
python3-rpm-4.13.0.1-2.fc25.s390x
glusterfs-extra-xlators-3.10.5-1.fc25.s390x
dracut-config-rescue-046-2.git20170811.fc25.s390x
python2-sphinx-theme-alabaster-0.7.9-1.fc25.noarch
elfutils-devel-0.169-1.fc25.s390x
nss-3.32.0-1.1.fc25.s390x
pango-devel-1.40.9-1.fc25.s390x
glibc-debuginfo-2.24-10.fc25.s390x
gpg-pubkey-efe550f5-5220ba41
gpg-pubkey-81b46521-55b3ca9a
filesystem-3.2-37.fc24.s390x
libffi-3.1-9.fc24.s390x
keyutils-libs-1.5.9-8.fc24.s390x
libnfnetlink-1.0.1-8.fc24.s390x
libtheora-1.1.1-14.fc24.s390x
xml-common-0.6.3-44.fc24.noarch
autoconf-2.69-22.fc24.noarch
libXt-1.1.5-3.fc24.s390x
kbd-legacy-2.0.3-3.fc24.noarch
ghostscript-fonts-5.50-35.fc24.noarch
libXevie-1.0.3-11.fc24.s390x
libcap-2.25-2.fc25.s390x
mpfr-3.1.5-1.fc25.s390x
perl-Carp-1.40-365.fc25.noarch
libmnl-1.0.4-1.fc25.s390x
perl-Unicode-EastAsianWidth-1.33-8.fc25.noarch
libwayland-cursor-1.12.0-1.fc25.s390x
python-krbV-1.0.90-12.fc25.s390x
python2-urllib3-1.15.1-3.fc25.noarch
fipscheck-1.4.1-11.fc25.s390x
libndp-1.6-1.fc25.s390x
gnupg2-2.1.13-2.fc25.s390x
libXfixes-5.0.3-1.fc25.s390x
adwaita-icon-theme-3.22.0-1.fc25.noarch
dconf-0.26.0-1.fc25.s390x
ncurses-devel-6.0-6.20160709.fc25.s390x
dejagnu-1.6-1.fc25.noarch
device-mapper-1.02.136-3.fc25.s390x
libevent-2.0.22-1.fc25.s390x
atk-devel-2.22.0-1.fc25.s390x
libev-4.24-1.fc25.s390x
xorg-x11-fonts-Type1-7.5-16.fc24.noarch
brlapi-devel-0.6.5-2.fc25.s390x
pulseaudio-libs-10.0-2.fc25.s390x
glib2-2.50.3-1.fc25.s390x
dnf-1.1.10-6.fc25.noarch
texlive-metafont-bin-svn40987-33.20160520.fc25.1.s390x
texlive-xkeyval-svn35741.2.7a-33.fc25.1.noarch
texlive-euler-svn17261.2.5-33.fc25.1.noarch
texlive-mptopdf-svn41282-33.fc25.1.noarch
texlive-wasy-svn35831.0-33.fc25.1.noarch
texlive-avantgar-svn31835.0-33.fc25.1.noarch
texlive-eurosym-svn17265.1.4_subrfix-33.fc25.1.noarch
texlive-knuth-lib-svn35820.0-33.fc25.1.noarch
texlive-parallel-svn15878.0-33.fc25.1.noarch
texlive-texlive-msg-translations-svn41431-33.fc25.1.noarch
texlive-latex-svn40218-33.fc25.1.noarch
texlive-lualatex-math-svn40621-33.fc25.1.noarch
texlive-auto-pst-pdf-svn23723.0.6-33.fc25.1.noarch
texlive-powerdot-svn38984-33.fc25.1.noarch
texlive-wasysym-svn15878.2.0-33.fc25.1.noarch
ImageMagick-libs-6.9.3.0-6.fc25.s390x
geoclue2-2.4.5-1.fc25.s390x
perl-IO-Socket-IP-0.39-1.fc25.noarch
python2-pyasn1-0.2.3-1.fc25.noarch
at-spi2-core-devel-2.22.1-1.fc25.s390x
libacl-2.2.52-13.fc25.s390x
perl-libs-5.24.2-387.fc25.s390x
mesa-libglapi-17.0.5-3.fc25.s390x
python3-rpmconf-1.0.19-1.fc25.noarch
pcre-utf32-8.41-1.fc25.s390x
libX11-common-1.6.5-1.fc25.noarch
coreutils-common-8.25-17.fc25.s390x
mesa-libEGL-17.0.5-3.fc25.s390x
systemtap-runtime-3.1-5.fc25.s390x
NetworkManager-glib-1.4.4-5.fc25.s390x
audit-2.7.7-1.fc25.s390x
glibc-all-langpacks-2.24-10.fc25.s390x
libglvnd-glx-0.2.999-24.20170818git8d4d03f.fc25.s390x
glusterfs-api-3.10.5-1.fc25.s390x
libepoxy-devel-1.4.3-1.fc25.1.s390x
gtk3-3.22.17-2.fc25.s390x
rpm-4.13.0.1-2.fc25.s390x
net-snmp-agent-libs-5.7.3-15.fc25.s390x
pcre2-devel-10.23-9.fc25.s390x
subversion-1.9.7-1.fc25.s390x
libsndfile-1.0.28-6.fc25.s390x
lasi-1.1.2-6.fc24.s390x
python2-snowballstemmer-1.2.1-1.fc25.noarch
nss-util-devel-3.32.0-1.0.fc25.s390x
vim-common-8.0.1030-1.fc25.s390x
gd-2.2.5-1.fc25.s390x
gpg-pubkey-34ec9cba-54e38751
gpg-pubkey-030d5aed-55b577f0
basesystem-11-2.fc24.noarch
libmpc-1.0.2-5.fc24.s390x
libunistring-0.9.4-3.fc24.s390x
libmodman-2.0.1-12.fc24.s390x
lsscsi-0.28-3.fc24.s390x
kbd-misc-2.0.3-3.fc24.noarch
kmod-23-1.fc25.s390x
newt-0.52.19-2.fc25.s390x
perl-Text-Unidecode-1.27-3.fc25.noarch
plymouth-core-libs-0.9.3-0.6.20160620git0e65b86c.fc25.s390x
which-2.21-1.fc25.s390x
python3-slip-0.6.4-4.fc25.noarch
python3-systemd-232-1.fc25.s390x
python-lockfile-0.11.0-4.fc25.noarch
python2-requests-2.10.0-4.fc25.noarch
libnghttp2-1.13.0-2.fc25.s390x
python-urlgrabber-3.10.1-9.fc25.noarch
iputils-20161105-1.fc25.s390x
rest-0.8.0-1.fc25.s390x
adwaita-cursor-theme-3.22.0-1.fc25.noarch
authconfig-6.2.10-14.fc25.s390x
automake-1.15-7.fc25.noarch
shared-mime-info-1.8-1.fc25.s390x
pigz-2.3.4-1.fc25.s390x
device-mapper-libs-1.02.136-3.fc25.s390x
dnsmasq-2.76-2.fc25.s390x
fedora-packager-0.6.0.1-1.fc25.noarch
libwebp-0.5.2-1.fc25.s390x
boost-system-1.60.0-10.fc25.s390x
libasyncns-0.8-10.fc24.s390x
libXau-devel-1.0.8-6.fc24.s390x
libverto-libev-0.2.6-6.fc24.s390x
python3-html5lib-0.999-9.fc25.noarch
ttmkfdir-3.0.9-48.fc24.s390x
pulseaudio-libs-glib2-10.0-2.fc25.s390x
texlive-lib-2016-33.20160520.fc25.s390x
libXi-devel-1.7.9-1.fc25.s390x
python3-distro-1.0.3-1.fc25.noarch
texlive-texlive-common-doc-svn40682-33.fc25.1.noarch
packagedb-cli-2.14.1-1.fc25.noarch
texlive-metafont-svn40793-33.fc25.1.noarch
texlive-tools-svn40934-33.fc25.1.noarch
texlive-enumitem-svn24146.3.5.2-33.fc25.1.noarch
texlive-mptopdf-bin-svn18674.0-33.20160520.fc25.1.noarch
texlive-underscore-svn18261.0-33.fc25.1.noarch
texlive-anysize-svn15878.0-33.fc25.1.noarch
texlive-euenc-svn19795.0.1h-33.fc25.1.noarch
texlive-kastrup-svn15878.0-33.fc25.1.noarch
texlive-paralist-svn39247-33.fc25.1.noarch
texlive-texlive-en-svn41185-33.fc25.1.noarch
texlive-tipa-svn29349.1.3-33.fc25.1.noarch
texlive-currfile-svn40725-33.fc25.1.noarch
texlive-pst-node-svn40743-33.fc25.1.noarch
texlive-pst-slpe-svn24391.1.31-33.fc25.1.noarch
texlive-typehtml-svn17134.0-33.fc25.1.noarch
SDL2-devel-2.0.5-3.fc25.s390x
libcroco-0.6.11-3.fc25.s390x
bluez-libs-devel-5.44-1.fc25.s390x
firewalld-filesystem-0.4.4.5-1.fc25.noarch
pcre-cpp-8.41-1.fc25.s390x
python3-firewall-0.4.4.5-1.fc25.noarch
freetype-devel-2.6.5-9.fc25.s390x
pcre-utf16-8.41-1.fc25.s390x
linux-firmware-20170605-74.git37857004.fc25.noarch
kernel-modules-4.11.10-200.fc25.s390x
systemtap-devel-3.1-5.fc25.s390x
polkit-0.113-8.fc25.s390x
perl-SelfLoader-1.23-387.fc25.noarch
libdb-utils-5.3.28-24.fc25.s390x
glibc-common-2.24-10.fc25.s390x
libglvnd-0.2.999-24.20170818git8d4d03f.fc25.s390x
webkitgtk4-2.16.6-1.fc25.s390x
rpm-build-libs-4.13.0.1-2.fc25.s390x
libglvnd-core-devel-0.2.999-24.20170818git8d4d03f.fc25.s390x
rpm-devel-4.13.0.1-2.fc25.s390x
kernel-4.12.9-200.fc25.s390x
libtool-ltdl-2.4.6-14.fc25.s390x
gts-0.7.6-29.20121130.fc24.s390x
python2-imagesize-0.7.1-2.fc25.noarch
nss-softokn-freebl-3.32.0-1.2.fc25.s390x
selinux-policy-3.13.1-225.22.fc25.noarch
kernel-devel-4.12.11-200.fc25.s390x
fontpackages-filesystem-1.44-17.fc24.noarch
groff-base-1.22.3-8.fc24.s390x
ilmbase-2.2.0-5.fc24.s390x
OpenEXR-libs-2.2.0-5.fc24.s390x
hesiod-3.2.1-6.fc24.s390x
sysfsutils-2.1.0-19.fc24.s390x
ocaml-srpm-macros-2-4.fc24.noarch
mailx-12.5-19.fc24.s390x
ncurses-libs-6.0-6.20160709.fc25.s390x
ipset-libs-6.29-1.fc25.s390x
gmp-devel-6.1.1-1.fc25.s390x
python-pip-8.1.2-2.fc25.noarch
harfbuzz-1.3.2-1.fc25.s390x
python2-iniparse-0.4-20.fc25.noarch
python3-iniparse-0.4-20.fc25.noarch
python3-kickstart-2.32-1.fc25.noarch
perl-Net-SSLeay-1.78-1.fc25.s390x
drpm-0.3.0-3.fc25.s390x
glib-networking-2.50.0-1.fc25.s390x
webkitgtk3-2.4.11-3.fc25.s390x
libXaw-1.0.13-4.fc25.s390x
xorg-x11-font-utils-7.5-32.fc25.s390x
hardlink-1.1-1.fc25.s390x
libcom_err-1.43.3-1.fc25.s390x
python2-dateutil-2.6.0-1.fc25.noarch
libXpm-3.5.12-1.fc25.s390x
poppler-data-0.4.7-6.fc25.noarch
librbd1-10.2.4-2.fc25.s390x
perl-Digest-MD5-2.55-2.fc25.s390x
wayland-protocols-devel-1.7-1.fc25.noarch
texi2html-5.0-4.fc24.noarch
libxkbcommon-0.7.1-1.fc25.s390x
libuuid-devel-2.28.2-2.fc25.s390x
libcacard-2.5.3-1.fc25.s390x
libwmf-lite-0.2.8.4-50.fc25.s390x
texlive-tetex-svn41059-33.fc25.1.noarch
texlive-thumbpdf-svn34621.3.16-33.fc25.1.noarch
texlive-carlisle-svn18258.0-33.fc25.1.noarch
texlive-makeindex-bin-svn40473-33.20160520.fc25.1.s390x
texlive-pdftex-svn41149-33.fc25.1.noarch
texlive-csquotes-svn39538-33.fc25.1.noarch
texlive-courier-svn35058.0-33.fc25.1.noarch
texlive-helvetic-svn31835.0-33.fc25.1.noarch
texlive-mfnfss-svn19410.0-33.fc25.1.noarch
texlive-sepnum-svn20186.2.0-33.fc25.1.noarch
texlive-utopia-svn15878.0-33.fc25.1.noarch
texlive-luatexbase-svn38550-33.fc25.1.noarch
texlive-pst-3d-svn17257.1.10-33.fc25.1.noarch
texlive-latex-bin-bin-svn14050.0-33.20160520.fc25.1.noarch
texlive-l3experimental-svn41163-33.fc25.1.noarch
net-tools-2.0-0.40.20160329git.fc25.s390x
perl-Pod-Perldoc-3.28-1.fc25.noarch
openssl-1.0.2k-1.fc25.s390x
man-pages-4.06-4.fc25.noarch
libxml2-2.9.4-2.fc25.s390x
python3-dateutil-2.6.0-1.fc25.noarch
perl-threads-shared-1.57-1.fc25.s390x
libnotify-0.7.7-1.fc25.s390x
unzip-6.0-32.fc25.s390x
python-beautifulsoup4-4.6.0-1.fc25.noarch
dhcp-client-4.3.5-3.fc25.s390x
python2-fedora-0.9.0-6.fc25.noarch
gdb-7.12.1-48.fc25.s390x
sqlite-libs-3.14.2-3.fc25.s390x
webkitgtk4-jsc-2.16.6-1.fc25.s390x
libgomp-6.4.1-1.fc25.s390x
p11-kit-trust-0.23.8-1.fc25.s390x
gdk-pixbuf2-devel-2.36.9-1.fc25.s390x
rpm-plugin-selinux-4.13.0.1-2.fc25.s390x
mariadb-common-10.1.25-1.fc25.s390x
dbus-devel-1.11.16-1.fc25.s390x
lz4-libs-1.8.0-1.fc25.s390x
python2-jinja2-2.8.1-1.fc25.noarch
system-python-libs-3.5.4-1.fc25.s390x
python2-rpkg-1.50-2.fc25.noarch
libsolv-0.6.29-1.fc25.s390x
gpg-pubkey-95a43f54-5284415a
dejavu-fonts-common-2.35-3.fc24.noarch
libSM-1.2.2-4.fc24.s390x
diffutils-3.3-13.fc24.s390x
libogg-1.3.2-5.fc24.s390x
hunspell-en-US-0.20140811.1-5.fc24.noarch
libdaemon-0.14-10.fc24.s390x
patch-2.7.5-3.fc24.s390x
libsysfs-2.1.0-19.fc24.s390x
procmail-3.22-39.fc24.s390x
libXdamage-1.1.4-8.fc24.s390x
libotf-0.9.13-7.fc24.s390x
urw-fonts-2.4-22.fc24.noarch
crontabs-1.11-12.20150630git.fc24.noarch
ppp-2.4.7-9.fc24.s390x
cyrus-sasl-2.1.26-26.2.fc24.s390x
zlib-devel-1.2.8-10.fc24.s390x
time-1.7-49.fc24.s390x
gpg-pubkey-fdb19c98-56fd6333
libcap-ng-0.7.8-1.fc25.s390x
binutils-2.26.1-1.fc25.s390x
lcms2-2.8-2.fc25.s390x
libcomps-0.1.7-5.fc25.s390x
perl-constant-1.33-367.fc25.noarch
perl-Data-Dumper-2.161-1.fc25.s390x
ipcalc-0.1.8-1.fc25.s390x
gmp-c++-6.1.1-1.fc25.s390x
fontconfig-2.12.1-1.fc25.s390x
enchant-1.6.0-14.fc25.s390x
pyliblzma-0.5.3-16.fc25.s390x
libsepol-devel-2.5-10.fc25.s390x
python3-ordered-set-2.0.0-4.fc25.noarch
python-ipaddress-1.0.16-3.fc25.noarch
python2-kerberos-1.2.5-1.fc25.s390x
python2-pysocks-1.5.6-5.fc25.noarch
fipscheck-lib-1.4.1-11.fc25.s390x
libatomic_ops-7.4.4-1.fc25.s390x
python2-pygpgme-0.3-18.fc25.s390x
orc-0.4.26-1.fc25.s390x
yum-utils-1.1.31-511.fc25.noarch
libXrender-0.9.10-1.fc25.s390x
libXrandr-1.5.1-1.fc25.s390x
go-srpm-macros-2-7.fc25.noarch
gnupg2-smime-2.1.13-2.fc25.s390x
guile-devel-2.0.13-1.fc25.s390x
uboot-tools-2016.09.01-2.fc25.s390x
pykickstart-2.32-1.fc25.noarch
python-bunch-1.0.1-9.fc25.noarch
perl-generators-1.10-1.fc25.noarch
perl-Mozilla-CA-20160104-3.fc25.noarch
bzip2-libs-1.0.6-21.fc25.s390x
libpng-1.6.27-1.fc25.s390x
desktop-file-utils-0.23-2.fc25.s390x
python2-cccolutils-1.4-1.fc25.s390x
python2-lxml-3.7.2-1.fc25.s390x
redhat-rpm-config-45-1.fc25.noarch
device-mapper-event-libs-1.02.136-3.fc25.s390x
lvm2-libs-2.02.167-3.fc25.s390x
libselinux-python-2.5-13.fc25.s390x
boost-thread-1.60.0-10.fc25.s390x
librbd-devel-10.2.4-2.fc25.s390x
libXcursor-devel-1.1.14-6.fc24.s390x
latex2html-2012-7.fc24.noarch
lksctp-tools-1.0.16-5.fc24.s390x
libfdt-1.4.2-1.fc25.s390x
libXft-devel-2.3.2-4.fc24.s390x
libattr-devel-2.4.47-16.fc24.s390x
libiscsi-devel-1.15.0-2.fc24.s390x
gettext-0.19.8.1-3.fc25.s390x
libjpeg-turbo-devel-1.5.1-0.fc25.s390x
pulseaudio-libs-devel-10.0-2.fc25.s390x
libmount-2.28.2-2.fc25.s390x
python3-decorator-4.0.11-1.fc25.noarch
tzdata-java-2017b-1.fc25.noarch
python-srpm-macros-3-12.fc25.noarch
libsmartcols-2.28.2-2.fc25.s390x
texlive-kpathsea-svn41139-33.fc25.1.noarch
texlive-amsmath-svn41561-33.fc25.1.noarch
texlive-thumbpdf-bin-svn6898.0-33.20160520.fc25.1.noarch
texlive-psnfss-svn33946.9.2a-33.fc25.1.noarch
texlive-subfig-svn15878.1.3-33.fc25.1.noarch
texlive-fancybox-svn18304.1.4-33.fc25.1.noarch
texlive-lua-alt-getopt-svn29349.0.7.0-33.fc25.1.noarch
texlive-natbib-svn20668.8.31b-33.fc25.1.noarch
texlive-pdftex-bin-svn40987-33.20160520.fc25.1.s390x
texlive-xdvi-svn40768-33.fc25.1.noarch
texlive-crop-svn15878.1.5-33.fc25.1.noarch
texlive-babel-english-svn30264.3.3p-33.fc25.1.noarch
texlive-cmextra-svn32831.0-33.fc25.1.noarch
texlive-fancyhdr-svn15878.3.1-33.fc25.1.noarch
texlive-luatex-svn40963-33.fc25.1.noarch
texlive-knuth-local-svn38627-33.fc25.1.noarch
texlive-mflogo-font-svn36898.1.002-33.fc25.1.noarch
texlive-parskip-svn19963.2.0-33.fc25.1.noarch
texlive-section-svn20180.0-33.fc25.1.noarch
texlive-textcase-svn15878.0-33.fc25.1.noarch
texlive-updmap-map-svn41159-33.fc25.1.noarch
texlive-attachfile-svn38830-33.fc25.1.noarch
libtiff-4.0.8-1.fc25.s390x
libdb-5.3.28-24.fc25.s390x
bind-license-9.10.5-2.P2.fc25.noarch
mesa-libGLES-17.0.5-3.fc25.s390x
python3-requests-kerberos-0.10.0-2.fc25.noarch
python3-pyOpenSSL-16.2.0-1.fc25.noarch
perl-threads-2.16-1.fc25.s390x
cryptsetup-libs-1.7.5-1.fc25.s390x
netpbm-10.79.00-1.fc25.s390x
qrencode-libs-3.4.4-1.fc25.s390x
gstreamer1-plugins-base-1.10.5-1.fc25.s390x
elfutils-default-yama-scope-0.169-1.fc25.noarch
systemd-udev-231-17.fc25.s390x
python2-koji-1.13.0-2.fc25.noarch
unbound-libs-1.6.3-1.fc25.s390x
openldap-2.4.44-11.fc25.s390x
koji-1.13.0-2.fc25.noarch
bind99-libs-9.9.10-2.P3.fc25.s390x
mesa-libGL-devel-17.0.5-3.fc25.s390x
graphite2-devel-1.3.10-1.fc25.s390x
systemtap-sdt-devel-3.1-5.fc25.s390x
iproute-tc-4.11.0-1.fc25.s390x
libarchive-3.2.2-2.fc25.s390x
publicsuffix-list-dafsa-20170424-1.fc25.noarch
expat-2.2.3-1.fc25.s390x
p11-kit-0.23.8-1.fc25.s390x
kernel-core-4.12.9-200.fc25.s390x
emacs-filesystem-25.2-3.fc25.noarch
ca-certificates-2017.2.16-1.0.fc25.noarch
librsvg2-2.40.18-1.fc25.s390x
gtk-update-icon-cache-3.22.17-2.fc25.s390x
libidn2-2.0.4-1.fc25.s390x
rpm-libs-4.13.0.1-2.fc25.s390x
mariadb-libs-10.1.25-1.fc25.s390x
java-1.8.0-openjdk-headless-1.8.0.144-5.b01.fc25.s390x
gcc-objc-6.4.1-1.fc25.s390x
p11-kit-devel-0.23.8-1.fc25.s390x
ethtool-4.11-1.fc25.s390x
python2-sssdconfig-1.15.3-1.fc25.noarch
xorg-x11-fonts-ISO8859-1-100dpi-7.5-16.fc24.noarch
lato-fonts-2.015-2.fc24.noarch
python-sphinx-locale-1.5.2-2.fc25.noarch
dpkg-1.17.27-1.fc25.s390x
gnutls-3.5.15-1.fc25.s390x
nss-softokn-freebl-devel-3.32.0-1.2.fc25.s390x
vim-filesystem-8.0.1030-1.fc25.s390x
gnutls-devel-3.5.15-1.fc25.s390x
kernel-headers-4.12.11-200.fc25.s390x
mock-1.4.6-1.fc25.noarch
texlive-luaotfload-svn40902-33.fc25.1.noarch
texlive-unicode-math-svn38462-33.fc25.1.noarch
texlive-fancyvrb-svn18492.2.8-33.fc25.1.noarch
texlive-pst-pdf-bin-svn7838.0-33.20160520.fc25.1.noarch
texlive-amscls-svn36804.0-33.fc25.1.noarch
texlive-ltxmisc-svn21927.0-33.fc25.1.noarch
texlive-breqn-svn38099.0.98d-33.fc25.1.noarch
texlive-xetex-def-svn40327-33.fc25.1.noarch
openssh-server-7.4p1-4.fc25.s390x
sendmail-8.15.2-8.fc25.s390x
tzdata-2017b-1.fc25.noarch
hunspell-1.4.1-2.fc25.s390x
gpg-pubkey-8e1431d5-53bcbac7
zlib-1.2.8-10.fc24.s390x
sed-4.2.2-15.fc24.s390x
psmisc-22.21-8.fc24.s390x
gpm-libs-1.20.7-9.fc24.s390x
zip-3.0-16.fc24.s390x
libyubikey-1.13-2.fc24.s390x
sg3_utils-libs-1.41-3.fc24.s390x
polkit-pkla-compat-0.1-7.fc24.s390x
passwd-0.79-8.fc24.s390x
trousers-0.3.13-6.fc24.s390x
grubby-8.40-3.fc24.s390x
rootfiles-8.1-19.fc24.noarch
nettle-3.3-1.fc25.s390x
libksba-1.3.5-1.fc25.s390x
perl-Text-ParseWords-3.30-365.fc25.noarch
perl-PathTools-3.63-366.fc25.s390x
perl-File-Temp-0.23.04-365.fc25.noarch
fuse-libs-2.9.7-1.fc25.s390x
perl-Pod-Escapes-1.07-365.fc25.noarch
perl-Term-ANSIColor-4.05-2.fc25.noarch
perl-URI-1.71-5.fc25.noarch
libXfont-1.5.2-1.fc25.s390x
python-six-1.10.0-3.fc25.noarch
dbus-glib-0.108-1.fc25.s390x
gobject-introspection-1.50.0-1.fc25.s390x
libpwquality-1.3.0-6.fc25.s390x
python-gobject-base-3.22.0-1.fc25.s390x
python-html5lib-0.999-9.fc25.noarch
python3-dbus-1.2.4-2.fc25.s390x
python3-chardet-2.3.0-1.fc25.noarch
python3-urllib3-1.15.1-3.fc25.noarch
python-offtrac-0.1.0-7.fc25.noarch
python2-cryptography-1.5.3-3.fc25.s390x
python2-requests-kerberos-0.10.0-2.fc25.noarch
libserf-1.3.9-1.fc25.s390x
libdatrie-0.2.9-3.fc25.s390x
s390utils-base-1.36.0-1.fc25.s390x
kpartx-0.4.9-83.fc25.s390x
s390utils-cpuplugd-1.36.0-1.fc25.s390x
s390utils-osasnmpd-1.36.0-1.fc25.s390x
python-dnf-plugins-extras-common-0.0.12-4.fc25.noarch
fpc-srpm-macros-1.0-1.fc25.noarch
libuser-0.62-4.fc25.s390x
man-db-2.7.5-3.fc25.s390x
python-systemd-doc-232-1.fc25.s390x
bodhi-client-0.9.12.2-6.fc25.noarch
cairo-1.14.8-1.fc25.s390x
cracklib-dicts-2.9.6-4.fc25.s390x
libselinux-python3-2.5-13.fc25.s390x
python2-enchant-1.6.8-1.fc25.noarch
boost-iostreams-1.60.0-10.fc25.s390x
userspace-rcu-0.9.2-2.fc25.s390x
libXext-devel-1.3.3-4.fc24.s390x
libXrandr-devel-1.5.1-1.fc25.s390x
python3-lxml-3.7.2-1.fc25.s390x
libiscsi-1.15.0-2.fc24.s390x
fontconfig-devel-2.12.1-1.fc25.s390x
libfdt-devel-1.4.2-1.fc25.s390x
ceph-devel-compat-10.2.4-2.fc25.s390x
zlib-static-1.2.8-10.fc24.s390x
chrpath-0.16-3.fc24.s390x
info-6.1-4.fc25.s390x
iptables-libs-1.6.0-3.fc25.s390x
libfdisk-2.28.2-2.fc25.s390x
dnf-plugins-core-0.1.21-5.fc25.noarch
perl-Storable-2.56-368.fc25.s390x
python2-decorator-4.0.11-1.fc25.noarch
libnetfilter_conntrack-1.0.6-2.fc25.s390x
texlive-texlive.infra-bin-svn40312-33.20160520.fc25.1.s390x
texlive-ifluatex-svn41346-33.fc25.1.noarch
texlive-fp-svn15878.0-33.fc25.1.noarch
texlive-latex-fonts-svn28888.0-33.fc25.1.noarch
texlive-bibtex-bin-svn40473-33.20160520.fc25.1.s390x
texlive-glyphlist-svn28576.0-33.fc25.1.noarch
texlive-marvosym-svn29349.2.2a-33.fc25.1.noarch
texlive-tex-bin-svn40987-33.20160520.fc25.1.s390x
texlive-texconfig-svn40768-33.fc25.1.noarch
texlive-wasy2-ps-svn35830.0-33.fc25.1.noarch
texlive-psfrag-svn15878.3.04-33.fc25.1.noarch
texlive-charter-svn15878.0-33.fc25.1.noarch
texlive-ec-svn25033.1.0-33.fc25.1.noarch
texlive-lineno-svn21442.4.41-33.fc25.1.noarch
texlive-hyphen-base-svn41138-33.fc25.1.noarch
texlive-manfnt-font-svn35799.0-33.fc25.1.noarch
texlive-ncntrsbk-svn31835.0-33.fc25.1.noarch
texlive-pst-math-svn34786.0.63-33.fc25.1.noarch
texlive-symbol-svn31835.0-33.fc25.1.noarch
texlive-environ-svn33821.0.3-33.fc25.1.noarch
texlive-algorithms-svn38085.0.1-33.fc25.1.noarch
python3-hawkey-0.6.4-3.fc25.s390x
freetype-2.6.5-9.fc25.s390x
mesa-libwayland-egl-17.0.5-3.fc25.s390x
libicu-57.1-5.fc25.s390x
libnl3-cli-3.2.29-3.fc25.s390x
cups-libs-2.2.0-9.fc25.s390x
bind-libs-lite-9.10.5-2.P2.fc25.s390x
python3-kerberos-1.2.5-1.fc25.s390x
python3-cryptography-1.5.3-3.fc25.s390x
perl-IO-1.36-387.fc25.s390x
dhcp-libs-4.3.5-3.fc25.s390x
rsync-3.1.2-4.fc25.s390x
make-4.1-6.fc25.s390x
quota-4.03-8.fc25.s390x
libX11-devel-1.6.5-1.fc25.s390x
ghostscript-9.20-9.fc25.s390x
rpcbind-0.2.4-6.rc2.fc25.s390x
pyOpenSSL-16.2.0-1.fc25.noarch
python3-pycurl-7.43.0-6.fc25.s390x
bind99-license-9.9.10-2.P3.fc25.noarch
python-firewall-0.4.4.5-1.fc25.noarch
netpbm-progs-10.79.00-1.fc25.s390x
wget-1.18-3.fc25.s390x
libsemanage-2.5-9.fc25.s390x
telnet-0.17-68.fc25.s390x
gdk-pixbuf2-2.36.9-1.fc25.s390x
dbus-libs-1.11.16-1.fc25.s390x
glusterfs-client-xlators-3.10.5-1.fc25.s390x
libepoxy-1.4.3-1.fc25.1.s390x
dracut-046-2.git20170811.fc25.s390x
net-snmp-libs-5.7.3-15.fc25.s390x
libgo-devel-6.4.1-1.fc25.s390x
libglvnd-opengl-0.2.999-24.20170818git8d4d03f.fc25.s390x
sqlite-devel-3.14.2-3.fc25.s390x
cpp-6.4.1-1.fc25.s390x
git-2.9.5-1.fc25.s390x
pcre2-10.23-9.fc25.s390x
python2-GitPython-2.1.5-1.fc25.noarch
glusterfs-devel-3.10.5-1.fc25.s390x
net-snmp-5.7.3-15.fc25.s390x
rpm-plugin-systemd-inhibit-4.13.0.1-2.fc25.s390x
emacs-25.2-3.fc25.s390x
libstdc++-static-6.4.1-1.fc25.s390x
expat-devel-2.2.3-1.fc25.s390x
perl-Time-HiRes-1.9744-1.fc25.s390x
fontawesome-fonts-4.7.0-1.fc25.noarch
python-markupsafe-0.23-10.fc25.s390x
pytz-2016.6.1-1.fc25.noarch
python2-sphinx-1.5.2-2.fc25.noarch
nss-util-3.32.0-1.0.fc25.s390x
nss-sysinit-3.32.0-1.1.fc25.s390x
python3-3.5.4-1.fc25.s390x
selinux-policy-targeted-3.13.1-225.22.fc25.noarch
vim-minimal-8.0.1030-1.fc25.s390x
texlive-ifplatform-svn21156.0.4-33.fc25.1.noarch
texlive-eso-pic-svn37925.2.0g-33.fc25.1.noarch
texlive-xcolor-svn41044-33.fc25.1.noarch
texlive-pst-eps-svn15878.1.0-33.fc25.1.noarch
texlive-pst-text-svn15878.1.00-33.fc25.1.noarch
texlive-rotating-svn16832.2.16b-33.fc25.1.noarch
texlive-pdfpages-svn40638-33.fc25.1.noarch
texlive-cm-super-svn15878.0-33.fc25.1.noarch
texlive-xetex-svn41438-33.fc25.1.noarch
dnf-yum-1.1.10-6.fc25.noarch
libseccomp-devel-2.3.2-1.fc25.s390x
gpgme-1.8.0-10.fc25.s390x
apr-util-1.5.4-3.fc24.s390x
jbigkit-libs-2.1-5.fc24.s390x
pixman-0.34.0-2.fc24.s390x
dwz-0.12-2.fc24.s390x
expect-5.45-22.fc24.s390x
libsigsegv-2.10-10.fc24.s390x
fakeroot-libs-1.20.2-4.fc24.s390x
m17n-lib-1.7.0-5.fc24.s390x
libverto-0.2.6-6.fc24.s390x
libXmu-1.1.2-4.fc24.s390x
libXcursor-1.1.14-6.fc24.s390x
python-kitchen-1.2.4-2.fc24.noarch
fakeroot-1.20.2-4.fc24.s390x
blktrace-1.1.0-3.fc24.s390x
usermode-1.111-8.fc24.s390x
kbd-2.0.3-3.fc24.s390x
libaio-devel-0.3.110-6.fc24.s390x
web-assets-filesystem-5-4.fc24.noarch
libgpg-error-1.24-1.fc25.s390x
findutils-4.6.0-8.fc25.s390x
libassuan-2.4.3-1.fc25.s390x
libusbx-1.0.21-1.fc25.s390x
libxslt-1.1.28-13.fc25.s390x
libmetalink-0.1.3-1.fc25.s390x
perl-MIME-Base64-3.15-365.fc25.s390x
ncurses-6.0-6.20160709.fc25.s390x
libwayland-server-1.12.0-1.fc25.s390x
perl-Fedora-VSP-0.001-4.fc25.noarch
perl-libintl-perl-1.26-1.fc25.s390x
shadow-utils-4.2.1-11.fc25.s390x
atk-2.22.0-1.fc25.s390x
pam-1.3.0-1.fc25.s390x
harfbuzz-icu-1.3.2-1.fc25.s390x
libsecret-0.18.5-2.fc25.s390x
s390utils-iucvterm-1.36.0-1.fc25.s390x
python3-requests-2.10.0-4.fc25.noarch
pyusb-1.0.0-2.fc25.noarch
python-enum34-1.0.4-6.fc25.noarch
pyxattr-0.5.3-8.fc25.s390x
libbabeltrace-1.4.0-3.fc25.s390x
libthai-0.1.25-1.fc25.s390x
deltarpm-3.6-17.fc25.s390x
s390utils-mon_statd-1.36.0-1.fc25.s390x
device-mapper-multipath-0.4.9-83.fc25.s390x
python3-pygpgme-0.3-18.fc25.s390x
libreport-filesystem-2.8.0-1.fc25.s390x
ghc-srpm-macros-1.4.2-4.fc25.noarch
rpmdevtools-8.9-1.fc25.noarch
python-dnf-plugins-extras-migrate-0.0.12-4.fc25.noarch
perl-IO-Socket-SSL-2.038-1.fc25.noarch
perl-File-ShareDir-1.102-7.fc25.noarch
tcl-8.6.6-1.fc25.s390x
bzip2-1.0.6-21.fc25.s390x
libss-1.43.3-1.fc25.s390x
libselinux-utils-2.5-13.fc25.s390x
python3-enchant-1.6.8-1.fc25.noarch
python2-dockerfile-parse-0.0.5-7.fc25.noarch
systemd-bootchart-231-2.fc25.s390x
e2fsprogs-1.43.3-1.fc25.s390x
libpng-devel-1.6.27-1.fc25.s390x
perl-XML-Parser-2.44-5.fc25.s390x
lttng-ust-2.8.1-2.fc25.s390x
libXfixes-devel-5.0.3-1.fc25.s390x
libXcomposite-devel-0.4.4-8.fc24.s390x
python3-javapackages-4.7.0-6.1.fc25.noarch
libcephfs_jni-devel-10.2.4-2.fc25.s390x
keyutils-libs-devel-1.5.9-8.fc24.s390x
harfbuzz-devel-1.3.2-1.fc25.s390x
libidn-devel-1.33-1.fc25.s390x
libnfs-1.9.8-2.fc24.s390x
libssh2-devel-1.8.0-1.fc25.s390x
qemu-sanity-check-nodeps-1.1.5-5.fc24.s390x
alsa-lib-devel-1.1.1-2.fc25.s390x
libpsl-0.17.0-1.fc25.s390x
libseccomp-2.3.2-1.fc25.s390x
json-glib-1.2.6-1.fc25.s390x
python2-dnf-1.1.10-6.fc25.noarch
texlive-tetex-bin-svn36770.0-33.20160520.fc25.1.noarch
texlive-amsfonts-svn29208.3.04-33.fc25.1.noarch
texlive-babel-svn40706-33.fc25.1.noarch
texlive-colortbl-svn29803.v1.0a-33.fc25.1.noarch
texlive-babelbib-svn25245.1.31-33.fc25.1.noarch
texlive-footmisc-svn23330.5.5b-33.fc25.1.noarch
texlive-makeindex-svn40768-33.fc25.1.noarch
texlive-plain-svn40274-33.fc25.1.noarch
texlive-texconfig-bin-svn29741.0-33.20160520.fc25.1.noarch
texlive-zapfding-svn31835.0-33.fc25.1.noarch
texlive-microtype-svn41127-33.fc25.1.noarch
texlive-bookman-svn31835.0-33.fc25.1.noarch
texlive-dvisvgm-def-svn41011-33.fc25.1.noarch
texlive-finstrut-svn21719.0.5-33.fc25.1.noarch
texlive-hyph-utf8-svn41189-33.fc25.1.noarch
texlive-lualibs-svn40370-33.fc25.1.noarch
python2-hawkey-0.6.4-3.fc25.s390x
elfutils-libelf-0.169-1.fc25.s390x
libnl3-3.2.29-3.fc25.s390x
gstreamer1-1.10.5-1.fc25.s390x
polkit-libs-0.113-8.fc25.s390x
libtirpc-1.0.2-0.fc25.s390x
libteam-1.27-1.fc25.s390x
python3-pyasn1-0.2.3-1.fc25.noarch
perl-File-Path-2.12-366.fc25.noarch
mesa-libwayland-egl-devel-17.0.5-3.fc25.s390x
libacl-devel-2.2.52-13.fc25.s390x
lua-libs-5.3.4-3.fc25.s390x
quota-nls-4.03-8.fc25.noarch
ghostscript-x11-9.20-9.fc25.s390x
systemd-231-17.fc25.s390x
dhcp-common-4.3.5-3.fc25.noarch
vte291-devel-0.46.2-1.fc25.s390x
python-devel-2.7.13-2.fc25.s390x
elfutils-0.169-1.fc25.s390x
lua-5.3.4-3.fc25.s390x
python3-beautifulsoup4-4.6.0-1.fc25.noarch
libmicrohttpd-0.9.55-1.fc25.s390x
screen-4.6.1-1.fc25.s390x
strace-4.18-1.fc25.s390x
libstdc++-6.4.1-1.fc25.s390x
glusterfs-3.10.5-1.fc25.s390x
file-5.29-9.fc25.s390x
libgo-6.4.1-1.fc25.s390x
tar-1.29-4.fc25.s390x
subversion-libs-1.9.7-1.fc25.s390x
libglvnd-gles-0.2.999-24.20170818git8d4d03f.fc25.s390x
gdk-pixbuf2-modules-2.36.9-1.fc25.s390x
gcc-6.4.1-1.fc25.s390x
curl-7.51.0-9.fc25.s390x
pcre2-utf16-10.23-9.fc25.s390x
mariadb-config-10.1.25-1.fc25.s390x
libcurl-devel-7.51.0-9.fc25.s390x
gtk3-devel-3.22.17-2.fc25.s390x
krb5-devel-1.14.4-8.fc25.s390x
wpa_supplicant-2.6-3.fc25.s390x
fontawesome-fonts-web-4.7.0-1.fc25.noarch
python2-pygments-2.2.0-7.fc25.noarch
python2-babel-2.3.4-2.fc25.noarch
doxygen-1.8.13-9.fc25.s390x
nspr-devel-4.16.0-1.fc25.s390x
kernel-core-4.12.11-200.fc25.s390x
rpmlint-1.10-3.fc25.noarch
vim-enhanced-8.0.1030-1.fc25.s390x
openjpeg2-2.2.0-3.fc25.s390x
distribution-gpg-keys-1.15-1.fc25.noarch
texlive-mparhack-svn15878.1.4-33.fc25.1.noarch
texlive-pspicture-svn15878.0-33.fc25.1.noarch
texlive-soul-svn15878.2.4-33.fc25.1.noarch
texlive-trimspaces-svn15878.1.1-33.fc25.1.noarch
texlive-varwidth-svn24104.0.92-33.fc25.1.noarch
texlive-geometry-svn19716.5.6-33.fc25.1.noarch
texlive-memoir-svn41203-33.fc25.1.noarch
texlive-pgf-svn40966-33.fc25.1.noarch
texlive-pst-coil-svn37377.1.07-33.fc25.1.noarch
texlive-pst-plot-svn41242-33.fc25.1.noarch
texlive-latex-bin-svn41438-33.fc25.1.noarch
texlive-ucs-svn35853.2.2-33.fc25.1.noarch
texlive-ae-svn15878.1.4-33.fc25.1.noarch
texlive-xetex-bin-svn41091-33.20160520.fc25.1.s390x
fedora-upgrade-26.1-1.fc25.noarch
perl-Thread-Queue-3.12-1.fc25.noarch
cdparanoia-libs-10.2-21.fc24.s390x
ustr-1.0.4-21.fc24.s390x
libusb-0.1.5-7.fc24.s390x
readline-devel-6.3-8.fc24.s390x
chkconfig-1.8-1.fc25.s390x
avahi-libs-0.6.32-4.fc25.s390x
perl-Unicode-Normalize-1.25-365.fc25.s390x
perl-libnet-3.10-1.fc25.noarch
perl-podlators-4.09-1.fc25.noarch
dbus-python-1.2.4-2.fc25.s390x
libgnome-keyring-3.12.0-7.fc25.s390x
python-backports-1.0-8.fc25.s390x
python-pycparser-2.14-7.fc25.noarch
plymouth-scripts-0.9.3-0.6.20160620git0e65b86c.fc25.s390x
cronie-1.5.1-2.fc25.s390x
python2-librepo-1.7.18-3.fc25.s390x
libXv-1.0.11-1.fc25.s390x
python2-ndg_httpsclient-0.4.0-4.fc25.noarch
btrfs-progs-4.6.1-1.fc25.s390x
perl-Encode-2.88-5.fc25.s390x
cracklib-2.9.6-4.fc25.s390x
python3-dnf-plugin-system-upgrade-0.7.1-4.fc25.noarch
boost-random-1.60.0-10.fc25.s390x
libref_array-0.1.5-29.fc25.s390x
libXrender-devel-0.9.10-1.fc25.s390x
javapackages-tools-4.7.0-6.1.fc25.noarch
keyutils-1.5.9-8.fc24.s390x
libcom_err-devel-1.43.3-1.fc25.s390x
lzo-minilzo-2.08-8.fc24.s390x
libusbx-devel-1.0.21-1.fc25.s390x
virglrenderer-devel-0.5.0-1.20160411git61846f92f.fc25.s390x
acpica-tools-20160831-1.fc25.s390x
grep-2.27-2.fc25.s390x
dnf-conf-1.1.10-6.fc25.noarch
crypto-policies-20160921-4.gitf3018dd.fc25.noarch
libnfsidmap-0.27-1.fc25.s390x
SDL2-2.0.5-3.fc25.s390x
texlive-etex-pkg-svn39355-33.fc25.1.noarch
texlive-multido-svn18302.1.42-33.fc25.1.noarch
texlive-gsftopk-svn40768-33.fc25.1.noarch
texlive-pst-ovl-svn40873-33.fc25.1.noarch
texlive-ltabptch-svn17533.1.74d-33.fc25.1.noarch
texlive-cite-svn36428.5.5-33.fc25.1.noarch
texlive-fpl-svn15878.1.002-33.fc25.1.noarch
texlive-mathpazo-svn15878.1.003-33.fc25.1.noarch
texlive-rcs-svn15878.0-33.fc25.1.noarch
texlive-type1cm-svn21820.0-33.fc25.1.noarch
texlive-l3kernel-svn41246-33.fc25.1.noarch
texlive-hyperref-svn41396-33.fc25.1.noarch
texlive-pst-tree-svn24142.1.12-33.fc25.1.noarch
texlive-sansmathaccent-svn30187.0-33.fc25.1.noarch
texlive-dvipdfmx-bin-svn40273-33.20160520.fc25.1.s390x
texlive-zapfchan-svn31835.0-33.fc25.1.noarch
glib2-static-2.50.3-1.fc25.s390x
bash-completion-2.5-1.fc25.noarch
hyphen-2.8.8-4.fc24.s390x
python3-idna-2.5-1.fc25.noarch
less-481-7.fc25.s390x
rpmconf-base-1.0.19-1.fc25.noarch
gtk2-2.24.31-2.fc25.s390x
mesa-libgbm-17.0.5-3.fc25.s390x
nfs-utils-2.1.1-5.rc4.fc25.s390x
mc-4.8.19-5.fc25.s390x
pcre-static-8.41-1.fc25.s390x
bind-libs-9.10.5-2.P2.fc25.s390x
libproxy-0.4.15-2.fc25.s390x
file-libs-5.29-9.fc25.s390x
glibc-devel-2.24-10.fc25.s390x
glusterfs-server-3.10.5-1.fc25.s390x
git-core-doc-2.9.5-1.fc25.s390x
python2-smmap-2.0.3-1.fc25.noarch
glusterfs-api-devel-3.10.5-1.fc25.s390x
gcc-gdb-plugin-6.4.1-1.fc25.s390x
python3-magic-5.29-9.fc25.noarch
GeoIP-GeoLite-data-2017.07-1.fc25.noarch
python2-funcsigs-1.0.2-2.fc25.noarch
dos2unix-7.3.4-1.fc25.s390x
gnutls-c++-3.5.15-1.fc25.s390x
nss-tools-3.32.0-1.1.fc25.s390x
gpg-pubkey-a29cb19c-53bcbba6
m4-1.4.17-9.fc24.s390x
liblockfile-1.09-4.fc24.s390x
sg3_utils-1.41-3.fc24.s390x
libXinerama-1.1.3-6.fc24.s390x
libXft-2.3.2-4.fc24.s390x
tcp_wrappers-libs-7.6-83.fc25.s390x
perl-Text-Tabs+Wrap-2013.0523-365.fc25.noarch
perl-Error-0.17024-7.fc25.noarch
perl-Term-Cap-1.17-365.fc25.noarch
perl-Pod-Usage-1.69-1.fc25.noarch
device-mapper-persistent-data-0.6.3-1.fc25.s390x
python3-six-1.10.0-3.fc25.noarch
python3-pysocks-1.5.6-5.fc25.noarch
python-chardet-2.3.0-1.fc25.noarch
python2-cffi-1.7.0-2.fc25.s390x
gc-devel-7.4.4-1.fc25.s390x
plymouth-0.9.3-0.6.20160620git0e65b86c.fc25.s390x
ebtables-2.0.10-21.fc25.s390x
python3-librepo-1.7.18-3.fc25.s390x
at-spi2-atk-2.22.0-1.fc25.s390x
avahi-autoipd-0.6.32-4.fc25.s390x
pyparsing-2.1.10-1.fc25.noarch
python3-pyparsing-2.1.10-1.fc25.noarch
libcollection-0.7.0-29.fc25.s390x
libcephfs-devel-10.2.4-2.fc25.s390x
libXdamage-devel-1.1.4-8.fc24.s390x
libverto-devel-0.2.6-6.fc24.s390x
snappy-1.1.3-2.fc24.s390x
cairo-gobject-devel-1.14.8-1.fc25.s390x
cyrus-sasl-devel-2.1.26-26.2.fc24.s390x
libXi-1.7.9-1.fc25.s390x
texlive-base-2016-33.20160520.fc25.noarch
texlive-booktabs-svn40846-33.fc25.1.noarch
texlive-lm-svn28119.2.004-33.fc25.1.noarch
texlive-gsftopk-bin-svn40473-33.20160520.fc25.1.s390x
texlive-tex-svn40793-33.fc25.1.noarch
texlive-fancyref-svn15878.0.9c-33.fc25.1.noarch
texlive-chngcntr-svn17157.1.0a-33.fc25.1.noarch
texlive-fix2col-svn38770-33.fc25.1.noarch
texlive-marginnote-svn41382-33.fc25.1.noarch
texlive-pxfonts-svn15878.0-33.fc25.1.noarch
texlive-txfonts-svn15878.0-33.fc25.1.noarch
texlive-l3packages-svn41246-33.fc25.1.noarch
texlive-oberdiek-svn41346-33.fc25.1.noarch
texlive-pst-tools-svn34067.0.05-33.fc25.1.noarch
texlive-tex-gyre-svn18651.2.004-33.fc25.1.noarch
texlive-dvipdfmx-svn41149-33.fc25.1.noarch
texlive-collection-fontsrecommended-svn35830.0-33.20160520.fc25.1.noarch
libcacard-devel-2.5.3-1.fc25.s390x
ykpers-1.18.0-2.fc25.s390x
python2-idna-2.5-1.fc25.noarch
policycoreutils-2.5-20.fc25.s390x
libgcrypt-1.7.8-1.fc25.s390x
pcre-8.41-1.fc25.s390x
GeoIP-1.6.11-1.fc25.s390x
ghostscript-core-9.20-9.fc25.s390x
python3-cffi-1.7.0-2.fc25.s390x
json-c-0.12.1-2.fc25.s390x
vte291-0.46.2-1.fc25.s390x
gssproxy-0.7.0-9.fc25.s390x
systemtap-3.1-5.fc25.s390x
mesa-libgbm-devel-17.0.5-3.fc25.s390x
libgusb-0.2.10-1.fc25.s390x
kernel-modules-4.12.9-200.fc25.s390x
sqlite-3.14.2-3.fc25.s390x
perl-Git-2.9.5-1.fc25.noarch
python2-gitdb-2.0.2-1.fc25.noarch
libglvnd-devel-0.2.999-24.20170818git8d4d03f.fc25.s390x
gcc-c++-6.4.1-1.fc25.s390x
python-magic-5.29-9.fc25.noarch
kernel-devel-4.12.9-200.fc25.s390x
python2-mock-2.0.0-2.fc25.noarch
nspr-4.16.0-1.fc25.s390x
python3-libs-3.5.4-1.fc25.s390x
system-python-3.5.4-1.fc25.s390x
python-async-0.6.1-9.fc22.s390x
dejavu-sans-mono-fonts-2.35-3.fc24.noarch
popt-1.16-7.fc24.s390x
cyrus-sasl-lib-2.1.26-26.2.fc24.s390x
xz-5.2.2-2.fc24.s390x
libpipeline-1.4.1-2.fc24.s390x
pinentry-0.9.7-2.fc24.s390x
pth-2.0.7-27.fc24.s390x
libsepol-2.5-10.fc25.s390x
libxcb-1.12-1.fc25.s390x
perl-Getopt-Long-2.49.1-1.fc25.noarch
avahi-glib-0.6.32-4.fc25.s390x
python3-pip-8.1.2-2.fc25.noarch
python3-libcomps-0.1.7-5.fc25.s390x
python-slip-0.6.4-4.fc25.noarch
python2-libcomps-0.1.7-5.fc25.s390x
gc-7.4.4-1.fc25.s390x
s390utils-cmsfs-1.36.0-1.fc25.s390x
newt-python-0.52.19-2.fc25.s390x
qt5-srpm-macros-5.7.1-1.fc25.noarch
device-mapper-event-1.02.136-3.fc25.s390x
perl-Class-Inspector-1.31-2.fc25.noarch
libbasicobjects-0.1.1-29.fc25.s390x
libradosstriper1-10.2.4-2.fc25.s390x
libXxf86vm-devel-1.1.4-3.fc24.s390x
zziplib-0.13.62-7.fc24.s390x
libpaper-1.1.24-12.fc24.s390x
libini_config-1.3.0-29.fc25.s390x
snappy-devel-1.1.3-2.fc24.s390x
libcap-ng-devel-0.7.8-1.fc25.s390x
libxkbcommon-devel-0.7.1-1.fc25.s390x
openssl-libs-1.0.2k-1.fc25.s390x
util-linux-2.28.2-2.fc25.s390x
texlive-etoolbox-svn38031.2.2a-33.fc25.1.noarch
texlive-dvips-svn41149-33.fc25.1.noarch
texlive-latexconfig-svn40274-33.fc25.1.noarch
texlive-tex-ini-files-svn40533-33.fc25.1.noarch
texlive-qstest-svn15878.0-33.fc25.1.noarch
texlive-cmap-svn41168-33.fc25.1.noarch
texlive-luatex-bin-svn41091-33.20160520.fc25.1.s390x
texlive-mflogo-svn38628-33.fc25.1.noarch
texlive-sansmath-svn17997.1.1-33.fc25.1.noarch
texlive-unicode-data-svn39808-33.fc25.1.noarch
texlive-luaotfload-bin-svn34647.0-33.20160520.fc25.1.noarch
texlive-listings-svn37534.1.6-33.fc25.1.noarch
texlive-pstricks-svn41321-33.fc25.1.noarch
texlive-metalogo-svn18611.0.12-33.fc25.1.noarch
texlive-collection-latex-svn41011-33.20160520.fc25.1.noarch
python2-dnf-plugins-core-0.1.21-5.fc25.noarch
xkeyboard-config-2.20-2.fc25.noarch
perl-Test-Harness-3.39-1.fc25.noarch
systemd-libs-231-17.fc25.s390x
python3-pycparser-2.14-7.fc25.noarch
kernel-devel-4.11.10-200.fc25.s390x
gsm-1.0.17-1.fc25.s390x
python-2.7.13-2.fc25.s390x
kernel-4.11.10-200.fc25.s390x
rpmconf-1.0.19-1.fc25.noarch
teamd-1.27-1.fc25.s390x
jasper-libs-1.900.13-4.fc25.s390x
glusterfs-libs-3.10.5-1.fc25.s390x
libcrypt-nss-2.24-10.fc25.s390x
emacs-common-25.2-3.fc25.s390x
libcurl-7.51.0-9.fc25.s390x
java-1.8.0-openjdk-1.8.0.144-5.b01.fc25.s390x
gcc-go-6.4.1-1.fc25.s390x
perl-XML-XPath-1.39-2.fc25.noarch
python2-sphinx_rtd_theme-0.1.9-2.fc24.noarch
libxml2-devel-2.9.4-2.fc25.s390x
nss-softokn-devel-3.32.0-1.2.fc25.s390x
nss-devel-3.32.0-1.1.fc25.s390x
libattr-2.4.47-16.fc24.s390x
libvisual-0.4.0-20.fc24.s390x
libpcap-1.7.4-2.fc24.s390x
libutempter-1.1.6-8.fc24.s390x
libgudev-230-3.fc24.s390x
popt-devel-1.16-7.fc24.s390x
hicolor-icon-theme-0.15-3.fc24.noarch
setup-2.10.4-1.fc25.noarch
bash-4.3.43-4.fc25.s390x
libjpeg-turbo-1.5.1-0.fc25.s390x
perl-Socket-2.024-1.fc25.s390x
perl-HTTP-Tiny-0.070-1.fc25.noarch
ipset-6.29-1.fc25.s390x
python2-setuptools-25.1.1-1.fc25.noarch
gsettings-desktop-schemas-3.22.0-1.fc25.s390x
python3-setuptools-25.1.1-1.fc25.noarch
python-slip-dbus-0.6.4-4.fc25.noarch
python2-ply-3.8-2.fc25.noarch
dtc-1.4.2-1.fc25.s390x
guile-2.0.13-1.fc25.s390x
cronie-anacron-1.5.1-2.fc25.s390x
libXtst-1.2.3-1.fc25.s390x
iso-codes-3.70-1.fc25.noarch
s390utils-1.36.0-1.fc25.s390x
python-backports-ssl_match_hostname-3.5.0.1-3.fc25.noarch
fedora-cert-0.6.0.1-1.fc25.noarch
dnf-plugin-system-upgrade-0.7.1-4.fc25.noarch
lvm2-2.02.167-3.fc25.s390x
libselinux-devel-2.5-13.fc25.s390x
perl-Time-Local-1.250-1.fc25.noarch
libradosstriper-devel-10.2.4-2.fc25.s390x
flac-libs-1.3.2-1.fc25.s390x
perl-Digest-1.17-366.fc25.noarch
teckit-2.5.1-15.fc24.s390x
libpath_utils-0.2.1-29.fc25.s390x
attr-2.4.47-16.fc24.s390x
usbredir-0.7.1-2.fc24.s390x
cairo-devel-1.14.8-1.fc25.s390x
lzo-devel-2.08-8.fc24.s390x
libcap-devel-2.25-2.fc25.s390x
libbsd-0.8.3-1.fc25.s390x
texlive-url-svn32528.3.4-33.fc25.1.noarch
texlive-dvips-bin-svn40987-33.20160520.fc25.1.s390x
texlive-index-svn24099.4.1beta-33.fc25.1.noarch
texlive-setspace-svn24881.6.7a-33.fc25.1.noarch
texlive-mathtools-svn38833-33.fc25.1.noarch
texlive-cm-svn32865.0-33.fc25.1.noarch
texlive-graphics-def-svn41879-33.fc25.1.noarch
texlive-mdwtools-svn15878.1.05.4-33.fc25.1.noarch
texlive-rsfs-svn15878.0-33.fc25.1.noarch
texlive-ucharcat-svn38907-33.fc25.1.noarch
texlive-fontspec-svn41262-33.fc25.1.noarch
texlive-showexpl-svn32737.v0.3l-33.fc25.1.noarch
texlive-pstricks-add-svn40744-33.fc25.1.noarch
texlive-beamer-svn36461.3.36-33.fc25.1.noarch
texlive-collection-basic-svn41149-33.20160520.fc25.1.noarch
xemacs-filesystem-21.5.34-20.20170124hgf412e9f093d4.fc25.noarch
hawkey-0.6.4-3.fc25.s390x
bluez-libs-5.44-1.fc25.s390x
audit-libs-2.7.7-1.fc25.s390x
iproute-4.11.0-1.fc25.s390x
libICE-1.0.9-9.fc25.s390x
python3-ply-3.8-2.fc25.noarch
perl-5.24.2-387.fc25.s390x
graphite2-1.3.10-1.fc25.s390x
vte-profile-0.46.2-1.fc25.s390x
python-libs-2.7.13-2.fc25.s390x
mesa-libGL-17.0.5-3.fc25.s390x
python2-pycurl-7.43.0-6.fc25.s390x
NetworkManager-1.4.4-5.fc25.s390x
mesa-libEGL-devel-17.0.5-3.fc25.s390x
mesa-libGLES-devel-17.0.5-3.fc25.s390x
hostname-3.15-8.fc25.s390x
glibc-headers-2.24-10.fc25.s390x
glusterfs-cli-3.10.5-1.fc25.s390x
git-core-2.9.5-1.fc25.s390x
gcc-gfortran-6.4.1-1.fc25.s390x
webkitgtk4-plugin-process-gtk2-2.16.6-1.fc25.s390x
perl-Module-CoreList-5.20170821-1.fc25.noarch
python2-pbr-1.10.0-1.fc25.noarch
libtool-2.4.6-14.fc25.s390x
gnutls-dane-3.5.15-1.fc25.s390x
kernel-4.12.11-200.fc25.s390x
gpg-pubkey-a0a7badb-52844296
readline-6.3-8.fc24.s390x
cpio-2.12-3.fc24.s390x
libXcomposite-0.4.4-8.fc24.s390x
procps-ng-3.3.10-11.fc24.s390x
GConf2-3.2.6-16.fc24.s390x
xz-devel-5.2.2-2.fc24.s390x
fedora-logos-22.0.0-3.fc24.s390x
gpg-pubkey-e372e838-56fd7943
kmod-libs-23-1.fc25.s390x
perl-parent-0.236-1.fc25.noarch
perl-TermReadKey-2.37-1.fc25.s390x
ncurses-c++-libs-6.0-6.20160709.fc25.s390x
gzip-1.8-1.fc25.s390x
python3-gobject-base-3.22.0-1.fc25.s390x
python2-yubico-1.3.2-3.fc25.noarch
s390utils-ziomon-1.36.0-1.fc25.s390x
librepo-1.7.18-3.fc25.s390x
gnat-srpm-macros-4-1.fc25.noarch
python-decoratortools-1.8-12.fc25.noarch
m17n-db-1.7.0-7.fc25.noarch
e2fsprogs-libs-1.43.3-1.fc25.s390x
libvorbis-1.3.5-1.fc25.s390x
npth-1.3-1.fc25.s390x
libcephfs1-10.2.4-2.fc25.s390x
wayland-devel-1.12.0-1.fc25.s390x
libxcb-devel-1.12-1.fc25.s390x
perl-encoding-2.19-5.fc25.s390x
python3-cssselect-0.9.2-1.fc25.noarch
gettext-libs-0.19.8.1-3.fc25.s390x
at-spi2-atk-devel-2.22.0-1.fc25.s390x
virglrenderer-0.5.0-1.20160411git61846f92f.fc25.s390x
pixman-devel-0.34.0-2.fc24.s390x
libnfs-devel-1.9.8-2.fc24.s390x
libblkid-2.28.2-2.fc25.s390x
glib2-devel-2.50.3-1.fc25.s390x
texlive-ifxetex-svn19685.0.5-33.fc25.1.noarch
texlive-caption-svn41409-33.fc25.1.noarch
texlive-float-svn15878.1.3d-33.fc25.1.noarch
texlive-pdftex-def-svn22653.0.06d-33.fc25.1.noarch
texlive-xdvi-bin-svn40750-33.20160520.fc25.1.s390x
texlive-beton-svn15878.0-33.fc25.1.noarch
texlive-filecontents-svn24250.1.3-33.fc25.1.noarch
texlive-lm-math-svn36915.1.959-33.fc25.1.noarch
texlive-pslatex-svn16416.0-33.fc25.1.noarch
texlive-times-svn35058.0-33.fc25.1.noarch
texlive-breakurl-svn29901.1.40-33.fc25.1.noarch
texlive-filehook-svn24280.0.5d-33.fc25.1.noarch
texlive-pst-pdf-svn31660.1.1v-33.fc25.1.noarch
texlive-seminar-svn34011.1.62-33.fc25.1.noarch
texlive-xetexconfig-svn41133-33.fc25.1.noarch
python-rpm-macros-3-12.fc25.noarch
nss-pem-1.0.3-3.fc25.s390x
at-spi2-core-2.22.1-1.fc25.s390x
perl-Scalar-List-Utils-1.48-1.fc25.s390x
libtasn1-devel-4.12-1.fc25.s390x
python3-koji-1.13.0-2.fc25.noarch
opus-1.1.5-1.fc25.s390x
elfutils-libs-0.169-1.fc25.s390x
kernel-core-4.11.10-200.fc25.s390x
systemd-container-231-17.fc25.s390x
sudo-1.8.20p2-1.fc25.s390x
libicu-devel-57.1-5.fc25.s390x
js-jquery-2.2.4-3.fc25.noarch
krb5-libs-1.14.4-8.fc25.s390x
apr-1.6.2-1.fc25.s390x
dbus-1.11.16-1.fc25.s390x
libdrm-2.4.82-1.fc25.s390x
pcre2-utf32-10.23-9.fc25.s390x
copy-jdk-configs-2.3-1.fc25.noarch
libdrm-devel-2.4.82-1.fc25.s390x
krb5-workstation-1.14.4-8.fc25.s390x
python3-sssdconfig-1.15.3-1.fc25.noarch
python2-docutils-0.13.1-3.fc25.noarch
graphviz-2.38.0-39.fc25.s390x
kernel-modules-4.12.11-200.fc25.s390x
fedpkg-1.29-3.fc25.noarch
mock-core-configs-27.4-1.fc25.noarch
=== TEST BEGIN ===
Using CC: /home/fam/bin/cc
Install prefix /var/tmp/patchew-tester-tmp-w75fwes8/src/install
BIOS directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/share/qemu
firmware path /var/tmp/patchew-tester-tmp-w75fwes8/src/install/share/qemu-firmware
binary directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/bin
library directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/lib
module directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/lib/qemu
libexec directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/libexec
include directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/include
config directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/etc
local state directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/var
Manual directory /var/tmp/patchew-tester-tmp-w75fwes8/src/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /var/tmp/patchew-tester-tmp-w75fwes8/src
GIT binary git
GIT submodules ui/keycodemapdb capstone
C compiler /home/fam/bin/cc
Host C compiler cc
C++ compiler c++
Objective-C compiler /home/fam/bin/cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -Werror -DHAS_LIBSSH2_SFTP_FSYNC -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -DNCURSES_WIDECHAR -D_GNU_SOURCE -m64 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-shift-negative-value -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -I/usr/include/p11-kit-1 -I/usr/include/libpng16 -I/usr/include/libdrm -I$(SRC_PATH)/capstone/include
LDFLAGS -Wl,--warn-common -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU s390x
host big endian yes
target list aarch64-softmmu alpha-softmmu arm-softmmu cris-softmmu i386-softmmu lm32-softmmu m68k-softmmu microblazeel-softmmu microblaze-softmmu mips64el-softmmu mips64-softmmu mipsel-softmmu mips-softmmu moxie-softmmu nios2-softmmu or1k-softmmu ppc64-softmmu ppcemb-softmmu ppc-softmmu s390x-softmmu sh4eb-softmmu sh4-softmmu sparc64-softmmu sparc-softmmu tricore-softmmu unicore32-softmmu x86_64-softmmu xtensaeb-softmmu xtensa-softmmu aarch64-linux-user alpha-linux-user armeb-linux-user arm-linux-user cris-linux-user hppa-linux-user i386-linux-user m68k-linux-user microblazeel-linux-user microblaze-linux-user mips64el-linux-user mips64-linux-user mipsel-linux-user mips-linux-user mipsn32el-linux-user mipsn32-linux-user nios2-linux-user or1k-linux-user ppc64abi32-linux-user ppc64le-linux-user ppc64-linux-user ppc-linux-user s390x-linux-user sh4eb-linux-user sh4-linux-user sparc32plus-linux-user sparc64-linux-user sparc-linux-user tilegx-linux-user x86_64-linux-user
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
SDL support yes (2.0.5)
GTK support yes (3.22.17)
GTK GL support yes
VTE support yes (0.46.2)
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (3.3)
nettle kdf yes
libtasn1 yes
curses support yes
virgl support yes
curl support yes
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support yes
Multipath support no
VNC support yes
VNC SASL support yes
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support yes
bluez support yes
Documentation yes
PIE no
vde support no
netmap support no
Linux AIO support yes
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
TCG support yes
TCG debug enabled no
TCG interpreter no
RDMA support no
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support yes
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
vhost-user support yes
Trace backends log
spice support no
rbd support yes
xfsctl support no
smartcard support yes
libusb yes
usb net redir yes
OpenGL support yes
OpenGL dmabufs yes
libiscsi support yes
libnfs support yes
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support yes
coroutine backend ucontext
coroutine pool yes
debug stack usage no
crypto afalg no
GlusterFS support yes
gcov gcov
gcov enabled no
TPM support yes
libssh2 support yes
TPM passthrough no
TPM emulator yes
QOM debugging yes
Live block migration yes
lzo support yes
snappy support yes
bzip2 support yes
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
capstone git
GEN alpha-softmmu/config-devices.mak.tmp
GEN arm-softmmu/config-devices.mak.tmp
GEN aarch64-softmmu/config-devices.mak.tmp
GEN cris-softmmu/config-devices.mak.tmp
GEN cris-softmmu/config-devices.mak
GEN i386-softmmu/config-devices.mak.tmp
GEN arm-softmmu/config-devices.mak
GEN alpha-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN lm32-softmmu/config-devices.mak.tmp
GEN microblazeel-softmmu/config-devices.mak.tmp
GEN m68k-softmmu/config-devices.mak.tmp
GEN lm32-softmmu/config-devices.mak
GEN i386-softmmu/config-devices.mak
GEN microblaze-softmmu/config-devices.mak.tmp
GEN microblazeel-softmmu/config-devices.mak
GEN m68k-softmmu/config-devices.mak
GEN mips64el-softmmu/config-devices.mak.tmp
GEN mips64-softmmu/config-devices.mak.tmp
GEN mipsel-softmmu/config-devices.mak.tmp
GEN microblaze-softmmu/config-devices.mak
GEN mips-softmmu/config-devices.mak.tmp
GEN mips64el-softmmu/config-devices.mak
GEN moxie-softmmu/config-devices.mak.tmp
GEN mipsel-softmmu/config-devices.mak
GEN mips64-softmmu/config-devices.mak
GEN or1k-softmmu/config-devices.mak.tmp
GEN nios2-softmmu/config-devices.mak.tmp
GEN mips-softmmu/config-devices.mak
GEN ppc64-softmmu/config-devices.mak.tmp
GEN moxie-softmmu/config-devices.mak
GEN or1k-softmmu/config-devices.mak
GEN nios2-softmmu/config-devices.mak
GEN ppcemb-softmmu/config-devices.mak.tmp
GEN s390x-softmmu/config-devices.mak.tmp
GEN ppc-softmmu/config-devices.mak.tmp
GEN s390x-softmmu/config-devices.mak
GEN ppcemb-softmmu/config-devices.mak
GEN ppc64-softmmu/config-devices.mak
GEN sh4eb-softmmu/config-devices.mak.tmp
GEN sh4-softmmu/config-devices.mak.tmp
GEN sparc64-softmmu/config-devices.mak.tmp
GEN ppc-softmmu/config-devices.mak
GEN sparc-softmmu/config-devices.mak.tmp
GEN sparc64-softmmu/config-devices.mak
GEN sparc-softmmu/config-devices.mak
GEN sh4-softmmu/config-devices.mak
GEN tricore-softmmu/config-devices.mak.tmp
GEN unicore32-softmmu/config-devices.mak.tmp
GEN sh4eb-softmmu/config-devices.mak
GEN x86_64-softmmu/config-devices.mak.tmp
GEN xtensaeb-softmmu/config-devices.mak.tmp
GEN unicore32-softmmu/config-devices.mak
GEN tricore-softmmu/config-devices.mak
GEN xtensa-softmmu/config-devices.mak.tmp
GEN xtensaeb-softmmu/config-devices.mak
GEN aarch64-linux-user/config-devices.mak.tmp
GEN alpha-linux-user/config-devices.mak.tmp
GEN xtensa-softmmu/config-devices.mak
GEN x86_64-softmmu/config-devices.mak
GEN armeb-linux-user/config-devices.mak.tmp
GEN aarch64-linux-user/config-devices.mak
GEN alpha-linux-user/config-devices.mak
GEN arm-linux-user/config-devices.mak.tmp
GEN cris-linux-user/config-devices.mak.tmp
GEN hppa-linux-user/config-devices.mak.tmp
GEN armeb-linux-user/config-devices.mak
GEN arm-linux-user/config-devices.mak
GEN i386-linux-user/config-devices.mak.tmp
GEN cris-linux-user/config-devices.mak
GEN m68k-linux-user/config-devices.mak.tmp
GEN hppa-linux-user/config-devices.mak
GEN microblazeel-linux-user/config-devices.mak.tmp
GEN microblaze-linux-user/config-devices.mak.tmp
GEN i386-linux-user/config-devices.mak
GEN m68k-linux-user/config-devices.mak
GEN mips64el-linux-user/config-devices.mak.tmp
GEN mips64-linux-user/config-devices.mak.tmp
GEN microblazeel-linux-user/config-devices.mak
GEN microblaze-linux-user/config-devices.mak
GEN mipsel-linux-user/config-devices.mak.tmp
GEN mips64el-linux-user/config-devices.mak
GEN mips-linux-user/config-devices.mak.tmp
GEN mips64-linux-user/config-devices.mak
GEN mipsn32el-linux-user/config-devices.mak.tmp
GEN mipsel-linux-user/config-devices.mak
GEN mipsn32-linux-user/config-devices.mak.tmp
GEN mips-linux-user/config-devices.mak
GEN nios2-linux-user/config-devices.mak.tmp
GEN mipsn32el-linux-user/config-devices.mak
GEN or1k-linux-user/config-devices.mak.tmp
GEN ppc64abi32-linux-user/config-devices.mak.tmp
GEN mipsn32-linux-user/config-devices.mak
GEN nios2-linux-user/config-devices.mak
GEN ppc64le-linux-user/config-devices.mak.tmp
GEN or1k-linux-user/config-devices.mak
GEN ppc64-linux-user/config-devices.mak.tmp
GEN ppc-linux-user/config-devices.mak.tmp
GEN ppc64abi32-linux-user/config-devices.mak
GEN ppc64le-linux-user/config-devices.mak
GEN s390x-linux-user/config-devices.mak.tmp
GEN sh4eb-linux-user/config-devices.mak.tmp
GEN ppc-linux-user/config-devices.mak
GEN ppc64-linux-user/config-devices.mak
GEN sh4-linux-user/config-devices.mak.tmp
GEN sparc32plus-linux-user/config-devices.mak.tmp
GEN s390x-linux-user/config-devices.mak
GEN sh4eb-linux-user/config-devices.mak
GEN sparc64-linux-user/config-devices.mak.tmp
GEN sparc32plus-linux-user/config-devices.mak
GEN sparc-linux-user/config-devices.mak.tmp
GEN sh4-linux-user/config-devices.mak
GEN tilegx-linux-user/config-devices.mak.tmp
GEN x86_64-linux-user/config-devices.mak.tmp
GEN sparc64-linux-user/config-devices.mak
GEN sparc-linux-user/config-devices.mak
GEN tilegx-linux-user/config-devices.mak
GEN config-host.h
GEN x86_64-linux-user/config-devices.mak
GIT ui/keycodemapdb capstone
GEN qemu-options.def
GEN qmp-commands.h
GEN qapi-types.h
GEN qapi-visit.h
GEN qapi-event.h
GEN qmp-marshal.c
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.h
GEN qmp-introspect.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
Submodule 'capstone' (git://git.qemu.org/capstone.git) registered for path 'capstone'
Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb'
GEN module_block.h
Cloning into '/var/tmp/patchew-tester-tmp-w75fwes8/src/capstone'...
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN chardev/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN hw/ide/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN accel/tcg/trace.h
GEN accel/kvm/trace.h
GEN nbd/trace.h
GEN scsi/trace.h
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN chardev/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN hw/ide/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/ppc/trace.c
GEN target/s390x/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN accel/tcg/trace.c
GEN accel/kvm/trace.c
GEN nbd/trace.c
GEN scsi/trace.c
GEN config-all-devices.mak
Cloning into '/var/tmp/patchew-tester-tmp-w75fwes8/src/ui/keycodemapdb'...
GEN ui/input-keymap-qcode-to-qnum.c
GEN ui/input-keymap-linux-to-qcode.c
GEN ui/input-keymap-qnum-to-qcode.c
CC cs.o
CC utils.o
CC SStream.o
CC MCInstrDesc.o
CC MCRegisterInfo.o
CC arch/ARM/ARMDisassembler.o
CC arch/ARM/ARMInstPrinter.o
CC arch/ARM/ARMMapping.o
CC arch/ARM/ARMModule.o
CC arch/AArch64/AArch64BaseInfo.o
CC arch/AArch64/AArch64Disassembler.o
CC arch/AArch64/AArch64InstPrinter.o
CC arch/AArch64/AArch64Mapping.o
CC arch/AArch64/AArch64Module.o
CC arch/Mips/MipsDisassembler.o
CC arch/Mips/MipsInstPrinter.o
CC arch/Mips/MipsMapping.o
CC arch/Mips/MipsModule.o
CC arch/PowerPC/PPCDisassembler.o
CC arch/PowerPC/PPCInstPrinter.o
CC arch/PowerPC/PPCMapping.o
CC arch/PowerPC/PPCModule.o
CC arch/Sparc/SparcDisassembler.o
CC arch/Sparc/SparcInstPrinter.o
CC arch/Sparc/SparcMapping.o
CC arch/Sparc/SparcModule.o
CC arch/SystemZ/SystemZDisassembler.o
CC arch/SystemZ/SystemZInstPrinter.o
CC arch/SystemZ/SystemZMapping.o
CC arch/SystemZ/SystemZModule.o
CC arch/SystemZ/SystemZMCTargetDesc.o
CC arch/X86/X86DisassemblerDecoder.o
CC arch/X86/X86Disassembler.o
CC arch/X86/X86IntelInstPrinter.o
CC arch/X86/X86ATTInstPrinter.o
CC arch/X86/X86Mapping.o
CC arch/X86/X86Module.o
CC arch/XCore/XCoreDisassembler.o
CC arch/XCore/XCoreInstPrinter.o
CC arch/XCore/XCoreMapping.o
CC arch/XCore/XCoreModule.o
CC MCInst.o
AR libcapstone.a
ar: creating /var/tmp/patchew-tester-tmp-w75fwes8/src/build/capstone/libcapstone.a
make[1]: '/var/tmp/patchew-tester-tmp-w75fwes8/src/build/capstone/libcapstone.a' is up to date.
GEN docs/version.texi
GEN qemu-options.texi
GEN qemu-img-cmds.texi
GEN qemu-monitor.texi
CC tests/qemu-iotests/socket_scm_helper.o
GEN qemu-monitor-info.texi
GEN qemu-img.1
GEN qemu-nbd.8
GEN qemu-ga.8
GEN docs/interop/qemu-qmp-qapi.texi
GEN docs/interop/qemu-ga-qapi.texi
GEN docs/qemu-block-drivers.7
GEN fsdev/virtfs-proxy-helper.1
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qapi-visit.c
CC qmp-introspect.o
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qnum.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qbool.o
CC qobject/qlit.o
CC qobject/qjson.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-parser.o
CC qobject/json-streamer.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-posix.o
CC util/event_notifier-posix.o
CC util/compatfd.o
CC util/mmap-alloc.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/cacheinfo.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/qemu-config.o
CC util/iov.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/pagesize.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC util/stats64.o
CC util/systemd.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC chardev/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/usb/trace.o
CC hw/scsi/trace.o
CC hw/display/trace.o
CC hw/nvram/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc/trace.o
CC hw/isa/trace.o
CC hw/sd/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/xen/trace.o
CC hw/ide/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC accel/tcg/trace.o
CC accel/kvm/trace.o
CC nbd/trace.o
CC scsi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/is-daemonized.o
CC stubs/iothread-lock.o
CC stubs/linux-aio.o
CC stubs/machine-init-done.o
CC stubs/migr-blocker.o
CC stubs/change-state-handler.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/tpm.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/qmp_pc_dimm.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC stubs/pci-host-piix.o
CC qemu-keymap.o
CC ui/input-keymap.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC block.o
CC blockjob.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qcow2-bitmap.o
CC block/qed.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/qapi.o
CC block/snapshot.o
CC block/file-posix.o
CC block/linux-aio.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/iscsi-opts.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/throttle.o
CC block/crypto.o
CC nbd/server.o
CC nbd/common.o
CC nbd/client.o
CC scsi/utils.o
CC scsi/pr-manager.o
CC scsi/pr-manager-helper.o
CC block/iscsi.o
CC block/nfs.o
CC block/curl.o
CC block/rbd.o
CC block/gluster.o
CC block/ssh.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-nettle.o
CC crypto/hmac.o
CC crypto/aes.o
CC crypto/hmac-nettle.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/secret.o
CC crypto/random-gnutls.o
CC crypto/pbkdf.o
CC crypto/pbkdf-nettle.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
GEN qemu-img-cmds.h
CC qemu-io.o
CC fsdev/virtfs-proxy-helper.o
CC fsdev/9p-marshal.o
CC fsdev/9p-iov-marshal.o
CC scsi/qemu-pr-helper.o
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC bootdevice.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC qemu-seccomp.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/tpm.o
CC backends/rng-random.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/cryptodev.o
CC backends/hostmem-file.o
CC block/stream.o
CC backends/cryptodev-builtin.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC chardev/testdev.o
CC chardev/baum.o
CC disas/alpha.o
CC disas/arm.o
CXX disas/arm-a64.o
CC disas/cris.o
CC disas/hppa.o
CC disas/i386.o
CC disas/m68k.o
CC disas/microblaze.o
CC disas/mips.o
CC disas/nios2.o
CC disas/moxie.o
CC disas/ppc.o
CC disas/s390.o
CC disas/sh4.o
CC disas/sparc.o
CC disas/lm32.o
CXX disas/libvixl/vixl/utils.o
CXX disas/libvixl/vixl/compiler-intrinsics.o
CXX disas/libvixl/vixl/a64/decoder-a64.o
CXX disas/libvixl/vixl/a64/instructions-a64.o
CXX disas/libvixl/vixl/a64/disasm-a64.o
CC fsdev/qemu-fsdev.o
CC fsdev/qemu-fsdev-opts.o
CC fsdev/qemu-fsdev-throttle.o
CC fsdev/qemu-fsdev-dummy.o
CC hw/9pfs/9p.o
CC hw/9pfs/9p-util.o
CC hw/9pfs/9p-local.o
CC hw/9pfs/9p-xattr.o
CC hw/9pfs/9p-xattr-user.o
CC hw/9pfs/9p-posix-acl.o
CC hw/9pfs/coth.o
CC hw/9pfs/cofs.o
CC hw/9pfs/codir.o
CC hw/9pfs/coxattr.o
CC hw/9pfs/cofile.o
CC hw/9pfs/9p-synth.o
CC hw/9pfs/9p-handle.o
CC hw/9pfs/9p-proxy.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/cs4231.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/milkymist-ac97.o
CC hw/audio/soundhw.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/escc.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/xilinx_uartlite.o
CC hw/char/cadence_uart.o
CC hw/char/cmsdk-apb-uart.o
CC hw/char/etraxfs_ser.o
CC hw/char/debugcon.o
CC hw/char/grlib_apbuart.o
CC hw/char/imx_serial.o
CC hw/char/lm32_juart.o
CC hw/char/lm32_uart.o
CC hw/char/milkymist-uart.o
CC hw/char/sclpconsole.o
CC hw/char/sclpconsole-lm.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/nmi.o
CC hw/core/empty_slot.o
CC hw/core/stream.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/loader-fit.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/cpu/core.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/g364fb.o
CC hw/display/jazz_led.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vga-isa-mm.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/milkymist-vgafb.o
CC hw/display/tc6393xb.o
CC hw/display/milkymist-tmu2.o
CC hw/dma/puv3_dma.o
CC hw/dma/rc4030.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i82374.o
CC hw/dma/i8257.o
CC hw/dma/xilinx_axidma.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/dma/etraxfs_dma.o
CC hw/dma/sparc32_dma.o
CC hw/dma/sun4m_iommu.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/puv3_gpio.o
CC hw/gpio/zaurus.o
CC hw/gpio/mpc8xxx.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/cmd646.o
CC hw/ide/macio.o
CC hw/ide/mmio.o
CC hw/ide/via.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/ide/ahci-allwinner.o
CC hw/input/adb.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/heathrow_pic.o
CC hw/intc/i8259.o
CC hw/intc/i8259_common.o
CC hw/intc/pl190.o
CC hw/intc/puv3_intc.o
CC hw/intc/xilinx_intc.o
CC hw/intc/etraxfs_pic.o
CC hw/intc/imx_avic.o
CC hw/intc/lm32_pic.o
CC hw/intc/realview_gic.o
CC hw/intc/slavio_intctl.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/openpic.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/isa/i82378.o
CC hw/isa/pc87312.o
CC hw/isa/piix4.o
CC hw/isa/vt82c686.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/tmp421.o
CC hw/misc/debugexit.o
CC hw/misc/pc-testdev.o
CC hw/misc/sga.o
CC hw/misc/pci-testdev.o
CC hw/misc/edu.o
CC hw/misc/unimp.o
CC hw/misc/vmcoreinfo.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/misc/puv3_pm.o
CC hw/misc/macio/macio.o
CC hw/misc/macio/cuda.o
CC hw/misc/macio/mac_dbdma.o
CC hw/net/dp8393x.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/opencores_eth.o
CC hw/net/xgmac.o
CC hw/net/mipsnet.o
CC hw/net/xilinx_axienet.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/lance.o
CC hw/net/sunhme.o
CC hw/net/ftgmac100.o
CC hw/net/sungem.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/ds1225y.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/nvram/mac_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pcie_pci_bridge.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-bridge/dec.o
CC hw/pci-host/pam.o
CC hw/pci-host/prep.o
CC hw/pci-host/grackle.o
CC hw/pci-host/uninorth.o
CC hw/pci-host/ppce500.o
CC hw/pci-host/versatile.o
CC hw/pci-host/apb.o
CC hw/pci-host/bonito.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci-host/xilinx-pcie.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/ssi/mss-spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/m48t59.o
CC hw/timer/m48t59-isa.o
CC hw/timer/pl031.o
CC hw/timer/puv3_ost.o
CC hw/timer/twl92230.o
CC hw/timer/xilinx_timer.o
CC hw/timer/slavio_timer.o
CC hw/timer/etraxfs_timer.o
CC hw/timer/grlib_gptimer.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/lm32_timer.o
CC hw/timer/milkymist-sysctl.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/sun4v-rtc.o
CC hw/timer/cmsdk-apb-timer.o
CC hw/timer/mss-timer.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_emulator.o
CC hw/tpm/tpm_util.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-xhci-nec.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/ccid-card-passthru.o
CC hw/usb/ccid-card-emulated.o
CC hw/usb/dev-mtp.o
CC hw/usb/redirect.o
CC hw/usb/quirks.o
CC hw/usb/host-libusb.o
CC hw/usb/host-legacy.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/vhost-stub.o
CC hw/virtio/virtio-mmio.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_diag288.o
CC hw/watchdog/wdt_aspeed.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/channel.o
CC migration/savevm.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/vmstate-types.o
CC migration/page_cache.o
CC migration/qemu-file.o
CC migration/global_state.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/l2tpv3.o
CC net/vhost-user.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC net/tap.o
CC net/tap-linux.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC replay/replay-net.o
CC replay/replay-audio.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip6_output.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_input.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC slirp/ncsi.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/input.o
CC ui/qemu-pixman.o
CC ui/input-legacy.o
CC ui/input-linux.o
CC ui/sdl2.o
CC ui/sdl2-input.o
CC ui/sdl2-2d.o
CC ui/sdl2-gl.o
CC ui/x_keymap.o
CC ui/curses.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-auth-sasl.o
CC ui/vnc-ws.o
CC ui/vnc-jobs.o
CC ui/gtk.o
VERT ui/shader/texture-blit-vert.h
VERT ui/shader/texture-blit-flip-vert.h
FRAG ui/shader/texture-blit-frag.h
CC ui/console-gl.o
CC ui/egl-helpers.o
CC ui/egl-context.o
CC ui/egl-headless.o
CC ui/gtk-gl-area.o
CC chardev/char.o
CC chardev/char-fd.o
CC chardev/char-fe.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-null.o
CC chardev/char-parallel.o
CC chardev/char-pipe.o
CC chardev/char-pty.o
CC chardev/char-ringbuf.o
CC chardev/char-serial.o
CC chardev/char-socket.o
CC chardev/char-stdio.o
CC chardev/char-udp.o
CCAS s390-ccw/start.o
LINK tests/qemu-iotests/socket_scm_helper
CC s390-ccw/main.o
CC s390-ccw/bootmap.o
CC s390-ccw/sclp.o
CC s390-ccw/virtio.o
CC s390-ccw/virtio-scsi.o
CC s390-ccw/virtio-blkdev.o
s390-netboot.img not built since roms/SLOF/ is not available.
GEN qemu-doc.html
GEN qemu-doc.txt
GEN qemu.1
BUILD s390-ccw/s390-ccw.elf
STRIP s390-ccw/s390-ccw.img
GEN docs/interop/qemu-qmp-ref.html
GEN docs/interop/qemu-qmp-ref.txt
GEN docs/interop/qemu-ga-ref.html
GEN docs/interop/qemu-qmp-ref.7
GEN docs/interop/qemu-ga-ref.txt
GEN docs/interop/qemu-ga-ref.7
CC qga/commands.o
CC qga/guest-agent-command-state.o
CC qga/main.o
CC qga/commands-posix.o
CC qga/channel-posix.o
CC qga/qapi-generated/qga-qapi-types.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
AR libqemuutil.a
CC qemu-img.o
LINK qemu-io
LINK fsdev/virtfs-proxy-helper
LINK scsi/qemu-pr-helper
LINK qemu-bridge-helper
CC ui/shader.o
LINK qemu-ga
LINK qemu-keymap
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
GEN alpha-softmmu/hmp-commands.h
GEN alpha-softmmu/hmp-commands-info.h
GEN alpha-softmmu/config-target.h
GEN arm-softmmu/hmp-commands.h
GEN arm-softmmu/hmp-commands-info.h
GEN arm-softmmu/config-target.h
CC alpha-softmmu/exec.o
GEN cris-softmmu/hmp-commands.h
GEN aarch64-softmmu/hmp-commands.h
CC arm-softmmu/exec.o
GEN cris-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/config-target.h
CC aarch64-softmmu/exec.o
GEN cris-softmmu/config-target.h
CC cris-softmmu/exec.o
CC alpha-softmmu/tcg/tcg.o
CC arm-softmmu/tcg/tcg.o
CC aarch64-softmmu/tcg/tcg.o
CC cris-softmmu/tcg/tcg.o
CC alpha-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/tcg/tcg-op.o
CC arm-softmmu/tcg/tcg-op.o
CC cris-softmmu/tcg/tcg-op.o
CC alpha-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:11: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-w75fwes8/src/rules.mak:66: recipe for target 'tcg/tcg-op-vec.o' failed
make[1]: *** [tcg/tcg-op-vec.o] Error 1
Makefile:383: recipe for target 'subdir-alpha-softmmu' failed
make: *** [subdir-alpha-softmmu] Error 2
make: *** Waiting for unfinished jobs....
CC aarch64-softmmu/tcg/tcg-op-vec.o
CC cris-softmmu/tcg/tcg-op-vec.o
CC arm-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:11: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-w75fwes8/src/rules.mak:66: recipe for target 'tcg/tcg-op-vec.o' failed
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC aarch64-softmmu/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:11: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-w75fwes8/src/rules.mak:66: recipe for target 'tcg/tcg-op-vec.o' failed
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
Makefile:383: recipe for target 'subdir-cris-softmmu' failed
make: *** [subdir-cris-softmmu] Error 2
CC arm-softmmu/tcg/tcg-op-gvec.o
CC arm-softmmu/tcg/tcg-common.o
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:11: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
can = tcg_can_emit_vec_op(opc, type, vece);
^~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-w75fwes8/src/rules.mak:66: recipe for target 'tcg/tcg-op-vec.o' failed
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC arm-softmmu/tcg/optimize.o
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-gvec.c:533:24: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^~~~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^~
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-w75fwes8/src/rules.mak:66: recipe for target 'tcg/tcg-op-gvec.o' failed
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
Makefile:383: recipe for target 'subdir-aarch64-softmmu' failed
make: *** [subdir-aarch64-softmmu] Error 2
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-gvec.c:533:24: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^~~~~~~~~~~~~~~~~~~
/var/tmp/patchew-tester-tmp-w75fwes8/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^~
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-w75fwes8/src/rules.mak:66: recipe for target 'tcg/tcg-op-gvec.o' failed
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
Makefile:383: recipe for target 'subdir-arm-softmmu' failed
make: *** [subdir-arm-softmmu] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (26 preceding siblings ...)
2017-11-21 22:10 ` [Qemu-devel] [PATCH v6 00/26] tcg: generic " no-reply
@ 2017-11-21 22:19 ` no-reply
2017-11-21 22:23 ` no-reply
` (2 subsequent siblings)
30 siblings, 0 replies; 36+ messages in thread
From: no-reply @ 2017-11-21 22:19 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
Type: series
Message-id: 20171121212534.5177-1-richard.henderson@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20171121212534.5177-1-richard.henderson@linaro.org -> patchew/20171121212534.5177-1-richard.henderson@linaro.org
Switched to a new branch 'test'
25cb597f1f tcg/aarch64: Add vector operations
3f5327e6d4 tcg/i386: Add vector operations/expansions for mul/extend
9842ec4914 target/arm: Use vector infrastructure for aa64 widening shifts
5baa8f3688 tcg: Add generic vector ops for extension
f31da52954 target/arm: Use vector infrastructure for aa64 multiplies
32e58411b7 tcg: Add generic vector ops for multiplication
02b126c0de tcg/i386: Add vector operations/expansions for shift/cmp/interleave
bd28e62249 target/arm: Use vector infrastructure for aa64 compares
c1bffde42b tcg: Add generic vector ops for comparisons
c6dfe9f8f3 target/arm: Use vector infrastructure for aa64 constant shifts
692cd8553b tcg: Add generic vector ops for constant shifts
77a9e02822 target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
8b8ba000ae tcg: Add generic vector ops for interleave
e5c9bc047b tcg: Add tcg_expand_vec_op and tcg-target.opc.h
8f2687485e tcg/i386: Add vector operations
2895593422 target/arm: Use vector infrastructure for aa64 dup/movi
75b6cdbaa6 target/arm: Use vector infrastructure for aa64 mov/not/neg
01af1be046 target/arm: Use vector infrastructure for aa64 add/sub/logic
f368c49794 target/arm: Align vector registers
0870bb2a3c tcg: Add tcg_signed_cond
0ac77ecb27 tcg: Allow multiple word entries into the constant pool
729ef7471e tcg: Add generic vector expanders
b0b5925754 tcg: Add types and basic operations for host vectors
cfb22624a4 tcg: Generalize TCGOp parameters
17d3aaf14a tcg: Dynamically allocate TCGOps
795ee71296 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*
=== OUTPUT BEGIN ===
Checking PATCH 1/26: tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*...
Checking PATCH 2/26: tcg: Dynamically allocate TCGOps...
ERROR: line over 90 characters
#64: FILE: include/qemu/queue.h:430:
+ (var) && ((prev_var) = (*(((struct headname *)((var)->field.tqe_prev))->tqh_last)), 1); \
ERROR: spaces prohibited around that ':' (ctx:WxW)
#538: FILE: tcg/tcg.h:575:
+ unsigned life : 16; /* 32 */
^
total: 2 errors, 0 warnings, 520 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/26: tcg: Generalize TCGOp parameters...
ERROR: spaces prohibited around that ':' (ctx:WxW)
#110: FILE: tcg/tcg.h:570:
+ unsigned param1 : 4; /* 12 */
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#111: FILE: tcg/tcg.h:571:
+ unsigned param2 : 4; /* 16 */
^
ERROR: Macros with complex values should be enclosed in parenthesis
#119: FILE: tcg/tcg.h:583:
+#define TCGOP_CALLI(X) (X)->param1
ERROR: Macros with complex values should be enclosed in parenthesis
#120: FILE: tcg/tcg.h:584:
+#define TCGOP_CALLO(X) (X)->param2
total: 4 errors, 0 warnings, 92 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/26: tcg: Add types and basic operations for host vectors...
ERROR: externs should be avoided in .c files
#137: FILE: tcg/tcg-op-vec.c:37:
+extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64);
ERROR: externs should be avoided in .c files
#138: FILE: tcg/tcg-op-vec.c:38:
+extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);
ERROR: Macros with complex values should be enclosed in parenthesis
#535: FILE: tcg/tcg-opc.h:209:
+#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
WARNING: line over 80 characters
#538: FILE: tcg/tcg-opc.h:212:
+DEF(movi_vec, 1, 0, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) /* vecl defines const args */
ERROR: Macros with complex values should be enclosed in parenthesis
#800: FILE: tcg/tcg.h:615:
+#define TCGOP_VECL(X) (X)->param1
ERROR: Macros with complex values should be enclosed in parenthesis
#801: FILE: tcg/tcg.h:616:
+#define TCGOP_VECE(X) (X)->param2
total: 5 errors, 1 warnings, 807 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/26: tcg: Add generic vector expanders...
ERROR: spaces required around that '&' (ctx:WxO)
#320: FILE: accel/tcg/tcg-runtime-gvec.c:281:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
^
ERROR: space prohibited after that '~' (ctx:OxW)
#320: FILE: accel/tcg/tcg-runtime-gvec.c:281:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
^
ERROR: spaces required around that '|' (ctx:WxO)
#331: FILE: accel/tcg/tcg-runtime-gvec.c:292:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
^
ERROR: space prohibited after that '~' (ctx:OxW)
#331: FILE: accel/tcg/tcg-runtime-gvec.c:292:
+ *(vec64 *)(d + i) = *(vec64 *)(a + i) |~ *(vec64 *)(b + i);
^
total: 4 errors, 0 warnings, 1642 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/26: tcg: Allow multiple word entries into the constant pool...
ERROR: spaces prohibited around that ':' (ctx:WxW)
#23: FILE: tcg/tcg-pool.inc.c:26:
+ int addend : 32;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#24: FILE: tcg/tcg-pool.inc.c:27:
+ int rtype : 16;
^
ERROR: spaces prohibited around that ':' (ctx:WxW)
#25: FILE: tcg/tcg-pool.inc.c:28:
+ int nlong : 16;
^
total: 3 errors, 0 warnings, 156 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/26: tcg: Add tcg_signed_cond...
Checking PATCH 8/26: target/arm: Align vector registers...
Checking PATCH 9/26: target/arm: Use vector infrastructure for aa64 add/sub/logic...
Checking PATCH 10/26: target/arm: Use vector infrastructure for aa64 mov/not/neg...
Checking PATCH 11/26: target/arm: Use vector infrastructure for aa64 dup/movi...
Checking PATCH 12/26: tcg/i386: Add vector operations...
Checking PATCH 13/26: tcg: Add tcg_expand_vec_op and tcg-target.opc.h...
Checking PATCH 14/26: tcg: Add generic vector ops for interleave...
ERROR: code indent should never use tabs
#41: FILE: accel/tcg/tcg-runtime-gvec.c:318:
+^I*(TYPE *)(d + 2 * i + 0) = *(TYPE *)(a + i); \$
ERROR: code indent should never use tabs
#42: FILE: accel/tcg/tcg-runtime-gvec.c:319:
+^I*(TYPE *)(d + 2 * i + sizeof(TYPE)) = *(TYPE *)(b + i); \$
ERROR: code indent should never use tabs
#87: FILE: accel/tcg/tcg-runtime-gvec.c:364:
+^I*(TYPE *)(d + i + 0) = ae; \$
ERROR: code indent should never use tabs
#88: FILE: accel/tcg/tcg-runtime-gvec.c:365:
+^I*(TYPE *)(d + i + sizeof(TYPE)) = be; \$
total: 4 errors, 0 warnings, 684 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 15/26: target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn...
Checking PATCH 16/26: tcg: Add generic vector ops for constant shifts...
Checking PATCH 17/26: target/arm: Use vector infrastructure for aa64 constant shifts...
Checking PATCH 18/26: tcg: Add generic vector ops for comparisons...
ERROR: spaces required around that '*' (ctx:WxV)
#24: FILE: accel/tcg/tcg-runtime-gvec.c:530:
+ *(TYPE *)(d + i) = *(TYPE *)(a + i) OP *(TYPE *)(b + i); \
^
ERROR: spaces required around that '==' (ctx:WxB)
#30: FILE: accel/tcg/tcg-runtime-gvec.c:536:
+ DO_CMP1(gvec_eq##SZ, vec##SZ, ==) \
^
ERROR: spaces required around that '!=' (ctx:WxB)
#31: FILE: accel/tcg/tcg-runtime-gvec.c:537:
+ DO_CMP1(gvec_ne##SZ, vec##SZ, !=) \
^
ERROR: spaces required around that '<' (ctx:WxB)
#32: FILE: accel/tcg/tcg-runtime-gvec.c:538:
+ DO_CMP1(gvec_lt##SZ, svec##SZ, <) \
^
ERROR: spaces required around that '<=' (ctx:WxB)
#33: FILE: accel/tcg/tcg-runtime-gvec.c:539:
+ DO_CMP1(gvec_le##SZ, svec##SZ, <=) \
^
ERROR: spaces required around that '<' (ctx:WxB)
#34: FILE: accel/tcg/tcg-runtime-gvec.c:540:
+ DO_CMP1(gvec_ltu##SZ, vec##SZ, <) \
^
ERROR: spaces required around that '<=' (ctx:WxB)
#35: FILE: accel/tcg/tcg-runtime-gvec.c:541:
+ DO_CMP1(gvec_leu##SZ, vec##SZ, <=)
^
ERROR: space prohibited after that '&&' (ctx:ExW)
#247: FILE: tcg/tcg-op-gvec.c:1775:
+ && (TCG_TARGET_REG_BITS == 32 || vece != MO_64)
^
total: 8 errors, 0 warnings, 356 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 19/26: target/arm: Use vector infrastructure for aa64 compares...
Checking PATCH 20/26: tcg/i386: Add vector operations/expansions for shift/cmp/interleave...
Checking PATCH 21/26: tcg: Add generic vector ops for multiplication...
Checking PATCH 22/26: target/arm: Use vector infrastructure for aa64 multiplies...
Checking PATCH 23/26: tcg: Add generic vector ops for extension...
Checking PATCH 24/26: target/arm: Use vector infrastructure for aa64 widening shifts...
Checking PATCH 25/26: tcg/i386: Add vector operations/expansions for mul/extend...
Checking PATCH 26/26: tcg/aarch64: Add vector operations...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (27 preceding siblings ...)
2017-11-21 22:19 ` no-reply
@ 2017-11-21 22:23 ` no-reply
2017-11-21 22:44 ` no-reply
2017-11-27 16:09 ` Timothy Pearson
30 siblings, 0 replies; 36+ messages in thread
From: no-reply @ 2017-11-21 22:23 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel
Hi,
This series failed automatic build test. Please find the testing commands and
their output below. If you have docker installed, you can probably reproduce it
locally.
Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
Type: series
Message-id: 20171121212534.5177-1-richard.henderson@linaro.org
=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-quick@centos6
time make docker-test-build@min-glib
time make docker-test-mingw@fedora
time make docker-test-block@fedora
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
25cb597f1f tcg/aarch64: Add vector operations
3f5327e6d4 tcg/i386: Add vector operations/expansions for mul/extend
9842ec4914 target/arm: Use vector infrastructure for aa64 widening shifts
5baa8f3688 tcg: Add generic vector ops for extension
f31da52954 target/arm: Use vector infrastructure for aa64 multiplies
32e58411b7 tcg: Add generic vector ops for multiplication
02b126c0de tcg/i386: Add vector operations/expansions for shift/cmp/interleave
bd28e62249 target/arm: Use vector infrastructure for aa64 compares
c1bffde42b tcg: Add generic vector ops for comparisons
c6dfe9f8f3 target/arm: Use vector infrastructure for aa64 constant shifts
692cd8553b tcg: Add generic vector ops for constant shifts
77a9e02822 target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
8b8ba000ae tcg: Add generic vector ops for interleave
e5c9bc047b tcg: Add tcg_expand_vec_op and tcg-target.opc.h
8f2687485e tcg/i386: Add vector operations
2895593422 target/arm: Use vector infrastructure for aa64 dup/movi
75b6cdbaa6 target/arm: Use vector infrastructure for aa64 mov/not/neg
01af1be046 target/arm: Use vector infrastructure for aa64 add/sub/logic
f368c49794 target/arm: Align vector registers
0870bb2a3c tcg: Add tcg_signed_cond
0ac77ecb27 tcg: Allow multiple word entries into the constant pool
729ef7471e tcg: Add generic vector expanders
b0b5925754 tcg: Add types and basic operations for host vectors
cfb22624a4 tcg: Generalize TCGOp parameters
17d3aaf14a tcg: Dynamically allocate TCGOps
795ee71296 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*
=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-5gdjpuh6/src/dtc'...
Submodule path 'dtc': checked out '558cd81bdd432769b59bff01240c44f82cfb1a9d'
BUILD centos6
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-5gdjpuh6/src'
GEN /var/tmp/patchew-tester-tmp-5gdjpuh6/src/docker-src.2017-11-21-17.20.00.19187/qemu.tar
Cloning into '/var/tmp/patchew-tester-tmp-5gdjpuh6/src/docker-src.2017-11-21-17.20.00.19187/qemu.tar.vroot'...
done.
Checking out files: 44% (2539/5669)
Checking out files: 45% (2552/5669)
Checking out files: 46% (2608/5669)
Checking out files: 47% (2665/5669)
Checking out files: 48% (2722/5669)
Checking out files: 49% (2778/5669)
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Checking out files: 51% (2892/5669)
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Checking out files: 54% (3062/5669)
Checking out files: 55% (3118/5669)
Checking out files: 56% (3175/5669)
Checking out files: 57% (3232/5669)
Checking out files: 58% (3289/5669)
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Checking out files: 60% (3402/5669)
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Checking out files: 99% (5613/5669)
Checking out files: 100% (5669/5669)
Checking out files: 100% (5669/5669), done.
Your branch is up-to-date with 'origin/test'.
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-5gdjpuh6/src/docker-src.2017-11-21-17.20.00.19187/qemu.tar.vroot/dtc'...
Submodule path 'dtc': checked out '558cd81bdd432769b59bff01240c44f82cfb1a9d'
Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into '/var/tmp/patchew-tester-tmp-5gdjpuh6/src/docker-src.2017-11-21-17.20.00.19187/qemu.tar.vroot/ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '10739aa26051a5d49d88132604539d3ed085e72e'
COPY RUNNER
RUN test-quick in qemu:centos6
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
bison-2.4.1-5.el6.x86_64
bzip2-devel-1.0.5-7.el6_0.x86_64
ccache-3.1.6-2.el6.x86_64
csnappy-devel-0-6.20150729gitd7bc683.el6.x86_64
flex-2.5.35-9.el6.x86_64
gcc-4.4.7-18.el6.x86_64
gettext-0.17-18.el6.x86_64
git-1.7.1-9.el6_9.x86_64
glib2-devel-2.28.8-9.el6.x86_64
libepoxy-devel-1.2-3.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
librdmacm-devel-1.0.21-0.el6.x86_64
lzo-devel-2.03-3.1.el6_5.1.x86_64
make-3.81-23.el6.x86_64
mesa-libEGL-devel-11.0.7-4.el6.x86_64
mesa-libgbm-devel-11.0.7-4.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
spice-glib-devel-0.26-8.el6.x86_64
spice-server-devel-0.12.4-16.el6.x86_64
tar-1.23-15.el6_8.x86_64
vte-devel-0.25.1-9.el6.x86_64
xen-devel-4.6.6-2.el6.x86_64
zlib-devel-1.2.3-29.el6.x86_64
Environment variables:
PACKAGES=bison bzip2-devel ccache csnappy-devel flex g++ gcc gettext git glib2-devel libepoxy-devel libfdt-devel librdmacm-devel lzo-devel make mesa-libEGL-devel mesa-libgbm-devel pixman-devel SDL-devel spice-glib-devel spice-server-devel tar vte-devel xen-devel zlib-devel
HOSTNAME=c82885d05ec3
MAKEFLAGS= -j8
J=8
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
TARGET_LIST=
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
FEATURES= dtc
DEBUG=
_=/usr/bin/env
Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/tmp/qemu-test/install
No C++ compiler available; disabling C++ specific optional code
Install prefix /tmp/qemu-test/install
BIOS directory /tmp/qemu-test/install/share/qemu
firmware path /tmp/qemu-test/install/share/qemu-firmware
binary directory /tmp/qemu-test/install/bin
library directory /tmp/qemu-test/install/lib
module directory /tmp/qemu-test/install/lib/qemu
libexec directory /tmp/qemu-test/install/libexec
include directory /tmp/qemu-test/install/include
config directory /tmp/qemu-test/install/etc
local state directory /tmp/qemu-test/install/var
Manual directory /tmp/qemu-test/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /tmp/qemu-test/src
GIT binary git
GIT submodules
C compiler cc
Host C compiler cc
C++ compiler
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -DNCURSES_WIDECHAR -fPIE -DPIE -m64 -mcx16 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-all -Wno-missing-braces -I/usr/include/libpng12 -I/usr/include/libdrm -I/usr/include/spice-server -I/usr/include/cacard -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -I/usr/include/pixman-1 -I/usr/include/nss3 -I/usr/include/nspr4 -I/usr/include/spice-1
LDFLAGS -Wl,--warn-common -Wl,-z,relro -Wl,-z,now -pie -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU x86_64
host big endian no
target list x86_64-softmmu aarch64-softmmu
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
SDL support yes (1.2.14)
GTK support yes (2.24.23)
GTK GL support no
VTE support yes (0.25.1)
TLS priority NORMAL
GNUTLS support no
GNUTLS rnd no
libgcrypt no
libgcrypt kdf no
nettle no
nettle kdf no
libtasn1 no
curses support yes
virgl support no
curl support no
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support no
Multipath support no
VNC support yes
VNC SASL support no
VNC JPEG support yes
VNC PNG support yes
xen support yes
xen ctrl version 40600
pv dom build no
brlapi support no
bluez support no
Documentation no
PIE yes
vde support no
netmap support no
Linux AIO support no
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
TCG support yes
TCG debug enabled no
TCG interpreter no
RDMA support yes
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support no
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
vhost-user support yes
Trace backends log
spice support yes (0.12.6/0.12.4)
rbd support no
xfsctl support no
smartcard support yes
libusb no
usb net redir no
OpenGL support yes
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
crypto afalg no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough yes
TPM emulator yes
QOM debugging yes
Live block migration yes
lzo support yes
snappy support no
bzip2 support yes
NUMA host support no
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
capstone no
mkdir -p dtc/libfdt
mkdir -p dtc/tests
GEN aarch64-softmmu/config-devices.mak.tmp
GEN x86_64-softmmu/config-devices.mak.tmp
GEN config-host.h
GEN qemu-options.def
GEN qapi-types.h
GEN qapi-visit.h
GEN qmp-commands.h
GEN qapi-event.h
GEN x86_64-softmmu/config-devices.mak
GEN qmp-marshal.c
GEN aarch64-softmmu/config-devices.mak
GEN qapi-types.c
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.h
GEN qmp-introspect.c
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers-wrappers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN module_block.h
GEN ui/input-keymap-linux-to-qcode.c
GEN ui/input-keymap-qcode-to-qnum.c
GEN ui/input-keymap-qnum-to-qcode.c
GEN tests/test-qapi-types.h
GEN tests/test-qapi-visit.h
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN trace-root.h
GEN util/trace.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN chardev/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN hw/ide/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN accel/tcg/trace.h
GEN accel/kvm/trace.h
GEN nbd/trace.h
GEN trace-root.c
GEN scsi/trace.h
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN chardev/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN hw/ide/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN accel/tcg/trace.c
GEN accel/kvm/trace.c
GEN nbd/trace.c
GEN scsi/trace.c
GEN config-all-devices.mak
DEP /tmp/qemu-test/src/dtc/tests/dumptrees.c
DEP /tmp/qemu-test/src/dtc/tests/trees.S
DEP /tmp/qemu-test/src/dtc/tests/testutils.c
DEP /tmp/qemu-test/src/dtc/tests/value-labels.c
DEP /tmp/qemu-test/src/dtc/tests/asm_tree_dump.c
DEP /tmp/qemu-test/src/dtc/tests/truncated_property.c
DEP /tmp/qemu-test/src/dtc/tests/overlay_bad_fixup.c
DEP /tmp/qemu-test/src/dtc/tests/check_path.c
DEP /tmp/qemu-test/src/dtc/tests/overlay.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/integer-expressions.c
DEP /tmp/qemu-test/src/dtc/tests/property_iterate.c
DEP /tmp/qemu-test/src/dtc/tests/utilfdt_test.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset_aliases.c
DEP /tmp/qemu-test/src/dtc/tests/add_subnode_with_nops.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_unordered.c
DEP /tmp/qemu-test/src/dtc/tests/dtb_reverse.c
DEP /tmp/qemu-test/src/dtc/tests/dtbs_equal_ordered.c
DEP /tmp/qemu-test/src/dtc/tests/extra-terminating-null.c
DEP /tmp/qemu-test/src/dtc/tests/incbin.c
DEP /tmp/qemu-test/src/dtc/tests/boot-cpuid.c
DEP /tmp/qemu-test/src/dtc/tests/phandle_format.c
DEP /tmp/qemu-test/src/dtc/tests/path-references.c
DEP /tmp/qemu-test/src/dtc/tests/references.c
DEP /tmp/qemu-test/src/dtc/tests/string_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/propname_escapes.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop2.c
DEP /tmp/qemu-test/src/dtc/tests/appendprop1.c
DEP /tmp/qemu-test/src/dtc/tests/del_node.c
DEP /tmp/qemu-test/src/dtc/tests/del_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop.c
DEP /tmp/qemu-test/src/dtc/tests/set_name.c
DEP /tmp/qemu-test/src/dtc/tests/rw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/open_pack.c
DEP /tmp/qemu-test/src/dtc/tests/nopulate.c
DEP /tmp/qemu-test/src/dtc/tests/mangle-layout.c
DEP /tmp/qemu-test/src/dtc/tests/move_and_save.c
DEP /tmp/qemu-test/src/dtc/tests/sw_tree1.c
DEP /tmp/qemu-test/src/dtc/tests/nop_node.c
DEP /tmp/qemu-test/src/dtc/tests/nop_property.c
DEP /tmp/qemu-test/src/dtc/tests/setprop_inplace.c
DEP /tmp/qemu-test/src/dtc/tests/stringlist.c
DEP /tmp/qemu-test/src/dtc/tests/addr_size_cells.c
DEP /tmp/qemu-test/src/dtc/tests/notfound.c
DEP /tmp/qemu-test/src/dtc/tests/sized_cells.c
DEP /tmp/qemu-test/src/dtc/tests/char_literal.c
DEP /tmp/qemu-test/src/dtc/tests/get_alias.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_check_compatible.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/parent_offset.c
DEP /tmp/qemu-test/src/dtc/tests/node_offset_by_prop_value.c
DEP /tmp/qemu-test/src/dtc/tests/supernode_atdepth_offset.c
DEP /tmp/qemu-test/src/dtc/tests/get_path.c
DEP /tmp/qemu-test/src/dtc/tests/get_phandle.c
DEP /tmp/qemu-test/src/dtc/tests/getprop.c
DEP /tmp/qemu-test/src/dtc/tests/get_name.c
DEP /tmp/qemu-test/src/dtc/tests/path_offset.c
DEP /tmp/qemu-test/src/dtc/tests/subnode_offset.c
DEP /tmp/qemu-test/src/dtc/tests/root_node.c
DEP /tmp/qemu-test/src/dtc/tests/find_property.c
DEP /tmp/qemu-test/src/dtc/tests/get_mem_rsv.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_overlay.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_addresses.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_empty_tree.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_strerror.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_sw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_wip.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_rw.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt_ro.c
DEP /tmp/qemu-test/src/dtc/libfdt/fdt.c
DEP /tmp/qemu-test/src/dtc/util.c
DEP /tmp/qemu-test/src/dtc/fdtput.c
DEP /tmp/qemu-test/src/dtc/fdtget.c
DEP /tmp/qemu-test/src/dtc/fdtdump.c
LEX convert-dtsv0-lexer.lex.c
BISON dtc-parser.tab.c
DEP /tmp/qemu-test/src/dtc/srcpos.c
LEX dtc-lexer.lex.c
DEP /tmp/qemu-test/src/dtc/treesource.c
DEP /tmp/qemu-test/src/dtc/livetree.c
DEP /tmp/qemu-test/src/dtc/flattree.c
DEP /tmp/qemu-test/src/dtc/fstree.c
DEP /tmp/qemu-test/src/dtc/dtc.c
DEP /tmp/qemu-test/src/dtc/data.c
DEP /tmp/qemu-test/src/dtc/checks.c
DEP convert-dtsv0-lexer.lex.c
DEP dtc-lexer.lex.c
DEP dtc-parser.tab.c
CHK version_gen.h
UPD version_gen.h
DEP /tmp/qemu-test/src/dtc/util.c
CC libfdt/fdt.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
mkdir -p dtc/libfdt
mkdir -p dtc/tests
CC tests/qemu-iotests/socket_scm_helper.o
GEN qga/qapi-generated/qga-qapi-types.h
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qapi-visit.c
CC qmp-introspect.o
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnull.o
CC qobject/qnum.o
CC qobject/qstring.o
CC qobject/qdict.o
CC qobject/qlist.o
CC qobject/qbool.o
CC qobject/qjson.o
CC qobject/qlit.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC qobject/json-parser.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC util/cutils.o
CC util/unicode.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/aiocb.o
CC util/async.o
CC util/thread-pool.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/aio-posix.o
CC util/compatfd.o
CC util/event_notifier-posix.o
CC util/mmap-alloc.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/qemu-thread-posix.o
CC util/memfd.o
CC util/envlist.o
CC util/path.o
CC util/module.o
CC util/host-utils.o
CC util/bitmap.o
CC util/bitops.o
CC util/hbitmap.o
CC util/fifo8.o
CC util/acl.o
CC util/cacheinfo.o
CC util/error.o
CC util/qemu-error.o
CC util/id.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/uuid.o
CC util/throttle.o
CC util/getauxval.o
CC util/readline.o
CC util/rcu.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/buffer.o
CC util/timed-average.o
CC util/log.o
CC util/base64.o
CC util/pagesize.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC util/stats64.o
CC util/systemd.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC chardev/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/misc/trace.o
CC hw/usb/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/dma/trace.o
CC hw/timer/trace.o
CC hw/sparc/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/arm/trace.o
CC hw/alpha/trace.o
CC hw/xen/trace.o
CC hw/ide/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/i386/trace.o
CC target/mips/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC accel/tcg/trace.o
CC accel/kvm/trace.o
CC nbd/trace.o
CC scsi/trace.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/fdset.o
CC stubs/error-printf.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/machine-init-done.o
CC stubs/change-state-handler.o
CC stubs/migr-blocker.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/replay.o
CC stubs/runstate-check.o
CC stubs/set-fd-handler.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/tpm.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/vmstate.o
CC stubs/qmp_pc_dimm.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/xen-hvm.o
CC stubs/pci-host-piix.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC block.o
CC blockjob.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/cloop.o
CC block/bochs.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-snapshot.o
CC block/qcow2-cache.o
CC block/qcow2-bitmap.o
CC block/qed.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/vhdx-endian.o
CC block/vhdx-log.o
CC block/quorum.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-posix.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/throttle.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC scsi/utils.o
CC scsi/pr-manager.o
CC scsi/pr-manager-helper.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-glib.o
CC crypto/hmac.o
CC crypto/hmac-glib.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlssession.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/secret.o
CC crypto/random-platform.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/pbkdf.o
CC crypto/afsplit.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-watch.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
GEN qemu-img-cmds.h
CC qemu-io.o
CC scsi/qemu-pr-helper.o
CC qemu-bridge-helper.o
CC blockdev.o
CC blockdev-nbd.o
CC bootdevice.o
CC iothread.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/spiceaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/rng-random.o
CC backends/tpm.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC block/stream.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC chardev/testdev.o
CC chardev/spice.o
CC disas/arm.o
CC disas/i386.o
CC fsdev/qemu-fsdev-dummy.o
CC fsdev/qemu-fsdev-opts.o
CC fsdev/qemu-fsdev-throttle.o
CC hw/acpi/core.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/pcspk.o
CC hw/audio/hda-codec.o
CC hw/audio/wm8750.o
CC hw/audio/pl041.o
CC hw/audio/lm4549.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/soundhw.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/nand.o
CC hw/block/xen_disk.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/pl011.o
CC hw/char/parallel.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/xen_console.o
CC hw/char/cadence_uart.o
CC hw/char/cmsdk-apb-uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/hotplug.o
CC hw/core/nmi.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/cpu/core.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/ssd0323.o
CC hw/display/xenfb.o
CC hw/display/vga-pci.o
CC hw/display/vga-isa.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/tc6393xb.o
CC hw/display/qxl.o
CC hw/display/qxl-logger.o
CC hw/display/qxl-render.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i8257.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/gpio/max7310.o
CC hw/gpio/pl061.o
CC hw/gpio/zaurus.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/ide/ahci-allwinner.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/tsc2005.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/imx_avic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/tmp421.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/edu.o
CC hw/misc/unimp.o
CC hw/misc/arm_l2x0.o
CC hw/misc/vmcoreinfo.o
CC hw/misc/a9scu.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/arm11scu.o
CC hw/net/xen_nic.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/pcnet.o
CC hw/net/e1000.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/xgmac.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/cadence_gem.o
CC hw/net/stellaris_enet.o
CC hw/net/ftgmac100.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pcie_pci_bridge.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-host/pam.o
CC hw/pci-host/versatile.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/ssi/mss-spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/cadence_ttc.o
CC hw/timer/ds1338.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/pl031.o
CC hw/timer/twl92230.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/cmsdk-apb-timer.o
CC hw/timer/aspeed_timer.o
CC hw/timer/mss-timer.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_passthrough.o
CC hw/tpm/tpm_util.o
CC hw/tpm/tpm_emulator.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-xhci-nec.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/ccid-card-passthru.o
CC hw/usb/ccid-card-emulated.o
CC hw/usb/dev-mtp.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_aspeed.o
CC hw/xen/xen_backend.o
CC hw/xen/xen_devconfig.o
CC hw/xen/xen_pvdev.o
CC hw/xen/xen-common.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/channel.o
CC migration/savevm.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/vmstate-types.o
CC migration/page_cache.o
CC migration/qemu-file.o
CC migration/global_state.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/rdma.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/dump.o
CC net/eth.o
CC net/l2tpv3.o
CC net/vhost-user.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC net/tap.o
CC net/tap-linux.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
/tmp/qemu-test/src/replay/replay-internal.c: In function 'replay_put_array':
/tmp/qemu-test/src/replay/replay-internal.c:65: warning: ignoring return value of 'fwrite', declared with attribute warn_unused_result
CC replay/replay-snapshot.o
CC replay/replay-net.o
CC replay/replay-audio.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_output.o
CC slirp/ip6_input.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/tcp_input.o
CC slirp/socket.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/udp6.o
CC slirp/bootp.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC slirp/ncsi.o
CC ui/keymaps.o
/tmp/qemu-test/src/slirp/tcp_input.c: In function 'tcp_input':
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_p' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_len' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_tos' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_id' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_off' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_ttl' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_sum' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_src.s_addr' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:219: warning: 'save_ip.ip_dst.s_addr' may be used uninitialized in this function
/tmp/qemu-test/src/slirp/tcp_input.c:220: warning: 'save_ip6.ip_nh' may be used uninitialized in this function
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/input-linux.o
CC ui/spice-core.o
CC ui/spice-input.o
CC ui/spice-display.o
CC ui/sdl.o
CC ui/sdl_zoom.o
CC ui/x_keymap.o
CC ui/curses.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-ws.o
CC ui/vnc-jobs.o
CC ui/gtk.o
VERT ui/shader/texture-blit-vert.h
VERT ui/shader/texture-blit-flip-vert.h
FRAG ui/shader/texture-blit-frag.h
CC ui/console-gl.o
CC ui/egl-context.o
CC ui/egl-helpers.o
CC ui/gtk-egl.o
CC chardev/char.o
CC chardev/char-fd.o
CC chardev/char-fe.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-parallel.o
CC chardev/char-null.o
CC chardev/char-pipe.o
CC chardev/char-pty.o
CC chardev/char-ringbuf.o
CC chardev/char-serial.o
CC chardev/char-socket.o
CC chardev/char-stdio.o
CC chardev/char-udp.o
AS optionrom/multiboot.o
AS optionrom/linuxboot.o
LINK tests/qemu-iotests/socket_scm_helper
CC optionrom/linuxboot_dma.o
CC qga/commands.o
CC qga/guest-agent-command-state.o
cc: unrecognized option '-no-integrated-as'
cc: unrecognized option '-no-integrated-as'
AS optionrom/kvmvapic.o
BUILD optionrom/multiboot.img
CC qga/main.o
BUILD optionrom/linuxboot.img
BUILD optionrom/linuxboot_dma.img
BUILD optionrom/kvmvapic.img
BUILD optionrom/multiboot.raw
CC qga/commands-posix.o
BUILD optionrom/linuxboot.raw
BUILD optionrom/linuxboot_dma.raw
BUILD optionrom/kvmvapic.raw
SIGN optionrom/multiboot.bin
SIGN optionrom/linuxboot.bin
SIGN optionrom/linuxboot_dma.bin
SIGN optionrom/kvmvapic.bin
CC qga/channel-posix.o
CC qga/qapi-generated/qga-qapi-types.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qmp-marshal.o
AR libqemuutil.a
CC qemu-img.o
CC ui/shader.o
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
LINK qemu-io
LINK scsi/qemu-pr-helper
LINK qemu-bridge-helper
LINK qemu-ga
In file included from /usr/include/gtk-2.0/gtk/gtk.h:235,
from /tmp/qemu-test/src/include/ui/gtk.h:10,
from /tmp/qemu-test/src/ui/gtk-egl.c:21:
/usr/include/gtk-2.0/gtk/gtkitemfactory.h:47: warning: function declaration isn't a prototype
LINK qemu-img
In file included from /usr/include/gtk-2.0/gtk/gtk.h:235,
from /tmp/qemu-test/src/include/ui/gtk.h:10,
from /tmp/qemu-test/src/ui/gtk.c:43:
/usr/include/gtk-2.0/gtk/gtkitemfactory.h:47: warning: function declaration isn't a prototype
GEN x86_64-softmmu/hmp-commands.h
GEN x86_64-softmmu/hmp-commands-info.h
GEN x86_64-softmmu/config-target.h
GEN aarch64-softmmu/hmp-commands.h
GEN aarch64-softmmu/config-target.h
GEN aarch64-softmmu/hmp-commands-info.h
CC x86_64-softmmu/tcg/tcg-op-vec.o
CC x86_64-softmmu/exec.o
CC x86_64-softmmu/tcg/tcg.o
CC x86_64-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/tcg/tcg-op-gvec.o
CC x86_64-softmmu/tcg/tcg-common.o
CC x86_64-softmmu/tcg/optimize.o
CC aarch64-softmmu/exec.o
CC x86_64-softmmu/fpu/softfloat.o
CC aarch64-softmmu/tcg/tcg.o
CC aarch64-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/disas.o
GEN x86_64-softmmu/gdbstub-xml.c
CC x86_64-softmmu/arch_init.o
CC x86_64-softmmu/cpus.o
CC x86_64-softmmu/monitor.o
CC x86_64-softmmu/gdbstub.o
CC aarch64-softmmu/tcg/tcg-op-vec.o
CC x86_64-softmmu/balloon.o
CC x86_64-softmmu/ioport.o
CC x86_64-softmmu/numa.o
CC x86_64-softmmu/qtest.o
CC aarch64-softmmu/tcg/tcg-op-gvec.o
CC aarch64-softmmu/tcg/tcg-common.o
CC aarch64-softmmu/tcg/optimize.o
CC x86_64-softmmu/memory.o
CC x86_64-softmmu/memory_mapping.o
CC aarch64-softmmu/fpu/softfloat.o
CC aarch64-softmmu/disas.o
CC x86_64-softmmu/dump.o
CC x86_64-softmmu/migration/ram.o
CC x86_64-softmmu/accel/accel.o
GEN aarch64-softmmu/gdbstub-xml.c
CC x86_64-softmmu/accel/kvm/kvm-all.o
CC aarch64-softmmu/arch_init.o
CC x86_64-softmmu/accel/stubs/hax-stub.o
CC aarch64-softmmu/cpus.o
CC x86_64-softmmu/accel/tcg/tcg-all.o
CC aarch64-softmmu/monitor.o
CC x86_64-softmmu/accel/tcg/cputlb.o
CC x86_64-softmmu/accel/tcg/tcg-runtime.o
CC aarch64-softmmu/gdbstub.o
CC x86_64-softmmu/accel/tcg/tcg-runtime-gvec.o
CC x86_64-softmmu/accel/tcg/cpu-exec.o
CC x86_64-softmmu/accel/tcg/cpu-exec-common.o
CC aarch64-softmmu/balloon.o
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl8i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:353: error: invalid operands to binary << (have 'vec8' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl16i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:365: error: invalid operands to binary << (have 'vec16' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl32i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:377: error: invalid operands to binary << (have 'vec32' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl64i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:389: error: invalid operands to binary << (have 'vec64' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr8i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:401: error: invalid operands to binary >> (have 'vec8' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr16i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:413: error: invalid operands to binary >> (have 'vec16' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr32i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:425: error: invalid operands to binary >> (have 'vec32' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr64i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:437: error: invalid operands to binary >> (have 'vec64' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar8i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:449: error: invalid operands to binary >> (have 'svec8' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar16i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:461: error: invalid operands to binary >> (have 'svec16' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar32i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:473: error: invalid operands to binary >> (have 'svec32' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar64i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:485: error: invalid operands to binary >> (have 'svec64' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary == (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary != (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary < (have 'svec8' and 'svec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary <= (have 'svec8' and 'svec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary < (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary <= (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary == (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary != (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary < (have 'svec16' and 'svec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary <= (have 'svec16' and 'svec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary < (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary <= (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary == (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary != (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary < (have 'svec32' and 'svec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary <= (have 'svec32' and 'svec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary < (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary <= (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary == (have 'vec64' and 'vec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary != (have 'vec64' and 'vec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary < (have 'svec64' and 'svec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary <= (have 'svec64' and 'svec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary < (have 'vec64' and 'vec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary <= (have 'vec64' and 'vec64')
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC aarch64-softmmu/ioport.o
CC aarch64-softmmu/numa.o
CC aarch64-softmmu/qtest.o
CC aarch64-softmmu/memory.o
CC aarch64-softmmu/memory_mapping.o
CC aarch64-softmmu/dump.o
CC aarch64-softmmu/migration/ram.o
CC aarch64-softmmu/accel/accel.o
CC aarch64-softmmu/accel/stubs/hax-stub.o
CC aarch64-softmmu/accel/stubs/kvm-stub.o
CC aarch64-softmmu/accel/tcg/tcg-all.o
CC aarch64-softmmu/accel/tcg/cputlb.o
CC aarch64-softmmu/accel/tcg/tcg-runtime.o
CC aarch64-softmmu/accel/tcg/tcg-runtime-gvec.o
make: *** [subdir-x86_64-softmmu] Error 2
make: *** Waiting for unfinished jobs....
CC aarch64-softmmu/accel/tcg/cpu-exec.o
CC aarch64-softmmu/accel/tcg/cpu-exec-common.o
CC aarch64-softmmu/accel/tcg/translate-all.o
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl8i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:353: error: invalid operands to binary << (have 'vec8' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl16i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:365: error: invalid operands to binary << (have 'vec16' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl32i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:377: error: invalid operands to binary << (have 'vec32' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shl64i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:389: error: invalid operands to binary << (have 'vec64' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr8i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:401: error: invalid operands to binary >> (have 'vec8' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr16i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:413: error: invalid operands to binary >> (have 'vec16' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr32i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:425: error: invalid operands to binary >> (have 'vec32' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_shr64i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:437: error: invalid operands to binary >> (have 'vec64' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar8i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:449: error: invalid operands to binary >> (have 'svec8' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar16i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:461: error: invalid operands to binary >> (have 'svec16' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar32i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:473: error: invalid operands to binary >> (have 'svec32' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_sar64i':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:485: error: invalid operands to binary >> (have 'svec64' and 'int')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary == (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary != (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary < (have 'svec8' and 'svec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary <= (have 'svec8' and 'svec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary < (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu8':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:587: error: invalid operands to binary <= (have 'vec8' and 'vec8')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary == (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary != (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary < (have 'svec16' and 'svec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary <= (have 'svec16' and 'svec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary < (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu16':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:588: error: invalid operands to binary <= (have 'vec16' and 'vec16')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary == (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary != (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary < (have 'svec32' and 'svec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary <= (have 'svec32' and 'svec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary < (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu32':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:589: error: invalid operands to binary <= (have 'vec32' and 'vec32')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_eq64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary == (have 'vec64' and 'vec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ne64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary != (have 'vec64' and 'vec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_lt64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary < (have 'svec64' and 'svec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_le64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary <= (have 'svec64' and 'svec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_ltu64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary < (have 'vec64' and 'vec64')
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c: In function 'helper_gvec_leu64':
/tmp/qemu-test/src/accel/tcg/tcg-runtime-gvec.c:590: error: invalid operands to binary <= (have 'vec64' and 'vec64')
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [subdir-aarch64-softmmu] Error 2
Traceback (most recent call last):
File "./tests/docker/docker.py", line 407, in <module>
sys.exit(main())
File "./tests/docker/docker.py", line 404, in main
return args.cmdobj.run(args, argv)
File "./tests/docker/docker.py", line 261, in run
return Docker().run(argv, args.keep, quiet=args.quiet)
File "./tests/docker/docker.py", line 229, in run
quiet=quiet)
File "./tests/docker/docker.py", line 147, in _do_check
return subprocess.check_call(self._command + cmd, **kwargs)
File "/usr/lib64/python2.7/subprocess.py", line 186, in check_call
raise CalledProcessError(retcode, cmd)
subprocess.CalledProcessError: Command '['docker', 'run', '--label', 'com.qemu.instance.uuid=23b8b4e8cf0a11e7b76e52540069c830', '-u', '0', '--security-opt', 'seccomp=unconfined', '--rm', '--net=none', '-e', 'TARGET_LIST=', '-e', 'EXTRA_CONFIGURE_OPTS=', '-e', 'V=', '-e', 'J=8', '-e', 'DEBUG=', '-e', 'SHOW_ENV=1', '-e', 'CCACHE_DIR=/var/tmp/ccache', '-v', '/root/.cache/qemu-docker-ccache:/var/tmp/ccache:z', '-v', '/var/tmp/patchew-tester-tmp-5gdjpuh6/src/docker-src.2017-11-21-17.20.00.19187:/var/tmp/qemu:z,ro', 'qemu:centos6', '/var/tmp/qemu/run', 'test-quick']' returned non-zero exit status 2
make[1]: *** [tests/docker/Makefile.include:129: docker-run] Error 1
make[1]: Leaving directory '/var/tmp/patchew-tester-tmp-5gdjpuh6/src'
make: *** [tests/docker/Makefile.include:163: docker-run-test-quick@centos6] Error 2
real 3m30.127s
user 0m4.169s
sys 0m4.551s
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (28 preceding siblings ...)
2017-11-21 22:23 ` no-reply
@ 2017-11-21 22:44 ` no-reply
2017-11-27 16:09 ` Timothy Pearson
30 siblings, 0 replies; 36+ messages in thread
From: no-reply @ 2017-11-21 22:44 UTC (permalink / raw)
To: richard.henderson; +Cc: famz, qemu-devel
Hi,
This series failed build test on ppc host. Please find the details below.
Message-id: 20171121212534.5177-1-richard.henderson@linaro.org
Type: series
Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
=== TEST SCRIPT BEGIN ===
#!/bin/bash
# Testing script will be invoked under the git checkout with
# HEAD pointing to a commit that has the patches applied on top of "base"
# branch
set -e
echo "=== ENV ==="
env
echo "=== PACKAGES ==="
rpm -qa
echo "=== TEST BEGIN ==="
INSTALL=$PWD/install
BUILD=$PWD/build
mkdir -p $BUILD $INSTALL
SRC=$PWD
cd $BUILD
$SRC/configure --prefix=$INSTALL
make -j100
# XXX: we need reliable clean up
# make check -j100 V=1
make install
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20171121212534.5177-1-richard.henderson@linaro.org -> patchew/20171121212534.5177-1-richard.henderson@linaro.org
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Submodule 'pixman' (git://anongit.freedesktop.org/pixman) registered for path 'pixman'
Submodule 'roms/SLOF' (git://git.qemu-project.org/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (git://git.qemu-project.org/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (git://git.qemu-project.org/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (git://git.qemu-project.org/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (git://github.com/rth7680/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (git://git.qemu-project.org/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/sgabios' (git://git.qemu-project.org/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/u-boot' (git://git.qemu-project.org/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/vgabios' (git://git.qemu-project.org/vgabios.git/) registered for path 'roms/vgabios'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '65cc4d2748a2c2e6f27f1cf39e07a5dbabd80ebf'
Cloning into 'pixman'...
Submodule path 'pixman': checked out '87eea99e443b389c978cf37efc52788bf03a0ee0'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 'e3d05727a074619fc12d0a67f05cf2c42c875cce'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out '04186319181298083ef28695a8309028b26fe83c'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 'e79bca64838c96ec44fd7acd508879c5284233dd'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 'c87a92639b28ac42bc8f6c67443543b405dc479b'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'e2fc41e24ee0ada60fc511d60b15a41b294538be'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out '23d474943dcd55d0550a3d20b3d30e9040a4f15b'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out '2072e7262965bb48d7fffb1e283101e6ed8b21a8'
Cloning into 'roms/vgabios'...
Submodule path 'roms/vgabios': checked out '19ea12c230ded95928ecaef0db47a82231c2e485'
warning: unable to rmdir pixman: Directory not empty
Switched to a new branch 'test'
M dtc
M roms/SLOF
M roms/ipxe
M roms/openbios
M roms/qemu-palcode
M roms/seabios
M roms/sgabios
M roms/u-boot
25cb597 tcg/aarch64: Add vector operations
3f5327e tcg/i386: Add vector operations/expansions for mul/extend
9842ec4 target/arm: Use vector infrastructure for aa64 widening shifts
5baa8f3 tcg: Add generic vector ops for extension
f31da52 target/arm: Use vector infrastructure for aa64 multiplies
32e5841 tcg: Add generic vector ops for multiplication
02b126c tcg/i386: Add vector operations/expansions for shift/cmp/interleave
bd28e62 target/arm: Use vector infrastructure for aa64 compares
c1bffde tcg: Add generic vector ops for comparisons
c6dfe9f target/arm: Use vector infrastructure for aa64 constant shifts
692cd85 tcg: Add generic vector ops for constant shifts
77a9e02 target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
8b8ba00 tcg: Add generic vector ops for interleave
e5c9bc0 tcg: Add tcg_expand_vec_op and tcg-target.opc.h
8f26874 tcg/i386: Add vector operations
2895593 target/arm: Use vector infrastructure for aa64 dup/movi
75b6cdb target/arm: Use vector infrastructure for aa64 mov/not/neg
01af1be target/arm: Use vector infrastructure for aa64 add/sub/logic
f368c49 target/arm: Align vector registers
0870bb2 tcg: Add tcg_signed_cond
0ac77ec tcg: Allow multiple word entries into the constant pool
729ef74 tcg: Add generic vector expanders
b0b5925 tcg: Add types and basic operations for host vectors
cfb2262 tcg: Generalize TCGOp parameters
17d3aaf tcg: Dynamically allocate TCGOps
795ee71 tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*
=== OUTPUT BEGIN ===
=== ENV ===
XDG_SESSION_ID=43713
SHELL=/bin/sh
USER=patchew
PATCHEW=/home/patchew/patchew/patchew-cli -s http://patchew.org --nodebug
PATH=/usr/bin:/bin
PWD=/var/tmp/patchew-tester-tmp-lmn4s2rx/src
LANG=en_US.UTF-8
HOME=/home/patchew
SHLVL=2
LOGNAME=patchew
XDG_RUNTIME_DIR=/run/user/1000
_=/usr/bin/env
=== PACKAGES ===
plymouth-core-libs-0.8.9-0.28.20140113.el7.centos.ppc64le
vim-common-7.4.160-2.el7.ppc64le
perl-Test-Simple-0.98-243.el7.noarch
hplip-common-3.15.9-3.el7.ppc64le
valgrind-3.12.0-8.el7.ppc64le
gamin-0.1.10-16.el7.ppc64le
libpeas-loader-python-1.20.0-1.el7.ppc64le
telepathy-filesystem-0.0.2-6.el7.noarch
colord-libs-1.3.4-1.el7.ppc64le
kbd-legacy-1.15.5-13.el7.noarch
perl-CPAN-Meta-YAML-0.008-14.el7.noarch
libvirt-daemon-driver-nwfilter-3.2.0-14.el7.ppc64le
ntsysv-1.7.4-1.el7.ppc64le
kernel-bootwrapper-3.10.0-693.el7.ppc64le
telepathy-farstream-0.6.0-5.el7.ppc64le
kdenetwork-common-4.10.5-8.el7_0.noarch
elfutils-devel-0.168-8.el7.ppc64le
pm-utils-1.4.1-27.el7.ppc64le
perl-Error-0.17020-2.el7.noarch
usbmuxd-1.1.0-1.el7.ppc64le
bzip2-devel-1.0.6-13.el7.ppc64le
blktrace-1.0.5-8.el7.ppc64le
gnome-keyring-pam-3.20.0-3.el7.ppc64le
tzdata-java-2017b-1.el7.noarch
perl-devel-5.16.3-292.el7.ppc64le
gnome-getting-started-docs-3.22.0-1.el7.noarch
perl-Log-Message-Simple-0.10-2.el7.noarch
totem-pl-parser-3.10.7-1.el7.ppc64le
lohit-oriya-fonts-2.5.4.1-3.el7.noarch
python-coverage-3.6-0.5.b3.el7.ppc64le
java-1.7.0-openjdk-1.7.0.141-2.6.10.5.el7.ppc64le
mailcap-2.1.41-2.el7.noarch
perl-CPANPLUS-0.91.38-4.el7.noarch
fprintd-pam-0.5.0-4.0.el7_0.ppc64le
less-458-9.el7.ppc64le
gupnp-igd-0.2.4-1.el7.ppc64le
thai-scalable-waree-fonts-0.5.0-7.el7.noarch
python-di-0.3-2.el7.noarch
yelp-libs-3.22.0-1.el7.ppc64le
vte-profile-0.46.2-1.el7.ppc64le
gpm-libs-1.20.7-5.el7.ppc64le
gnome-clocks-3.22.1-1.el7.ppc64le
p11-kit-trust-0.23.5-3.el7.ppc64le
gssproxy-0.7.0-4.el7.ppc64le
gnu-free-mono-fonts-20120503-8.el7.noarch
python-dateutil-1.5-7.el7.noarch
gucharmap-libs-3.18.2-1.el7.ppc64le
glibc-common-2.17-196.el7.ppc64le
libreport-plugin-mantisbt-2.1.11-38.el7.centos.ppc64le
motif-devel-2.3.4-8.1.el7_3.ppc64le
celt051-0.5.1.3-8.el7.ppc64le
radvd-1.9.2-9.el7.ppc64le
lohit-tamil-fonts-2.5.3-2.el7.noarch
python-ipaddress-1.0.16-2.el7.noarch
anaconda-widgets-21.48.22.121-1.el7.centos.ppc64le
zlib-1.2.7-17.el7.ppc64le
libstdc++-devel-4.8.5-16.el7.ppc64le
system-config-printer-1.4.1-19.el7.ppc64le
mozjs24-24.2.0-7.el7.ppc64le
device-mapper-multipath-libs-0.4.9-111.el7.ppc64le
wqy-microhei-fonts-0.2.0-0.12.beta.el7.noarch
python-schedutils-0.4-6.el7.ppc64le
gnome-bluetooth-3.20.1-1.el7.ppc64le
nss-util-3.28.4-3.el7.ppc64le
dotconf-1.3-8.el7.ppc64le
ibus-rawcode-1.3.2-3.el7.ppc64le
abattis-cantarell-fonts-0.0.25-1.el7.noarch
sssd-common-1.15.2-50.el7.ppc64le
sil-padauk-fonts-2.8-5.el7.noarch
bind-utils-9.9.4-50.el7.ppc64le
sox-14.4.1-6.el7.ppc64le
libSM-1.2.2-2.el7.ppc64le
libtiff-devel-4.0.3-27.el7_3.ppc64le
plymouth-system-theme-0.8.9-0.28.20140113.el7.centos.ppc64le
python-libs-2.7.5-58.el7.ppc64le
sssd-1.15.2-50.el7.ppc64le
rfkill-0.4-9.el7.ppc64le
cyrus-sasl-md5-2.1.26-21.el7.ppc64le
libXtst-devel-1.2.3-1.el7.ppc64le
avahi-libs-0.6.31-17.el7.ppc64le
ruby-2.0.0.648-30.el7.ppc64le
seahorse-3.20.0-1.el7.ppc64le
python-six-1.9.0-2.el7.noarch
gpgme-1.3.2-5.el7.ppc64le
iwl7260-firmware-22.0.7.0-56.el7.noarch
libsss_certmap-1.15.2-50.el7.ppc64le
xorg-x11-drv-wacom-0.34.2-2.el7.ppc64le
libXau-1.0.8-2.1.el7.ppc64le
shadow-utils-4.1.5.1-24.el7.ppc64le
evolution-ews-3.22.6-6.el7.ppc64le
libsecret-0.18.5-2.el7.ppc64le
perl-Module-Signature-0.73-2.el7.noarch
rootfiles-8.1-11.el7.noarch
trace-cmd-2.6.0-8.el7.ppc64le
hamcrest-1.3-6.el7.noarch
gawk-4.0.2-4.el7_3.1.ppc64le
usermode-1.111-5.el7.ppc64le
gnome-terminal-nautilus-3.22.1-2.el7.ppc64le
gvfs-client-1.30.4-3.el7.ppc64le
yum-utils-1.1.31-42.el7.noarch
iwl3945-firmware-15.32.2.9-56.el7.noarch
perl-Archive-Zip-1.30-11.el7.noarch
spice-glib-0.33-6.el7.ppc64le
augeas-libs-1.4.0-2.el7.ppc64le
openlmi-providers-0.5.0-4.el7.ppc64le
gnome-color-manager-3.22.2-1.el7.ppc64le
imsettings-libs-1.6.3-9.el7.ppc64le
nss-softokn-devel-3.28.3-6.el7.ppc64le
python34-3.4.5-4.el7.ppc64le
perl-DBI-1.627-4.el7.ppc64le
plymouth-plugin-label-0.8.9-0.28.20140113.el7.centos.ppc64le
binutils-2.25.1-31.base.el7.ppc64le
libsss_nss_idmap-1.15.2-50.el7.ppc64le
gvfs-smb-1.30.4-3.el7.ppc64le
freetype-devel-2.4.11-15.el7.ppc64le
libXi-1.7.9-1.el7.ppc64le
perl-Text-Diff-1.41-5.el7.noarch
gcr-devel-3.20.0-1.el7.ppc64le
numactl-libs-2.0.9-6.el7_2.ppc64le
hardlink-1.0-19.el7.ppc64le
gnome-disk-utility-3.22.1-1.el7.ppc64le
mariadb-libs-5.5.56-2.el7.ppc64le
libnotify-0.7.7-1.el7.ppc64le
perl-TimeDate-2.30-2.el7.noarch
soprano-devel-2.9.2-3.el7.ppc64le
pixman-0.34.0-1.el7.ppc64le
kmod-20-15.el7.ppc64le
qt3-PostgreSQL-3.3.8b-51.el7.ppc64le
python2-pyasn1-0.1.9-7.el7.noarch
libXt-1.1.5-3.el7.ppc64le
perl-Font-AFM-1.20-13.el7.noarch
ibus-1.5.3-13.el7.ppc64le
findutils-4.5.11-5.el7.ppc64le
ibus-libs-1.5.3-13.el7.ppc64le
iprutils-2.4.14.1-1.el7.ppc64le
libpwquality-1.2.3-4.el7.ppc64le
libXrender-devel-0.9.10-1.el7.ppc64le
perl-IO-stringy-2.110-22.el7.noarch
kdelibs-4.14.8-6.el7_3.ppc64le
flac-libs-1.3.0-5.el7_1.ppc64le
device-mapper-event-libs-1.02.140-8.el7.ppc64le
gnutls-devel-3.3.26-9.el7.ppc64le
libXau-devel-1.0.8-2.1.el7.ppc64le
gstreamer1-plugins-base-1.10.4-1.el7.ppc64le
perl-HTML-Tree-5.03-2.el7.noarch
kdenetwork-kopete-4.10.5-8.el7_0.ppc64le
libepoxy-1.3.1-1.el7.ppc64le
mesa-libGLES-17.0.1-6.20170307.el7.ppc64le
qt-postgresql-4.8.5-13.el7.ppc64le
fontconfig-devel-2.10.95-11.el7.ppc64le
java-1.8.0-openjdk-headless-1.8.0.131-11.b12.el7.ppc64le
libXfont-1.5.2-1.el7.ppc64le
libkexiv2-4.10.5-3.el7.ppc64le
openjpeg-libs-1.5.1-17.el7.ppc64le
iscsi-initiator-utils-6.2.0.874-4.el7.ppc64le
NetworkManager-adsl-1.8.0-9.el7.ppc64le
libgtop2-2.34.2-1.el7.ppc64le
libXdamage-devel-1.1.4-4.1.el7.ppc64le
ipset-libs-6.29-1.el7.ppc64le
kde-runtime-drkonqi-4.10.5-8.el7.ppc64le
e2fsprogs-libs-1.42.9-10.el7.ppc64le
dhclient-4.2.5-58.el7.centos.ppc64le
usbutils-007-5.el7.ppc64le
python-ethtool-0.8-5.el7.ppc64le
gstreamer1-plugins-bad-free-1.10.4-2.el7.ppc64le
fftw-libs-double-3.3.3-8.el7.ppc64le
kdenetwork-krdc-4.10.5-8.el7_0.ppc64le
fuse-libs-2.9.2-8.el7.ppc64le
pciutils-3.5.1-2.el7.ppc64le
at-3.1.13-22.el7.ppc64le
python-IPy-0.75-6.el7.noarch
libXp-1.0.2-2.1.el7.ppc64le
vim-minimal-7.4.160-2.el7.ppc64le
kdesdk-kmtrace-4.10.5-6.el7.ppc64le
libraw1394-2.1.0-2.el7.ppc64le
libdrm-devel-2.4.74-1.el7.ppc64le
irqbalance-1.0.7-10.el7.ppc64le
fipscheck-lib-1.4.1-6.el7.ppc64le
gvfs-1.30.4-3.el7.ppc64le
libiscsi-1.9.0-7.el7.ppc64le
motif-2.3.4-8.1.el7_3.ppc64le
keyutils-1.5.8-3.el7.ppc64le
NetworkManager-ppp-1.8.0-9.el7.ppc64le
systemtap-3.1-3.el7.ppc64le
boost-serialization-1.53.0-27.el7.ppc64le
grilo-0.3.3-1.el7.ppc64le
rpm-4.11.3-25.el7.ppc64le
kdegraphics-libs-4.10.5-3.el7.noarch
libfontenc-1.1.3-3.el7.ppc64le
perl-Git-1.8.3.1-11.el7.noarch
rubygem-abrt-0.3.0-1.el7.noarch
tcl-8.5.13-8.el7.ppc64le
gtksourceview3-3.22.2-1.el7.ppc64le
cmake-2.8.12.2-2.el7.ppc64le
pulseaudio-utils-10.0-3.el7.ppc64le
libusal-1.1.11-23.el7.ppc64le
grub2-ppc64le-2.02-0.64.el7.centos.ppc64le
libreport-plugin-mailx-2.1.11-38.el7.centos.ppc64le
libvisual-0.4.0-16.el7.ppc64le
metacity-2.34.13-7.el7.ppc64le
redland-virtuoso-1.0.16-6.el7.ppc64le
nautilus-3.22.3-3.el7.ppc64le
pciutils-libs-3.5.1-2.el7.ppc64le
soprano-2.9.2-3.el7.ppc64le
mariadb-devel-5.5.56-2.el7.ppc64le
libxkbcommon-x11-0.7.1-1.el7.ppc64le
farstream02-0.2.3-3.el7.ppc64le
redhat-rpm-config-9.1.0-76.el7.centos.noarch
skkdic-20130104-6.T1435.el7.noarch
perl-HTTP-Tiny-0.033-3.el7.noarch
lvm2-libs-2.02.171-8.el7.ppc64le
perl-XML-Grove-0.46alpha-52.el7.noarch
boost-devel-1.53.0-27.el7.ppc64le
pycairo-1.8.10-8.el7.ppc64le
popt-devel-1.13-16.el7.ppc64le
gnome-settings-daemon-3.22.2-5.el7.ppc64le
perl-Socket-2.010-4.el7.ppc64le
numad-0.5-17.20150602git.el7.ppc64le
e2fsprogs-devel-1.42.9-10.el7.ppc64le
libsecret-devel-0.18.5-2.el7.ppc64le
libXv-devel-1.0.11-1.el7.ppc64le
libchewing-0.3.4-6.el7.ppc64le
gnome-shell-extension-places-menu-3.22.2-10.el7.noarch
perl-Time-HiRes-1.9725-3.el7.ppc64le
openchange-2.3-2.el7.ppc64le
audit-libs-devel-2.7.6-3.el7.ppc64le
python-dmidecode-3.12.2-1.el7.ppc64le
libmediaart-1.9.1-1.el7.ppc64le
elfutils-default-yama-scope-0.168-8.el7.noarch
quota-4.01-14.el7.ppc64le
perl-threads-1.87-4.el7.ppc64le
realmd-0.16.1-9.el7.ppc64le
nautilus-sendto-3.8.4-1.el7.ppc64le
gstreamer-0.10.36-7.el7.ppc64le
cairo-gobject-devel-1.14.8-2.el7.ppc64le
abrt-libs-2.1.11-48.el7.centos.ppc64le
libvirt-daemon-driver-storage-iscsi-3.2.0-14.el7.ppc64le
perl-Pod-Parser-1.61-2.el7.noarch
python-devel-2.7.5-58.el7.ppc64le
mpfr-devel-3.1.1-4.el7.ppc64le
kernel-headers-3.10.0-693.el7.ppc64le
powerpc-utils-python-1.2.1-9.el7.noarch
linux-firmware-20170606-56.gitc990aae.el7.noarch
libqmi-1.16.0-1.el7.ppc64le
libvirt-libs-3.2.0-14.el7.ppc64le
perl-Digest-1.17-245.el7.noarch
libgcab1-0.7-3.el7.ppc64le
flex-2.5.37-3.el7.ppc64le
tzdata-2017b-1.el7.noarch
phonon-4.6.0-10.el7.ppc64le
anaconda-tui-21.48.22.121-1.el7.centos.ppc64le
libmbim-utils-1.14.0-2.el7.ppc64le
gnutls-utils-3.3.26-9.el7.ppc64le
perl-Parse-CPAN-Meta-1.4404-5.el7.noarch
flite-1.3-22.el7.ppc64le
nfs4-acl-tools-0.3.3-15.el7.ppc64le
poppler-data-0.4.6-3.el7.noarch
gvfs-fuse-1.30.4-3.el7.ppc64le
gnome-software-3.22.7-1.el7.ppc64le
perl-ExtUtils-ParseXS-3.18-3.el7.noarch
libvirt-python-3.2.0-3.el7.ppc64le
perl-Module-Load-Conditional-0.54-3.el7.noarch
python-netifaces-0.10.4-3.el7.ppc64le
swig-2.0.10-5.el7.ppc64le
ipa-client-common-4.5.0-20.el7.centos.noarch
cheese-libs-3.22.1-1.el7.ppc64le
gnome-tweak-tool-3.22.0-1.el7.noarch
perl-ExtUtils-CBuilder-0.28.2.6-292.el7.noarch
libsoup-devel-2.56.0-3.el7.ppc64le
perl-IO-Zlib-1.10-292.el7.noarch
fros-1.0-2.el7.noarch
lohit-devanagari-fonts-2.5.3-4.el7.noarch
grub2-ppc64le-modules-2.02-0.64.el7.centos.noarch
libgdata-0.17.8-1.el7.ppc64le
evince-nautilus-3.22.1-5.el7.ppc64le
perl-ExtUtils-Embed-1.30-292.el7.noarch
dleyna-connector-dbus-0.2.0-2.el7.ppc64le
libiec61883-1.2.0-10.el7.ppc64le
python-lxml-3.2.1-4.el7.ppc64le
liberation-serif-fonts-1.07.2-15.el7.noarch
tigervnc-license-1.8.0-1.el7.noarch
gnome-packagekit-3.22.1-2.el7.ppc64le
hpijs-3.15.9-3.el7.ppc64le
libmodman-2.0.1-8.el7.ppc64le
ntp-4.2.6p5-25.el7.centos.2.ppc64le
gmp-devel-6.0.0-15.el7.ppc64le
pyxattr-0.5.1-5.el7.ppc64le
sil-abyssinica-fonts-1.200-6.el7.noarch
ncurses-libs-5.9-13.20130511.el7.ppc64le
gnome-dictionary-libs-3.20.0-1.el7.ppc64le
kdesdk-devel-4.10.5-6.el7.ppc64le
libreport-rhel-anaconda-bugzilla-2.1.11-38.el7.centos.ppc64le
libvirt-daemon-config-network-3.2.0-14.el7.ppc64le
boost-iostreams-1.53.0-27.el7.ppc64le
python-ply-3.4-11.el7.noarch
ucs-miscfixed-fonts-0.3-11.el7.noarch
info-5.1-4.el7.ppc64le
libXxf86misc-devel-1.0.3-7.1.el7.ppc64le
ibus-qt-1.3.2-4.el7.ppc64le
gnome-video-effects-0.4.3-1.el7.noarch
bridge-utils-1.5-9.el7.ppc64le
make-3.82-23.el7.ppc64le
pywbem-0.7.0-25.20130827svn625.el7.noarch
pnm2ppa-1.04-28.el7.ppc64le
chkconfig-1.7.4-1.el7.ppc64le
at-spi2-atk-devel-2.22.0-2.el7.ppc64le
freeglut-devel-2.8.1-3.el7.ppc64le
jbigkit-libs-2.0-11.el7.ppc64le
sssd-ipa-1.15.2-50.el7.ppc64le
openssl-libs-1.0.2k-8.el7.ppc64le
ldns-1.6.16-10.el7.ppc64le
rdate-1.4-25.el7.ppc64le
libdb-5.3.21-20.el7.ppc64le
evince-libs-3.22.1-5.el7.ppc64le
empathy-3.12.12-4.el7.ppc64le
rubygem-json-1.7.7-30.el7.ppc64le
dmraid-1.0.0.rc16-28.el7.ppc64le
libblkid-2.23.2-43.el7.ppc64le
logrotate-3.8.6-14.el7.ppc64le
iwl105-firmware-18.168.6.1-56.el7.noarch
grep-2.20-3.el7.ppc64le
xorg-x11-drv-synaptics-1.9.0-1.el7.ppc64le
iowatcher-1.0-6.el7.ppc64le
rubygem-net-http-persistent-2.8-5.el7.noarch
setroubleshoot-plugins-3.0.65-1.el7.noarch
atk-2.22.0-3.el7.ppc64le
libcacard-2.5.2-2.el7.ppc64le
iwl6050-firmware-41.28.5.1-56.el7.noarch
lcms2-2.6-3.el7.ppc64le
tigervnc-server-minimal-1.8.0-1.el7.ppc64le
gvfs-goa-1.30.4-3.el7.ppc64le
authconfig-6.2.8-30.el7.ppc64le
yum-plugin-fastestmirror-1.1.31-42.el7.noarch
dbus-python-1.1.1-9.el7.ppc64le
perl-Archive-Tar-1.92-2.el7.noarch
iwl5000-firmware-8.83.5.1_1-56.el7.noarch
libacl-2.2.51-12.el7.ppc64le
farstream-0.1.2-8.el7.ppc64le
ppc64-utils-0.14-16.el7.ppc64le
servicelog-1.1.14-3.el7.ppc64le
python2-ipaclient-4.5.0-20.el7.centos.noarch
libpeas-1.20.0-1.el7.ppc64le
perl-TermReadKey-2.30-20.el7.ppc64le
hdparm-9.43-5.el7.ppc64le
libicu-50.1.2-15.el7.ppc64le
polkit-qt-0.103.0-10.el7_0.ppc64le
gnome-weather-3.20.2-1.el7.noarch
libmspack-0.5-0.5.alpha.el7.ppc64le
libkkc-data-0.3.1-9.el7.ppc64le
hicolor-icon-theme-0.12-7.el7.noarch
perl-Newt-1.08-36.el7.ppc64le
libexif-0.6.21-6.el7.ppc64le
gtk3-devel-3.22.10-4.el7.ppc64le
gvfs-mtp-1.30.4-3.el7.ppc64le
ncompress-4.2.4.4-3.el7.ppc64le
libXcomposite-0.4.4-4.1.el7.ppc64le
python-decorator-3.4.0-3.el7.noarch
perl-Business-ISBN-Data-20120719.001-2.el7.noarch
cpio-2.11-24.el7.ppc64le
mesa-libGLU-9.0.0-4.el7.ppc64le
baobab-3.22.1-1.el7.ppc64le
device-mapper-libs-1.02.140-8.el7.ppc64le
libXtst-1.2.3-1.el7.ppc64le
ModemManager-glib-1.6.0-2.el7.ppc64le
perl-HTML-Parser-3.71-4.el7.ppc64le
libical-1.0.1-1.el7.ppc64le
xorg-x11-xinit-1.3.4-1.el7.ppc64le
gstreamer1-plugins-base-devel-1.10.4-1.el7.ppc64le
libdrm-2.4.74-1.el7.ppc64le
libXfixes-devel-5.0.3-1.el7.ppc64le
python-gssapi-1.2.0-3.el7.ppc64le
perl-Text-Unidecode-0.04-20.el7.noarch
hunspell-1.3.2-15.el7.ppc64le
kde-settings-19-23.5.el7.centos.noarch
perl-App-cpanminus-1.6922-2.el7.noarch
parted-3.1-28.el7.ppc64le
mesa-libGL-17.0.1-6.20170307.el7.ppc64le
elfutils-libelf-devel-0.168-8.el7.ppc64le
perl-Net-LibIDN-0.12-15.el7.ppc64le
apr-1.4.8-3.el7.ppc64le
kdepimlibs-4.10.5-4.el7.ppc64le
virt-top-1.0.8-23.el7.ppc64le
samba-client-libs-4.6.2-8.el7.ppc64le
gstreamer-plugins-base-0.10.36-10.el7.ppc64le
json-glib-devel-1.2.6-1.el7.ppc64le
perl-autodie-2.16-2.el7.noarch
tar-1.26-32.el7.ppc64le
ksysguard-libs-4.11.19-8.el7.ppc64le
rdma-core-devel-13-7.el7.ppc64le
accountsservice-0.6.45-2.el7.ppc64le
libxklavier-5.4-7.el7.ppc64le
libxml2-devel-2.9.1-6.el7_2.3.ppc64le
ghostscript-fonts-5.50-32.el7.noarch
libassuan-2.1.0-3.el7.ppc64le
libkipi-devel-4.10.5-3.el7.ppc64le
python-smbc-1.0.13-7.el7.ppc64le
initscripts-9.49.39-1.el7.ppc64le
qt3-3.3.8b-51.el7.ppc64le
yum-metadata-parser-1.1.4-10.el7.ppc64le
device-mapper-persistent-data-0.7.0-0.1.rc6.el7.ppc64le
adwaita-icon-theme-3.22.0-1.el7.noarch
kdepim-4.10.5-6.el7.ppc64le
postfix-2.10.1-6.el7.ppc64le
abrt-addon-pstoreoops-2.1.11-48.el7.centos.ppc64le
freerdp-libs-1.0.2-10.el7.ppc64le
langtable-python-0.0.31-3.el7.noarch
tcp_wrappers-7.6-77.el7.ppc64le
lm_sensors-libs-3.4.0-4.20160601gitf9185e5.el7.ppc64le
kde-style-oxygen-4.11.19-8.el7.ppc64le
powertop-2.3-12.el7.ppc64le
wpa_supplicant-2.6-5.el7.ppc64le
gtk3-3.22.10-4.el7.ppc64le
boost-python-1.53.0-27.el7.ppc64le
keyutils-libs-devel-1.5.8-3.el7.ppc64le
libdvdread-5.0.3-3.el7.ppc64le
im-chooser-common-1.6.4-4.el7.ppc64le
aic94xx-firmware-30-6.el7.noarch
media-player-info-17-4.el7.noarch
compat-gnome-desktop314-3.14.2-1.el7.ppc64le
harfbuzz-1.3.2-1.el7.ppc64le
libgcrypt-devel-1.5.3-14.el7.ppc64le
groff-base-1.22.2-8.el7.ppc64le
sane-backends-1.0.24-9.el7.ppc64le
setuptool-1.19.11-8.el7.ppc64le
ebtables-2.0.10-15.el7.ppc64le
libchamplain-0.12.15-1.el7.ppc64le
boost-math-1.53.0-27.el7.ppc64le
libuser-0.60-7.el7_1.ppc64le
boost-date-time-1.53.0-27.el7.ppc64le
espeak-1.47.11-4.el7.ppc64le
tbb-devel-4.1-9.20130314.el7.ppc64le
grub2-tools-minimal-2.02-0.64.el7.centos.ppc64le
gjs-1.46.0-1.el7.ppc64le
libsss_autofs-1.15.2-50.el7.ppc64le
deltarpm-3.6-3.el7.ppc64le
libnl-1.1.4-3.el7.ppc64le
libgpod-0.8.2-12.el7.ppc64le
postgresql-devel-9.2.21-1.el7.ppc64le
libibcm-13-7.el7.ppc64le
abrt-gui-libs-2.1.11-48.el7.centos.ppc64le
libxkbcommon-0.7.1-1.el7.ppc64le
passwd-0.79-4.el7.ppc64le
lsvpd-1.7.8-1.el7.ppc64le
fprintd-0.5.0-4.0.el7_0.ppc64le
hunspell-en-0.20121024-6.el7.noarch
qca-ossl-2.0.0-0.19.beta3.el7.ppc64le
libdmapsharing-2.9.37-1.el7.ppc64le
ortp-0.20.0-10.el7.ppc64le
python-pycurl-7.19.0-19.el7.ppc64le
perl-Pod-Escapes-1.04-292.el7.noarch
pcp-3.11.8-7.el7.ppc64le
libblkid-devel-2.23.2-43.el7.ppc64le
dracut-network-033-502.el7.ppc64le
pyatspi-2.20.3-1.el7.noarch
systemtap-sdt-devel-3.1-3.el7.ppc64le
check-0.9.9-5.el7.ppc64le
perl-threads-shared-1.43-6.el7.ppc64le
gnome-shell-extension-common-3.22.2-10.el7.noarch
gnome-icon-theme-symbolic-3.12.0-2.el7.noarch
abrt-cli-2.1.11-48.el7.centos.ppc64le
festival-speechtools-libs-1.2.96-28.el7.ppc64le
python-slip-dbus-0.4.0-2.el7.noarch
mesa-private-llvm-3.9.1-3.el7.ppc64le
perl-Time-Local-1.2300-2.el7.noarch
yelp-3.22.0-1.el7.ppc64le
fuse-devel-2.9.2-8.el7.ppc64le
dnsmasq-2.76-2.el7.ppc64le
festvox-slt-arctic-hts-0.20061229-28.el7.noarch
libtasn1-devel-4.10-1.el7.ppc64le
libgudev1-219-42.el7.ppc64le
perl-version-0.99.07-2.el7.ppc64le
libvirt-daemon-driver-qemu-3.2.0-14.el7.ppc64le
ps_mem-3.1-7.el7.noarch
rtkit-0.11-10.el7.ppc64le
abrt-gui-2.1.11-48.el7.centos.ppc64le
nettle-devel-2.7.1-8.el7.ppc64le
perl-ExtUtils-Manifest-1.61-244.el7.noarch
libreswan-3.20-3.el7.ppc64le
python-pyudev-0.15-9.el7.noarch
appstream-data-7-20170301.el7.noarch
powerpc-utils-1.3.3-4.el7.ppc64le
setup-2.8.71-7.el7.noarch
enscript-1.6.6-6.el7.ppc64le
libgexiv2-0.10.4-2.el7.ppc64le
perl-Digest-SHA-5.85-4.el7.ppc64le
upower-0.99.4-2.el7.ppc64le
dhcp-libs-4.2.5-58.el7.centos.ppc64le
kbd-1.15.5-13.el7.ppc64le
phonon-backend-gstreamer-4.6.3-3.el7.ppc64le
dejavu-fonts-common-2.33-6.el7.noarch
libaio-devel-0.3.109-13.el7.ppc64le
grubby-8.28-23.el7.ppc64le
perl-CPAN-Meta-2.120921-5.el7.noarch
libmusicbrainz5-5.0.1-9.el7.ppc64le
liberation-mono-fonts-1.07.2-15.el7.noarch
fcoe-utils-1.0.32-1.el7.ppc64le
gvfs-afc-1.30.4-3.el7.ppc64le
m17n-db-1.6.4-3.el7.noarch
time-1.7-45.el7.ppc64le
python-configobj-4.7.2-7.el7.noarch
perl-Log-Message-0.08-3.el7.noarch
glib-networking-2.50.0-1.el7.ppc64le
gcc-4.8.5-16.el7.ppc64le
gnome-classic-session-3.22.2-10.el7.noarch
libglade2-2.6.4-11.el7.ppc64le
langtable-data-0.0.31-3.el7.noarch
dejavu-serif-fonts-2.33-6.el7.noarch
python-requests-2.6.0-1.el7_1.noarch
perl-HTML-Tagset-3.20-15.el7.noarch
gssdp-1.0.1-1.el7.ppc64le
perl-CPANPLUS-Dist-Build-0.70-3.el7.noarch
brasero-nautilus-3.12.1-2.el7.ppc64le
evolution-data-server-3.22.7-6.el7.ppc64le
khmeros-fonts-common-5.0-17.el7.noarch
dejavu-sans-fonts-2.33-6.el7.noarch
python-kmod-0.9-4.el7.ppc64le
lzop-1.03-10.el7.ppc64le
telepathy-salut-0.8.1-6.el7.ppc64le
tbb-4.1-9.20130314.el7.ppc64le
kdegraphics-devel-4.10.5-3.el7.noarch
libcryptui-3.12.2-1.el7.ppc64le
ncurses-base-5.9-13.20130511.el7.noarch
lohit-nepali-fonts-2.5.3-2.el7.noarch
python-configshell-1.1.fb23-3.el7.noarch
acl-2.2.51-12.el7.ppc64le
python-rtslib-2.1.fb63-2.el7.noarch
libreport-plugin-rhtsupport-2.1.11-38.el7.centos.ppc64le
imsettings-qt-1.6.3-9.el7.ppc64le
webkitgtk3-2.4.11-2.el7.ppc64le
libsepol-2.5-6.el7.ppc64le
smc-meera-fonts-6.0-7.el7.noarch
python-mako-0.8.1-2.el7.noarch
pinentry-0.8.1-17.el7.ppc64le
alsa-tools-firmware-1.1.0-1.el7.ppc64le
libgdither-0.6-8.el7.ppc64le
ibus-libpinyin-1.6.91-4.el7.ppc64le
libXp-devel-1.0.2-2.1.el7.ppc64le
nspr-4.13.1-1.0.el7_3.ppc64le
cscope-15.8-10.el7.ppc64le
m2crypto-0.21.1-17.el7.ppc64le
libatomic-4.8.5-16.el7.ppc64le
opencc-0.4.3-3.el7.ppc64le
sbc-1.0-5.el7.ppc64le
SDL-devel-1.2.15-14.el7.ppc64le
vorbis-tools-1.4.0-12.el7.ppc64le
bzip2-libs-1.0.6-13.el7.ppc64le
google-crosextra-carlito-fonts-1.103-0.2.20130920.el7.noarch
nmap-ncat-6.40-7.el7.ppc64le
krb5-libs-1.15.1-8.el7.ppc64le
sssd-krb5-1.15.2-50.el7.ppc64le
cups-filters-libs-1.0.35-22.el7.ppc64le
virt-manager-1.4.1-7.el7.noarch
evince-3.22.1-5.el7.ppc64le
readline-6.2-10.el7.ppc64le
ctags-5.8-13.el7.ppc64le
sound-theme-freedesktop-0.8-3.el7.noarch
ruby-libs-2.0.0.648-30.el7.ppc64le
pth-2.0.7-23.el7.ppc64le
rubygems-2.0.14.1-30.el7.noarch
gnome-dictionary-3.20.0-1.el7.ppc64le
xorg-x11-drv-evdev-2.10.5-2.1.el7.ppc64le
audit-libs-2.7.6-3.el7.ppc64le
iwl135-firmware-18.168.6.1-56.el7.noarch
python-nss-0.16.0-3.el7.ppc64le
json-glib-1.2.6-1.el7.ppc64le
flatpak-libs-0.8.7-1.el7.ppc64le
libutempter-1.1.6-4.el7.ppc64le
ekiga-4.0.1-7.el7.ppc64le
easymock2-2.5.2-12.el7.noarch
keyutils-libs-1.5.8-3.el7.ppc64le
iwl1000-firmware-39.31.5.1-56.el7.noarch
teamd-1.25-5.el7.ppc64le
telepathy-glib-0.24.0-1.el7.ppc64le
PackageKit-yum-1.1.5-1.el7.centos.ppc64le
virt-what-1.13-10.el7.ppc64le
ppc64-diag-2.7.3-3.el7.ppc64le
libpurple-2.10.11-5.el7.ppc64le
libffi-3.0.13-18.el7.ppc64le
iwl2000-firmware-18.168.6.1-56.el7.noarch
perl-YAML-0.84-5.el7.noarch
libxml2-python-2.9.1-6.el7_2.3.ppc64le
lsscsi-0.27-6.el7.ppc64le
systemtap-client-3.1-3.el7.ppc64le
virt-viewer-5.0-7.el7.ppc64le
dbusmenu-qt-0.9.2-7.el7.ppc64le
libtar-1.2.11-29.el7.ppc64le
ccache-3.3.4-1.el7.ppc64le
perl-DBD-SQLite-1.39-3.el7.ppc64le
gnome-icon-theme-3.12.0-1.el7.noarch
gdk-pixbuf2-2.36.5-1.el7.ppc64le
libpath_utils-0.2.1-27.el7.ppc64le
gvfs-archive-1.30.4-3.el7.ppc64le
gnome-online-accounts-devel-3.22.5-1.el7.ppc64le
yajl-2.0.4-4.el7.ppc64le
perl-Pod-Coverage-0.23-3.el7.noarch
libselinux-python-2.5-11.el7.ppc64le
libX11-devel-1.6.5-1.el7.ppc64le
qrencode-libs-3.4.1-3.el7.ppc64le
gnome-system-log-3.9.90-3.el7.ppc64le
mesa-libGLU-devel-9.0.0-4.el7.ppc64le
boost-system-1.53.0-27.el7.ppc64le
perl-HTTP-Message-6.06-6.el7.noarch
cracklib-2.9.0-11.el7.ppc64le
libXcursor-1.1.14-8.el7.ppc64le
dbus-1.6.12-17.el7.ppc64le
libnotify-devel-0.7.7-1.el7.ppc64le
ibus-gtk3-1.5.3-13.el7.ppc64le
libv4l-0.9.5-4.el7.ppc64le
perl-Time-Piece-1.20.1-292.el7.ppc64le
cracklib-dicts-2.9.0-11.el7.ppc64le
startup-notification-0.12-8.el7.ppc64le
dconf-0.26.0-2.el7.ppc64le
net-snmp-devel-5.7.2-28.el7.ppc64le
kate-part-4.10.5-4.el7.ppc64le
orc-0.4.26-1.el7.ppc64le
kernel-devel-3.10.0-693.el7.ppc64le
avahi-gobject-0.6.31-17.el7.ppc64le
cairo-gobject-1.14.8-2.el7.ppc64le
httpd-2.4.6-67.el7.centos.ppc64le
subversion-1.7.14-10.el7.ppc64le
kdepimlibs-akonadi-4.10.5-4.el7.ppc64le
gdbm-1.10-8.el7.ppc64le
perl-File-CheckTree-4.42-3.el7.noarch
atk-devel-2.22.0-3.el7.ppc64le
java-1.8.0-openjdk-devel-1.8.0.131-11.b12.el7.ppc64le
abrt-dbus-2.1.11-48.el7.centos.ppc64le
qt-mysql-4.8.5-13.el7.ppc64le
libkdcraw-4.10.5-4.el7.ppc64le
libaio-0.3.109-13.el7.ppc64le
urw-fonts-2.4-16.el7.noarch
libgee06-0.6.8-3.el7.ppc64le
libXrandr-devel-1.5.1-2.el7.ppc64le
cronie-anacron-1.4.11-17.el7.ppc64le
mlocate-0.26-6.el7.ppc64le
kdesdk-okteta-devel-4.10.5-6.el7.ppc64le
iso-codes-3.46-2.el7.noarch
cpp-4.8.5-16.el7.ppc64le
e2fsprogs-1.42.9-10.el7.ppc64le
at-spi2-atk-2.22.0-2.el7.ppc64le
libstoragemgmt-python-clibs-1.4.0-3.el7.ppc64le
PackageKit-command-not-found-1.1.5-1.el7.centos.ppc64le
kdenetwork-kopete-devel-4.10.5-8.el7_0.ppc64le
libmnl-1.0.3-7.el7.ppc64le
tcp_wrappers-devel-7.6-77.el7.ppc64le
python-dns-1.12.0-4.20150617git465785f.el7.noarch
libXinerama-devel-1.1.3-2.1.el7.ppc64le
libibverbs-13-7.el7.ppc64le
net-tools-2.0-0.22.20131004git.el7.ppc64le
kde-workspace-libs-4.11.19-8.el7.ppc64le
libwebp-0.3.0-7.el7.ppc64le
libattr-devel-2.4.46-12.el7.ppc64le
libkadm5-1.15.1-8.el7.ppc64le
gcr-3.20.0-1.el7.ppc64le
colord-1.3.4-1.el7.ppc64le
rsyslog-8.24.0-12.el7.ppc64le
im-chooser-1.6.4-4.el7.ppc64le
boost-filesystem-1.53.0-27.el7.ppc64le
libgpg-error-devel-1.12-3.el7.ppc64le
harfbuzz-icu-1.3.2-1.el7.ppc64le
libpeas-gtk-1.20.0-1.el7.ppc64le
abrt-addon-python-2.1.11-48.el7.centos.ppc64le
selinux-policy-targeted-3.13.1-166.el7.noarch
libksane-4.10.5-4.el7.ppc64le
m4-1.4.16-10.el7.ppc64le
xmlrpc-c-client-1.32.5-1905.svn2451.el7.ppc64le
sysvinit-tools-2.88-14.dsf.el7.ppc64le
libnma-1.8.0-3.el7.ppc64le
os-prober-1.58-9.el7.ppc64le
libproxy-mozjs-0.4.11-10.el7.ppc64le
speech-dispatcher-0.7.1-15.el7.ppc64le
boost-signals-1.53.0-27.el7.ppc64le
python-ldap-2.4.15-2.el7.ppc64le
libvpx-1.3.0-5.el7_0.ppc64le
nm-connection-editor-1.8.0-3.el7.ppc64le
NetworkManager-team-1.8.0-9.el7.ppc64le
perf-3.10.0-693.el7.ppc64le
libgsf-1.14.26-7.el7.ppc64le
libpfm-4.7.0-4.el7.ppc64le
postgresql-9.2.21-1.el7.ppc64le
ethtool-4.8-1.el7.ppc64le
xorg-x11-server-utils-7.7-20.el7.ppc64le
attica-0.4.2-1.el7.ppc64le
xfsdump-3.1.4-1.el7.ppc64le
firewalld-filesystem-0.4.4.4-6.el7.noarch
libXfont2-2.0.1-2.el7.ppc64le
net-snmp-agent-libs-5.7.2-28.el7.ppc64le
tcl-devel-8.5.13-8.el7.ppc64le
libgxps-0.2.5-1.el7.ppc64le
cyrus-sasl-devel-2.1.26-21.el7.ppc64le
hmaccalc-0.9.13-4.el7.ppc64le
libwacom-data-0.24-1.el7.noarch
perl-Pod-Usage-1.63-3.el7.noarch
libitm-4.8.5-16.el7.ppc64le
python-yubico-1.2.3-1.el7.noarch
libXxf86vm-devel-1.1.4-1.el7.ppc64le
abrt-tui-2.1.11-48.el7.centos.ppc64le
pinfo-0.6.10-9.el7.ppc64le
gnome-shell-extension-user-theme-3.22.2-10.el7.noarch
perl-File-Path-2.09-2.el7.noarch
xorg-x11-fonts-Type1-7.5-9.el7.noarch
python-firewall-0.4.4.4-6.el7.noarch
libXres-1.0.7-2.1.el7.ppc64le
libcgroup-tools-0.41-13.el7.ppc64le
libnl-devel-1.1.4-3.el7.ppc64le
gnome-user-docs-3.22.0-1.el7.noarch
perl-Pod-Simple-3.28-4.el7.noarch
systemd-libs-219-42.el7.ppc64le
ncurses-devel-5.9-13.20130511.el7.ppc64le
mesa-libEGL-devel-17.0.1-6.20170307.el7.ppc64le
audit-2.7.6-3.el7.ppc64le
iotop-0.6-2.el7.noarch
libvirt-daemon-driver-storage-logical-3.2.0-14.el7.ppc64le
perl-Module-CoreList-2.76.02-292.el7.noarch
libmbim-1.14.0-2.el7.ppc64le
libgcc-4.8.5-16.el7.ppc64le
xdg-desktop-portal-0.5-2.el7.ppc64le
perl-Module-Load-0.24-3.el7.noarch
caribou-gtk3-module-0.4.21-1.el7.ppc64le
sqlite-devel-3.7.17-8.el7.ppc64le
centos-indexhtml-7-9.el7.centos.noarch
elfutils-0.168-8.el7.ppc64le
centos-release-7-4.1708.el7.centos.ppc64le
trousers-0.3.14-2.el7.ppc64le
perl-Thread-Queue-3.02-2.el7.noarch
python-meh-gui-0.25.2-1.el7.noarch
gom-0.3.2-1.el7.ppc64le
lldpad-1.0.1-3.git036e314.el7.ppc64le
libgusb-0.2.9-1.el7.ppc64le
liberation-fonts-common-1.07.2-15.el7.noarch
libimobiledevice-1.2.0-1.el7.ppc64le
perl-Module-Pluggable-4.8-3.el7.noarch
ghostscript-cups-9.07-28.el7.ppc64le
osinfo-db-tools-1.1.0-1.el7.ppc64le
kbd-misc-1.15.5-13.el7.noarch
dhcp-common-4.2.5-58.el7.centos.ppc64le
control-center-filesystem-3.22.2-5.el7.ppc64le
libvirt-glib-1.0.0-1.el7.ppc64le
perl-CPAN-Meta-Requirements-2.122-7.el7.noarch
PyQt4-4.10.1-13.el7.ppc64le
btrfs-progs-4.9.1-1.el7.ppc64le
anaconda-gui-21.48.22.121-1.el7.centos.ppc64le
libatasmart-0.19-6.el7.ppc64le
shared-desktop-ontologies-0.11.0-2.el7.noarch
libvirt-daemon-config-nwfilter-3.2.0-14.el7.ppc64le
autoconf-2.69-11.el7.noarch
gnome-terminal-3.22.1-2.el7.ppc64le
python-cups-1.9.63-6.el7.ppc64le
intltool-0.50.2-7.el7.noarch
glibc-headers-2.17-196.el7.ppc64le
kdesdk-common-4.10.5-6.el7.noarch
libvirt-daemon-driver-secret-3.2.0-14.el7.ppc64le
perl-Locale-Maketext-Simple-0.21-292.el7.noarch
gnome-keyring-3.20.0-3.el7.ppc64le
python-sss-murmur-1.15.2-50.el7.ppc64le
vim-enhanced-7.4.160-2.el7.ppc64le
perl-ExtUtils-MakeMaker-6.68-3.el7.noarch
emacs-filesystem-24.3-19.el7_3.noarch
libvncserver-0.9.9-9.el7_0.1.ppc64le
perl-Object-Accessor-0.42-292.el7.noarch
gnome-desktop3-3.22.2-2.el7.ppc64le
python-backports-1.0-8.el7.ppc64le
evolution-help-3.22.6-10.el7.noarch
systemtap-devel-3.1-3.el7.ppc64le
langtable-0.0.31-3.el7.noarch
geocode-glib-3.20.1-1.el7.ppc64le
perl-Compress-Raw-Bzip2-2.061-3.el7.ppc64le
pygtk2-libglade-2.24.0-9.el7.ppc64le
python-urllib3-1.10.2-3.el7.noarch
orca-3.6.3-4.el7.ppc64le
perl-File-Fetch-0.42-2.el7.noarch
latencytop-common-0.5-13.el7.ppc64le
geoclue2-libs-2.4.5-1.el7.ppc64le
perl-Module-Loaded-0.08-292.el7.noarch
webkitgtk4-2.14.7-2.el7.ppc64le
python-paste-1.7.5.1-9.20111221hg1498.el7.noarch
totem-nautilus-3.22.1-1.el7.ppc64le
libtool-2.4.2-22.el7_3.ppc64le
smc-fonts-common-6.0-7.el7.noarch
libnice-0.1.3-4.el7.ppc64le
libdvdnav-5.0.3-1.el7.ppc64le
folks-0.11.3-1.el7.ppc64le
python-ipaddr-2.1.11-1.el7.noarch
xorg-x11-utils-7.5-22.el7.ppc64le
oxygen-icon-theme-4.10.5-2.el7.noarch
libkkc-common-0.3.1-9.el7.noarch
libgovirt-0.3.3-5.el7.ppc64le
boost-timer-1.53.0-27.el7.ppc64le
gnome-packagekit-common-3.22.1-2.el7.ppc64le
javapackages-tools-3.4.1-11.el7.noarch
sane-backends-devel-1.0.24-9.el7.ppc64le
konkretcmpi-0.9.1-5.el7.ppc64le
perl-srpm-macros-1-8.el7.noarch
chrony-3.1-2.el7.centos.ppc64le
fuse-2.9.2-8.el7.ppc64le
evolution-3.22.6-10.el7.ppc64le
python-urwid-1.1.1-3.el7.ppc64le
shotwell-0.24.5-1.el7.ppc64le
libreport-web-2.1.11-38.el7.centos.ppc64le
glibc-2.17-196.el7.ppc64le
usb_modeswitch-data-20160612-2.el7.noarch
patch-2.7.1-8.el7.ppc64le
file-roller-3.22.3-1.el7.ppc64le
python-netaddr-0.7.5-7.el7.noarch
ibus-table-chinese-1.4.6-3.el7.noarch
libreport-plugin-reportuploader-2.1.11-38.el7.centos.ppc64le
pcre-8.32-17.el7.ppc64le
libvirt-daemon-driver-network-3.2.0-14.el7.ppc64le
cyrus-sasl-plain-2.1.26-21.el7.ppc64le
glade-libs-3.20.0-1.el7.ppc64le
python-markupsafe-0.11-10.el7.ppc64le
kdenetwork-devel-4.10.5-8.el7_0.noarch
libreport-plugin-ureport-2.1.11-38.el7.centos.ppc64le
dbus-libs-1.6.12-17.el7.ppc64le
alsa-firmware-1.0.28-2.el7.noarch
mozjs17-17.0.0-19.el7.ppc64le
avahi-ui-gtk3-0.6.31-17.el7.ppc64le
python-cffi-1.6.0-5.el7.ppc64le
xdg-user-dirs-gtk-0.10-4.el7.ppc64le
gavl-1.4.0-4.el7.ppc64le
libjpeg-turbo-1.2.90-5.el7.ppc64le
device-mapper-multipath-0.4.9-111.el7.ppc64le
libcdio-0.92-1.el7.ppc64le
pulseaudio-module-bluetooth-10.0-3.el7.ppc64le
pytalloc-2.1.9-1.el7.ppc64le
ibus-sayura-1.3.2-3.el7.ppc64le
checkpolicy-2.5-4.el7.ppc64le
libICE-1.0.9-9.el7.ppc64le
libvirt-daemon-driver-interface-3.2.0-14.el7.ppc64le
libunistring-0.9.3-9.el7.ppc64le
libXScrnSaver-devel-1.2.2-6.1.el7.ppc64le
openlmi-python-base-0.5.0-4.el7.noarch
PyQt4-devel-4.10.1-13.el7.ppc64le
libndp-1.2-7.el7.ppc64le
libxml2-2.9.1-6.el7_2.3.ppc64le
sssd-krb5-common-1.15.2-50.el7.ppc64le
ncurses-5.9-13.20130511.el7.ppc64le
icedax-1.1.11-23.el7.ppc64le
libmsn-4.2.1-7.el7.ppc64le
evolution-data-server-devel-3.22.7-6.el7.ppc64le
poppler-0.26.5-16.el7.ppc64le
sed-4.2.2-5.el7.ppc64le
sssd-ldap-1.15.2-50.el7.ppc64le
fontconfig-2.10.95-11.el7.ppc64le
pinentry-qt-0.8.1-17.el7.ppc64le
cyrus-sasl-scram-2.1.26-21.el7.ppc64le
paps-0.6.8-28.el7.1.ppc64le
libyaml-0.1.4-11.el7_0.ppc64le
libgpg-error-1.12-3.el7.ppc64le
sgpio-1.2.0.10-13.el7.ppc64le
alsa-lib-1.1.3-3.el7.ppc64le
gutenprint-5.2.9-18.el7.ppc64le
openslp-2.0.0-6.el7.ppc64le
ruby-irb-2.0.0.648-30.el7.noarch
libgcrypt-1.5.3-14.el7.ppc64le
python-blivet-0.61.15.65-1.el7.noarch
gzip-1.5-9.el7.ppc64le
xorg-x11-drv-void-1.4.1-2.el7.ppc64le
nss-pem-1.0.3-4.el7.ppc64le
rubygem-rdoc-4.0.0-30.el7.noarch
libcap-ng-0.7.5-4.el7.ppc64le
rpm-build-libs-4.11.3-25.el7.ppc64le
shared-mime-info-1.8-3.el7.ppc64le
xorg-x11-drv-v4l-0.2.0-47.el7.ppc64le
nss-tools-3.28.4-8.el7.ppc64le
libsemanage-2.5-8.el7.ppc64le
libxcb-1.12-1.el7.ppc64le
flatpak-0.8.7-1.el7.ppc64le
gstreamer1-1.10.4-2.el7.ppc64le
xorg-x11-drv-nouveau-1.0.13-3.el7.ppc64le
sgml-common-0.6.3-39.el7.noarch
util-linux-2.23.2-43.el7.ppc64le
libtdb-1.3.12-2.el7.ppc64le
rpm-devel-4.11.3-25.el7.ppc64le
gobject-introspection-1.50.0-1.el7.ppc64le
qdox-1.12.1-10.el7.noarch
libteam-1.25-5.el7.ppc64le
openssh-clients-7.4p1-11.el7.ppc64le
libattr-2.4.46-12.el7.ppc64le
python-meh-0.25.2-1.el7.noarch
avahi-glib-0.6.31-17.el7.ppc64le
rhino-1.7R5-1.el7.noarch
perl-Pod-Checker-1.60-2.el7.noarch
rarian-0.8.1-11.el7.ppc64le
gmp-6.0.0-15.el7.ppc64le
createrepo-0.9.9-28.el7.noarch
python-gobject-base-3.22.0-1.el7.ppc64le
telepathy-haze-0.8.0-1.el7.ppc64le
perl-Version-Requirements-0.101022-244.el7.noarch
tog-pegasus-2.14.1-5.el7.ppc64le
lua-5.1.4-15.el7.ppc64le
libburn-1.2.8-4.el7.ppc64le
openssl-1.0.2k-8.el7.ppc64le
dleyna-server-0.5.0-1.el7.ppc64le
perl-IO-HTML-1.00-2.el7.noarch
libsemanage-python-2.5-8.el7.ppc64le
libidn-1.28-4.el7.ppc64le
nss-devel-3.28.4-8.el7.ppc64le
net-snmp-libs-5.7.2-28.el7.ppc64le
paps-libs-0.6.8-28.el7.1.ppc64le
perl-DBIx-Simple-1.35-7.el7.noarch
lzo-minilzo-2.06-8.el7.ppc64le
libref_array-0.1.5-27.el7.ppc64le
libX11-1.6.5-1.el7.ppc64le
xdg-utils-1.1.0-0.17.20120809git.el7.noarch
harfbuzz-devel-1.3.2-1.el7.ppc64le
perl-CGI-3.63-4.el7.noarch
libini_config-1.3.0-27.el7.ppc64le
xmlrpc-c-1.32.5-1905.svn2451.el7.ppc64le
libXfixes-5.0.3-1.el7.ppc64le
glibmm24-2.50.0-1.el7.ppc64le
webkitgtk4-devel-2.14.7-2.el7.ppc64le
perl-Devel-Symdump-2.10-2.el7.noarch
libpipeline-1.2.3-3.el7.ppc64le
mpfr-3.1.1-4.el7.ppc64le
libXrandr-1.5.1-2.el7.ppc64le
cyrus-sasl-gssapi-2.1.26-21.el7.ppc64le
gtk2-devel-2.24.31-1.el7.ppc64le
perl-URI-1.60-9.el7.noarch
kpartx-0.4.9-111.el7.ppc64le
file-libs-5.11-33.el7.ppc64le
libXext-devel-1.3.3-3.el7.ppc64le
libSM-devel-1.2.2-2.el7.ppc64le
qt-devel-4.8.5-13.el7.ppc64le
perl-HTTP-Date-6.02-8.el7.noarch
dracut-033-502.el7.ppc64le
libtool-ltdl-2.4.2-22.el7_3.ppc64le
libcanberra-0.30-5.el7.ppc64le
python-enum34-1.0.4-1.el7.noarch
libxkbfile-devel-1.0.9-3.el7.ppc64le
perl-HTTP-Cookies-6.01-5.el7.noarch
polkit-0.112-12.el7_3.ppc64le
libtheora-1.1.1-8.el7.ppc64le
libXpm-3.5.12-1.el7.ppc64le
libevent-2.0.21-4.el7.ppc64le
ibus-gtk2-1.5.3-13.el7.ppc64le
kdelibs-common-4.14.8-6.el7_3.ppc64le
systemd-sysv-219-42.el7.ppc64le
diffutils-3.3-4.el7.ppc64le
libXv-1.0.11-1.el7.ppc64le
pam-1.1.8-18.el7.ppc64le
imsettings-gsettings-1.6.3-9.el7.ppc64le
perl-YAML-Tiny-1.51-6.el7.noarch
GConf2-3.2.6-8.el7.ppc64le
libtasn1-4.10-1.el7.ppc64le
libxkbfile-1.0.9-3.el7.ppc64le
gettext-libs-0.19.8.1-2.el7.ppc64le
kdelibs-ktexteditor-4.14.8-6.el7_3.ppc64le
perl-Env-1.04-2.el7.noarch
libpciaccess-0.13.4-3.el7_3.ppc64le
nss-softokn-3.28.3-6.el7.ppc64le
pango-1.40.4-1.el7.ppc64le
telepathy-logger-0.8.0-5.el7.ppc64le
nepomuk-core-4.10.5-5.el7.ppc64le
perl-Net-HTTP-6.06-2.el7.noarch
samba-common-4.6.2-8.el7.noarch
libsigc++20-2.10.0-1.el7.ppc64le
cogl-1.22.2-1.el7.ppc64le
pcre-devel-8.32-17.el7.ppc64le
kdenetwork-kopete-libs-4.10.5-8.el7_0.ppc64le
icoutils-0.31.3-1.el7_3.ppc64le
pyparted-3.9-13.el7.ppc64le
apr-util-1.5.2-6.el7.ppc64le
giflib-4.1.6-9.el7.ppc64le
expat-devel-2.1.0-10.el7_3.ppc64le
kdesdk-okteta-4.10.5-6.el7.ppc64le
papi-5.2.0-23.el7.ppc64le
abrt-python-2.1.11-48.el7.centos.ppc64le
lzo-2.06-8.el7.ppc64le
java-1.8.0-openjdk-1.8.0.131-11.b12.el7.ppc64le
libffi-devel-3.0.13-18.el7.ppc64le
kwin-libs-4.11.19-8.el7.ppc64le
xorg-x11-font-utils-7.5-20.el7.ppc64le
iscsi-initiator-utils-iscsiuio-6.2.0.874-4.el7.ppc64le
file-5.11-33.el7.ppc64le
libXft-devel-2.3.2-2.el7.ppc64le
libipa_hbac-1.15.2-50.el7.ppc64le
kwin-gles-libs-4.11.19-8.el7.ppc64le
libsamplerate-0.1.8-6.el7.ppc64le
cronie-1.4.11-17.el7.ppc64le
xml-common-0.6.3-39.el7.noarch
ghostscript-9.07-28.el7.ppc64le
libpinyin-data-0.9.93-4.el7.ppc64le
kde-runtime-libs-4.10.5-8.el7.ppc64le
ipset-6.29-1.el7.ppc64le
plymouth-0.8.9-0.28.20140113.el7.centos.ppc64le
taglib-1.8-7.20130218git.el7.ppc64le
at-spi2-core-2.22.0-1.el7.ppc64le
xfsprogs-4.5.0-12.el7.ppc64le
kdepim-runtime-4.10.5-3.el7.ppc64le
libusbmuxd-1.0.10-5.el7.ppc64le
libstoragemgmt-python-1.4.0-3.el7.noarch
libseccomp-2.3.1-3.el7.ppc64le
gstreamer1-plugins-good-1.10.4-2.el7.ppc64le
pyusb-1.0.0-0.11.b1.el7.noarch
nepomuk-core-devel-4.10.5-5.el7.ppc64le
libofa-0.9.3-24.el7.ppc64le
device-mapper-event-1.02.140-8.el7.ppc64le
librtas-2.0.1-1.el7.ppc64le
libXcomposite-devel-0.4.4-4.1.el7.ppc64le
audit-libs-python-2.7.6-3.el7.ppc64le
okular-libs-4.10.5-4.el7.ppc64le
gdisk-0.8.6-5.el7.ppc64le
libibumad-13-7.el7.ppc64le
libsndfile-1.0.25-10.el7.ppc64le
libXxf86misc-1.0.3-7.1.el7.ppc64le
pyparsing-1.5.6-9.el7.noarch
kdesdk-kmtrace-libs-4.10.5-6.el7.ppc64le
attr-2.4.46-12.el7.ppc64le
rpcbind-0.2.0-42.el7.ppc64le
slang-2.2.4-11.el7.ppc64le
gtk2-2.24.31-1.el7.ppc64le
libssh2-1.4.3-10.el7_2.1.ppc64le
kdesdk-kompare-4.10.5-6.el7.ppc64le
openssl-devel-1.0.2k-8.el7.ppc64le
bluez-5.44-2.el7.ppc64le
boost-thread-1.53.0-27.el7.ppc64le
clutter-gtk-1.8.2-1.el7.ppc64le
soundtouch-1.4.0-9.el7.ppc64le
ibus-table-1.5.0-5.el7.noarch
setools-libs-3.3.8-1.1.el7.ppc64le
ppp-2.4.5-33.el7.ppc64le
libvpd-2.2.5-1.el7.ppc64le
clutter-gst3-3.0.22-1.el7.ppc64le
boost-test-1.53.0-27.el7.ppc64le
libgphoto2-2.5.2-5.el7.ppc64le
libcurl-7.29.0-42.el7.ppc64le
libmtp-1.1.6-5.el7.ppc64le
unzip-6.0-16.el7.ppc64le
vte291-0.46.2-1.el7.ppc64le
boost-random-1.53.0-27.el7.ppc64le
hplip-libs-3.15.9-3.el7.ppc64le
openldap-2.4.44-5.el7.ppc64le
rsync-3.0.9-18.el7.ppc64le
psmisc-22.20-15.el7.ppc64le
compat-cheese314-3.14.2-1.el7.ppc64le
dosfstools-3.0.20-9.el7.ppc64le
sane-backends-drivers-cameras-1.0.24-9.el7.ppc64le
kde-filesystem-4-47.el7.ppc64le
cryptsetup-1.7.4-3.el7.ppc64le
boost-program-options-1.53.0-27.el7.ppc64le
libgnomekbd-3.22.0.1-1.el7.ppc64le
libsrtp-1.4.4-10.20101004cvs.el7.ppc64le
speech-dispatcher-python-0.7.1-15.el7.ppc64le
raptor2-2.0.9-3.el7.ppc64le
grub2-tools-2.02-0.64.el7.centos.ppc64le
libiodbc-3.52.7-7.el7.ppc64le
gtk-vnc2-0.7.0-2.el7.ppc64le
libdv-1.0.0-17.el7.ppc64le
libXxf86dga-1.1.4-2.1.el7.ppc64le
python-deltarpm-3.6-3.el7.ppc64le
ibacm-13-7.el7.ppc64le
opus-1.0.2-6.el7.ppc64le
system-config-printer-libs-1.4.1-19.el7.noarch
libthai-0.1.14-9.el7.ppc64le
tracker-1.10.5-4.el7.ppc64le
shared-desktop-ontologies-devel-0.11.0-2.el7.noarch
qt-4.8.5-13.el7.ppc64le
pcre2-10.23-2.el7.ppc64le
gtkspell3-3.0.3-4.el7.ppc64le
libevdev-1.5.6-1.el7.ppc64le
totem-3.22.1-1.el7.ppc64le
virtuoso-opensource-6.1.6-6.el7.ppc64le
strigi-libs-0.7.7-12.20120626.el7.ppc64le
boost-wave-1.53.0-27.el7.ppc64le
libXmu-devel-1.1.2-2.el7.ppc64le
iproute-3.10.0-87.el7.ppc64le
firewalld-0.4.4.4-6.el7.noarch
color-filesystem-1-13.el7.noarch
automoc-1.0-0.20.rc3.el7.ppc64le
perl-Pod-Perldoc-3.20-4.el7.noarch
poppler-utils-0.26.5-16.el7.ppc64le
boost-1.53.0-27.el7.ppc64le
pcp-libs-3.11.8-7.el7.ppc64le
pykickstart-1.99.66.12-1.el7.noarch
openldap-devel-2.4.44-5.el7.ppc64le
perl-Encode-2.51-7.el7.ppc64le
python-gobject-3.22.0-1.el7.ppc64le
krb5-workstation-1.15.1-8.el7.ppc64le
libwacom-0.24-1.el7.ppc64le
isomd5sum-1.0.10-5.el7.ppc64le
abrt-addon-vmcore-2.1.11-48.el7.centos.ppc64le
perl-constant-1.27-2.el7.noarch
compat-libcogl12-1.14.0-3.el7.ppc64le
python-libipa_hbac-1.15.2-50.el7.ppc64le
gdm-3.22.3-11.el7.ppc64le
gstreamer1-devel-1.10.4-2.el7.ppc64le
abrt-retrace-client-2.1.11-48.el7.centos.ppc64le
perl-Exporter-5.68-3.el7.noarch
libXpm-devel-3.5.12-1.el7.ppc64le
python2-pyasn1-modules-0.1.9-7.el7.noarch
gnome-shell-extension-alternate-tab-3.22.2-10.el7.noarch
ttmkfdir-3.0.9-42.el7.ppc64le
samba-libs-4.6.2-8.el7.ppc64le
perl-File-Temp-0.23.01-3.el7.noarch
brltty-4.5-15.el7.ppc64le
sos-3.4-6.el7.centos.noarch
gnome-shell-extension-window-list-3.22.2-10.el7.noarch
clucene-core-2.3.3.4-11.el7.ppc64le
osinfo-db-20170423-2.el7.noarch
perl-macros-5.16.3-292.el7.ppc64le
python-brlapi-0.6.0-15.el7.ppc64le
libselinux-devel-2.5-11.el7.ppc64le
quota-nls-4.01-14.el7.noarch
elfutils-libs-0.168-8.el7.ppc64le
oddjob-mkhomedir-0.31.5-4.el7.ppc64le
perl-5.16.3-292.el7.ppc64le
opal-3.10.10-4.el7.ppc64le
gstreamer-tools-0.10.36-7.el7.ppc64le
libvirt-daemon-driver-storage-scsi-3.2.0-14.el7.ppc64le
satyr-0.13-14.el7.ppc64le
polkit-docs-0.112-12.el7_3.noarch
perl-Compress-Raw-Zlib-2.061-4.el7.ppc64le
compat-libcogl-pango12-1.14.0-3.el7.ppc64le
alsa-lib-devel-1.1.3-3.el7.ppc64le
libvirt-daemon-driver-storage-mpath-3.2.0-14.el7.ppc64le
NetworkManager-libnm-1.8.0-9.el7.ppc64le
tcsh-6.18.01-15.el7.ppc64le
perl-XML-Dumper-0.81-17.el7.noarch
libpfm-devel-4.7.0-4.el7.ppc64le
unixODBC-devel-2.3.1-11.el7.ppc64le
rcs-5.9.0-5.el7.ppc64le
ltrace-0.7.91-14.el7.ppc64le
ed-1.9-4.el7.ppc64le
wqy-zenhei-fonts-0.9.46-11.el7.noarch
lohit-bengali-fonts-2.5.3-4.el7.noarch
paratype-pt-sans-fonts-20101909-3.el7.noarch
paktype-naskh-basic-fonts-4.1-3.el7.noarch
lklug-fonts-0.6-10.20090803cvs.el7.noarch
lohit-kannada-fonts-2.5.3-3.el7.noarch
cjkuni-uming-fonts-0.2.20080216.1-53.el7.noarch
vlgothic-fonts-20130607-2.el7.noarch
lohit-telugu-fonts-2.5.3-3.el7.noarch
gnu-free-serif-fonts-20120503-8.el7.noarch
jomolhari-fonts-0.003-17.el7.noarch
scl-utils-20130529-17.el7_1.ppc64le
diffstat-1.57-4.el7.ppc64le
xorg-x11-drivers-7.7-6.el7.ppc64le
setserial-2.17-33.el7.ppc64le
vinagre-3.22.0-8.el7.ppc64le
man-pages-overrides-7.4.3-1.el7.ppc64le
gedit-3.22.0-3.el7.ppc64le
iwl5150-firmware-8.24.2.2-56.el7.noarch
gnome-contacts-3.22.1-1.el7.ppc64le
words-3.0-22.el7.noarch
setroubleshoot-3.2.28-3.el7.ppc64le
iwl7265-firmware-22.0.7.0-56.el7.noarch
gnome-system-monitor-3.22.2-2.el7.ppc64le
man-pages-3.53-5.el7.noarch
librsvg2-devel-2.40.16-1.el7.ppc64le
gpg-pubkey-f4a80eb5-53a7ff4b
system-config-printer-udev-1.4.1-19.el7.ppc64le
gnome-calculator-3.22.3-1.el7.ppc64le
gvfs-afp-1.30.4-3.el7.ppc64le
latencytop-0.5-13.el7.ppc64le
gtk3-immodule-xim-3.22.10-4.el7.ppc64le
mousetweaks-3.12.0-1.el7.ppc64le
qt3-MySQL-3.3.8b-51.el7.ppc64le
xvattr-1.3-27.el7.ppc64le
yum-langpacks-0.4.2-7.el7.noarch
rpm-build-4.11.3-25.el7.ppc64le
virt-install-1.4.1-7.el7.noarch
samba-client-4.6.2-8.el7.ppc64le
qt-odbc-4.8.5-13.el7.ppc64le
NetworkManager-tui-1.8.0-9.el7.ppc64le
avahi-0.6.31-17.el7.ppc64le
httpd-manual-2.4.6-67.el7.centos.noarch
PackageKit-gstreamer-plugin-1.1.5-1.el7.centos.ppc64le
tuned-2.8.0-5.el7.noarch
qemu-guest-agent-2.8.0-2.el7.ppc64le
smartmontools-6.2-8.el7.ppc64le
openssh-server-7.4p1-11.el7.ppc64le
dracut-config-rescue-033-502.el7.ppc64le
openlmi-providers-devel-0.5.0-4.el7.ppc64le
oprofile-0.9.9-22.el7.ppc64le
gcc-c++-4.8.5-16.el7.ppc64le
perl-homedir-1.008010-4.el7.noarch
libgudev1-devel-219-42.el7.ppc64le
sudo-1.8.19p2-10.el7.ppc64le
libacl-devel-2.2.51-12.el7.ppc64le
perl-XML-Twig-3.44-2.el7.noarch
crash-trace-command-2.0-12.el7.ppc64le
crash-gcore-command-1.3.1-0.el7.ppc64le
libgnome-keyring-devel-3.12.0-1.el7.ppc64le
binutils-devel-2.25.1-31.base.el7.ppc64le
libcap-ng-devel-0.7.5-4.el7.ppc64le
bash-completion-2.1-6.el7.noarch
dstat-0.7.2-12.el7.noarch
wget-1.14-15.el7.ppc64le
gpg-pubkey-352c64e5-52ae6884
certmonger-0.78.4-3.el7.ppc64le
libatomic-static-4.8.5-16.el7.ppc64le
libicu-devel-50.1.2-15.el7.ppc64le
caribou-0.4.21-1.el7.ppc64le
grub2-common-2.02-0.64.el7.centos.noarch
plymouth-graphics-libs-0.8.9-0.28.20140113.el7.centos.ppc64le
kernel-3.10.0-693.el7.ppc64le
perl-Perl-OSType-1.003-3.el7.noarch
libvirt-daemon-3.2.0-14.el7.ppc64le
ledmon-0.80-2.el7.ppc64le
gupnp-av-0.12.10-1.el7.ppc64le
cups-1.6.3-29.el7.ppc64le
mozilla-filesystem-1.9-11.el7.ppc64le
libqmi-utils-1.16.0-1.el7.ppc64le
anaconda-core-21.48.22.121-1.el7.centos.ppc64le
perl-JSON-PP-2.27202-2.el7.noarch
libvirt-client-3.2.0-14.el7.ppc64le
numactl-devel-2.0.9-6.el7_2.ppc64le
cups-client-1.6.3-29.el7.ppc64le
mutter-3.22.3-11.el7.ppc64le
ipa-common-4.5.0-20.el7.centos.noarch
glibc-devel-2.17-196.el7.ppc64le
firefox-52.2.0-2.el7.centos.ppc64le
perl-Params-Check-0.38-2.el7.noarch
virt-manager-common-1.4.1-7.el7.noarch
indent-2.2.11-13.el7.ppc64le
python-linux-procfs-0.4.9-3.el7.noarch
gnome-session-3.22.3-4.el7.ppc64le
adwaita-cursor-theme-3.22.0-1.el7.noarch
perl-Archive-Extract-0.68-3.el7.noarch
gnome-initial-setup-3.22.1-4.el7.ppc64le
perl-IO-Compress-2.061-2.el7.noarch
geoclue2-2.4.5-1.el7.ppc64le
khmeros-base-fonts-5.0-17.el7.noarch
python-tempita-0.5.1-6.el7.noarch
gnome-online-accounts-3.22.5-1.el7.ppc64le
nhn-nanum-fonts-common-3.020-9.el7.noarch
gobject-introspection-devel-1.50.0-1.el7.ppc64le
rhythmbox-3.4.1-1.el7.ppc64le
libavc1394-0.5.3-14.el7.ppc64le
telepathy-gabble-0.18.1-4.el7.ppc64le
stix-fonts-1.1.0-5.el7.noarch
python-javapackages-3.4.1-11.el7.noarch
gnome-packagekit-installer-3.22.1-2.el7.ppc64le
mesa-filesystem-17.0.1-6.20170307.el7.ppc64le
konkretcmpi-python-0.9.1-5.el7.ppc64le
libsane-hpaio-3.15.9-3.el7.ppc64le
copy-jdk-configs-2.2-3.el7.noarch
usb_modeswitch-2.4.0-5.el7.ppc64le
nhn-nanum-gothic-fonts-3.020-9.el7.noarch
pytz-2016.10-2.el7.noarch
librsvg2-tools-2.40.16-1.el7.ppc64le
bash-4.2.46-28.el7.ppc64le
libreport-plugin-bugzilla-2.1.11-38.el7.centos.ppc64le
kde-workspace-devel-4.11.19-8.el7.ppc64le
libdb-devel-5.3.21-20.el7.ppc64le
fxload-2002_04_11-16.el7.ppc64le
google-crosextra-caladea-fonts-1.002-0.4.20130214.el7.noarch
python-pycparser-2.14-1.el7.noarch
libtimezonemap-0.4.4-1.el7.ppc64le
libcom_err-1.42.9-10.el7.ppc64le
frei0r-plugins-1.3-13.el7.ppc64le
ibus-m17n-1.3.4-13.el7.ppc64le
libcdio-paranoia-10.2+0.90-11.el7.ppc64le
netcf-libs-0.2.8-4.el7.ppc64le
lohit-punjabi-fonts-2.5.3-2.el7.noarch
cmpi-bindings-pywbem-0.9.5-6.el7.ppc64le
at-spi2-core-devel-2.22.0-1.el7.ppc64le
xz-libs-5.2.2-1.el7.ppc64le
libasyncns-0.8-7.el7.ppc64le
libcanberra-devel-0.30-5.el7.ppc64le
coreutils-8.22-18.el7.ppc64le
sssd-ad-1.15.2-50.el7.ppc64le
doxygen-1.8.5-3.el7.ppc64le
httpd-tools-2.4.6-67.el7.centos.ppc64le
libspectre-0.2.8-1.el7.ppc64le
cyrus-sasl-lib-2.1.26-21.el7.ppc64le
rubygem-bigdecimal-1.2.0-30.el7.ppc64le
icedtea-web-1.6.2-4.el7.ppc64le
libarchive-3.1.2-10.el7_2.ppc64le
python-pyblock-0.53-6.el7.ppc64le
byacc-1.9.20130304-3.el7.ppc64le
wodim-1.1.11-23.el7.ppc64le
xorg-x11-drv-qxl-0.1.5-3.el7.ppc64le
elfutils-libelf-0.168-8.el7.ppc64le
rubygem-thor-0.19.1-1.el7.noarch
file-roller-nautilus-3.22.3-1.el7.ppc64le
pkgconfig-0.27.1-4.el7.ppc64le
setroubleshoot-server-3.2.28-3.el7.ppc64le
iwl2030-firmware-18.168.6.1-56.el7.noarch
mailx-12.5-16.el7.ppc64le
xorg-x11-drv-fbdev-0.4.3-25.el7.ppc64le
libtevent-0.9.31-1.el7.ppc64le
policycoreutils-2.5-17.1.el7.ppc64le
java-1.7.0-openjdk-devel-1.7.0.141-2.6.10.5.el7.ppc64le
gsettings-desktop-schemas-3.22.0-1.el7.ppc64le
yum-3.4.3-154.el7.centos.noarch
iwl6000g2a-firmware-17.168.5.3-56.el7.noarch
perl-B-Lint-1.17-3.el7.noarch
gstreamer-plugins-bad-free-0.10.23-23.el7.ppc64le
libvorbis-1.3.3-8.el7.ppc64le
rarian-compat-0.8.1-11.el7.ppc64le
abrt-desktop-2.1.11-48.el7.centos.ppc64le
desktop-file-utils-0.23-1.el7.ppc64le
libiptcdata-1.0.4-11.el7.ppc64le
gpg-pubkey-f533f4fa-56585169
perl-DB_File-1.830-6.el7.ppc64le
compat-poppler022-qt-0.22.5-4.el7.ppc64le
libldb-1.1.29-1.el7.ppc64le
http-parser-2.7.1-1.el7.ppc64le
NetworkManager-libreswan-gnome-1.2.4-2.el7.ppc64le
centos-logos-70.0.6-3.el7.centos.noarch
libX11-common-1.6.5-1.el7.noarch
perl-FCGI-0.74-8.el7.ppc64le
pango-devel-1.40.4-1.el7.ppc64le
libbasicobjects-0.1.1-27.el7.ppc64le
libgfortran-4.8.5-16.el7.ppc64le
gtk2-immodule-xim-2.24.31-1.el7.ppc64le
libgnome-keyring-3.12.0-1.el7.ppc64le
libXrender-0.9.10-1.el7.ppc64le
perl-Business-ISBN-2.06-2.el7.noarch
freeglut-2.8.1-3.el7.ppc64le
libgomp-4.8.5-16.el7.ppc64le
device-mapper-1.02.140-8.el7.ppc64le
xdg-desktop-portal-gtk-0.5-1.el7.ppc64le
libudisks2-2.1.2-6.el7.ppc64le
pulseaudio-libs-10.0-3.el7.ppc64le
perl-HTTP-Daemon-6.01-5.el7.noarch
xorg-x11-xauth-1.0.9-1.el7.ppc64le
nettle-2.7.1-8.el7.ppc64le
polkit-pkla-compat-0.1-4.el7.ppc64le
startup-notification-devel-0.12-8.el7.ppc64le
genisoimage-1.1.11-23.el7.ppc64le
dbus-x11-1.6.12-17.el7.ppc64le
perl-Text-Soundex-3.04-4.el7.ppc64le
xdg-user-dirs-0.15-4.el7.ppc64le
jansson-2.10-1.el7.ppc64le
NetworkManager-glib-1.8.0-9.el7.ppc64le
rpm-sign-4.11.3-25.el7.ppc64le
gettext-0.19.8.1-2.el7.ppc64le
cairo-1.14.8-2.el7.ppc64le
perl-IO-Socket-SSL-1.94-6.el7.noarch
kdepimlibs-kxmlrpcclient-4.10.5-4.el7.ppc64le
libplist-1.12-3.el7.ppc64le
libwbclient-4.6.2-8.el7.ppc64le
cgdcbxd-1.0.2-7.el7.ppc64le
glib2-devel-2.50.3-3.el7.ppc64le
gdk-pixbuf2-devel-2.36.5-1.el7.ppc64le
theora-tools-1.1.1-8.el7.ppc64le
libkipi-4.10.5-3.el7.ppc64le
libmng-1.0.10-14.el7.ppc64le
abrt-addon-kerneloops-2.1.11-48.el7.centos.ppc64le
grub2-2.02-0.64.el7.centos.ppc64le
xz-devel-5.2.2-1.el7.ppc64le
xorg-x11-xkb-utils-7.7-12.el7.ppc64le
libverto-tevent-0.2.5-4.el7.ppc64le
libkdcraw-devel-4.10.5-4.el7.ppc64le
bzip2-1.0.6-13.el7.ppc64le
iputils-20160308-10.el7.ppc64le
cifs-utils-6.2-10.el7.ppc64le
libpinyin-0.9.93-4.el7.ppc64le
libao-1.1.0-8.el7.ppc64le
gdbm-devel-1.10-8.el7.ppc64le
kdepim-libs-4.10.5-6.el7.ppc64le
libxshmfence-1.2-1.el7.ppc64le
libstoragemgmt-1.4.0-3.el7.ppc64le
psacct-6.6.1-13.el7.ppc64le
pyliblzma-0.5.3-11.el7.ppc64le
libXcursor-devel-1.1.14-8.el7.ppc64le
hesiod-3.2.1-3.el7.ppc64le
okular-devel-4.10.5-4.el7.ppc64le
gsm-1.0.13-11.el7.ppc64le
telepathy-mission-control-5.16.3-3.el7.ppc64le
rng-tools-5-11.el7.ppc64le
python-chardet-2.2.1-1.el7_1.noarch
libcanberra-gtk3-0.30-5.el7.ppc64le
krb5-devel-1.15.1-8.el7.ppc64le
kdesdk-kompare-devel-4.10.5-6.el7.ppc64le
unixODBC-2.3.1-11.el7.ppc64le
dbus-devel-1.6.12-17.el7.ppc64le
kpatch-0.4.0-1.el7.noarch
graphite2-1.3.6-1.el7_2.ppc64le
nautilus-extensions-3.22.3-3.el7.ppc64le
libdb-utils-5.3.21-20.el7.ppc64le
sane-backends-libs-1.0.24-9.el7.ppc64le
zip-3.0-11.el7.ppc64le
mdadm-4.0-5.el7.ppc64le
memstomp-0.1.4-11.el7.ppc64le
libconfig-1.4.9-5.el7.ppc64le
clutter-gst2-2.0.18-1.el7.ppc64le
postgresql-libs-9.2.21-1.el7.ppc64le
gsound-1.0.2-2.el7.ppc64le
ilmbase-1.0.3-7.el7.ppc64le
udisks2-2.1.2-6.el7.ppc64le
perl-core-5.16.3-292.el7.ppc64le
pcsc-lite-libs-1.8.8-6.el7.ppc64le
gvnc-0.7.0-2.el7.ppc64le
qemu-img-1.5.3-141.el7.ppc64le
libappstream-glib-0.6.10-1.el7.ppc64le
sg3_utils-libs-1.37-12.el7.ppc64le
librdmacm-13-7.el7.ppc64le
adcli-0.8.1-3.el7.ppc64le
libnfnetlink-1.0.1-4.el7.ppc64le
colord-gtk-0.1.25-4.el7.ppc64le
libuser-python-0.60-7.el7_1.ppc64le
libfprint-0.5.0-4.el7.ppc64le
OpenEXR-libs-1.7.1-7.el7.ppc64le
attica-devel-0.4.2-1.el7.ppc64le
papi-devel-5.2.0-23.el7.ppc64le
m17n-lib-1.6.4-14.el7.ppc64le
qimageblitz-0.0.6-7.el7.ppc64le
python-urlgrabber-3.10-8.el7.noarch
pcp-selinux-3.11.8-7.el7.ppc64le
perl-Text-ParseWords-3.29-4.el7.noarch
apr-util-devel-1.5.2-6.el7.ppc64le
readline-devel-6.2-10.el7.ppc64le
python-kitchen-1.1.1-5.el7.noarch
gnome-abrt-0.3.4-8.el7.ppc64le
check-devel-0.9.9-5.el7.ppc64le
pulseaudio-gdm-hooks-10.0-3.el7.ppc64le
perl-Scalar-List-Utils-1.27-248.el7.ppc64le
abrt-addon-ccpp-2.1.11-48.el7.centos.ppc64le
gnome-icon-theme-extras-3.12.0-1.el7.noarch
python-slip-0.4.0-2.el7.noarch
brlapi-0.6.0-15.el7.ppc64le
qpdf-libs-5.0.1-3.el7.ppc64le
yelp-xsl-3.20.1-1.el7.noarch
perl-Storable-2.45-3.el7.ppc64le
libosinfo-1.0.0-1.el7.ppc64le
libcap-devel-2.22-9.el7.ppc64le
libepoxy-devel-1.3.1-1.el7.ppc64le
festival-1.96-28.el7.ppc64le
libusbx-1.0.20-1.el7.ppc64le
libvirt-daemon-driver-storage-disk-3.2.0-14.el7.ppc64le
perl-Test-Harness-3.28-3.el7.noarch
polkit-devel-0.112-12.el7_3.ppc64le
perl-Crypt-SSLeay-0.64-5.el7.ppc64le
libverto-devel-0.2.5-4.el7.ppc64le
caribou-gtk2-module-0.4.21-1.el7.ppc64le
vim-filesystem-7.4.160-2.el7.ppc64le
procps-ng-3.3.10-16.el7.ppc64le
NetworkManager-libreswan-1.2.4-2.el7.ppc64le
perl-Module-Metadata-1.000018-2.el7.noarch
pixman-devel-0.34.0-1.el7.ppc64le
patchutils-0.3.3-4.el7.ppc64le
filesystem-3.2-21.el7.ppc64le
cups-filesystem-1.6.3-29.el7.noarch
gettext-devel-0.19.8.1-2.el7.ppc64le
usbredir-0.7.1-2.el7.ppc64le
neon-0.30.0-3.el7.ppc64le
perl-LWP-MediaTypes-6.02-2.el7.noarch
python-qrcode-core-5.0.1-1.el7.noarch
hyphen-en-2.8.6-5.el7.noarch
gnu-free-fonts-common-20120503-8.el7.noarch
gtkmm30-3.22.0-1.el7.ppc64le
initial-setup-gui-0.3.9.40-1.el7.centos.ppc64le
libhugetlbfs-2.16-12.el7.ppc64le
subversion-libs-1.7.14-10.el7.ppc64le
perl-Encode-Locale-1.03-5.el7.noarch
python-inotify-0.9.4-4.el7.noarch
nano-2.3.1-10.el7.ppc64le
mobile-broadband-provider-info-1.20170310-1.el7.noarch
adwaita-gtk2-theme-3.22.2-1.el7.ppc64le
ipa-client-4.5.0-20.el7.centos.ppc64le
perl-IPC-Cmd-0.80-4.el7.noarch
libsoup-2.56.0-3.el7.ppc64le
perl-Term-UI-0.36-2.el7.noarch
python-setuptools-0.9.8-7.el7.noarch
dejavu-sans-mono-fonts-2.33-6.el7.noarch
bind-license-9.9.4-50.el7.noarch
webkitgtk4-jsc-2.14.7-2.el7.ppc64le
firewall-config-0.4.4.4-6.el7.noarch
perl-CPAN-1.9800-292.el7.noarch
gupnp-1.0.1-1.el7.ppc64le
boost-graph-1.53.0-27.el7.ppc64le
python-perf-3.10.0-693.el7.ppc64le
overpass-fonts-2.1-1.el7.noarch
thai-scalable-fonts-common-0.5.0-7.el7.noarch
webkitgtk4-jsc-devel-2.14.7-2.el7.ppc64le
pulseaudio-module-x11-10.0-3.el7.ppc64le
marisa-0.2.4-4.el7.ppc64le
gnutls-c++-3.3.26-9.el7.ppc64le
ca-certificates-2017.2.14-71.el7.noarch
python-idna-2.4-1.el7.noarch
strace-4.12-4.el7.ppc64le
nss-softokn-freebl-3.28.3-6.el7.ppc64le
vino-3.22.0-3.el7.ppc64le
libXaw-devel-1.0.13-4.el7.ppc64le
libreport-centos-2.1.11-38.el7.centos.ppc64le
alsa-utils-1.1.3-2.el7.ppc64le
libnl3-cli-3.2.28-4.el7.ppc64le
python-iniparse-0.4-9.el7.noarch
traceroute-2.0.22-2.el7.ppc64le
libselinux-2.5-11.el7.ppc64le
keybinder3-0.3.0-1.el7.ppc64le
kdepim-devel-4.10.5-6.el7.ppc64le
pakchois-0.4-10.el7.ppc64le
cryptsetup-python-1.7.4-3.el7.ppc64le
libjpeg-turbo-devel-1.2.90-5.el7.ppc64le
python-jwcrypto-0.2.1-1.el7.noarch
lohit-malayalam-fonts-2.5.3-2.el7.noarch
libpng-1.5.13-7.el7_2.ppc64le
freerdp-plugins-1.0.2-10.el7.ppc64le
ibus-chewing-1.4.4-14.el7.ppc64le
libfastjson-0.99.4-2.el7.ppc64le
libsss_sudo-1.15.2-50.el7.ppc64le
redhat-menus-12.0.2-8.el7.noarch
bind-libs-9.9.4-50.el7.ppc64le
gnu-free-sans-fonts-20120503-8.el7.noarch
libuuid-2.23.2-43.el7.ppc64le
festival-freebsoft-utils-0.10-7.el7.noarch
unique3-devel-3.0.2-8.el7.ppc64le
compat-poppler022-0.22.5-4.el7.ppc64le
sssd-proxy-1.15.2-50.el7.ppc64le
python-2.7.5-58.el7.ppc64le
libwvstreams-4.6.1-11.el7.ppc64le
lrzsz-0.12.20-36.el7.ppc64le
sqlite-3.7.17-8.el7.ppc64le
xorg-x11-server-common-1.19.3-11.el7.ppc64le
sushi-3.21.91-1.el7.ppc64le
rubygem-psych-2.0.0-30.el7.ppc64le
gnupg2-2.0.22-4.el7.ppc64le
libmount-2.23.2-43.el7.ppc64le
nss-3.28.4-8.el7.ppc64le
iwl3160-firmware-22.0.7.0-56.el7.noarch
libnl3-3.2.28-4.el7.ppc64le
xorg-x11-drv-ati-7.7.1-3.20160928git3fc839ff.el7.ppc64le
evolution-mapi-3.22.6-1.el7.ppc64le
libservicelog-1.1.17-2.el7.ppc64le
perl-PAR-Dist-0.49-2.el7.noarch
dbus-glib-0.100-7.el7.ppc64le
docbook-style-xsl-1.78.1-3.el7.noarch
iwl100-firmware-39.31.5.1-56.el7.noarch
libxslt-1.1.28-5.el7.ppc64le
junit-4.11-8.el7.noarch
gnome-session-xsession-3.22.3-4.el7.ppc64le
selinux-policy-3.13.1-166.el7.noarch
PackageKit-1.1.5-1.el7.centos.ppc64le
zlib-devel-1.2.7-17.el7.ppc64le
perl-libxml-perl-0.08-19.el7.noarch
iwl4965-firmware-228.61.2.24-56.el7.noarch
p11-kit-0.23.5-3.el7.ppc64le
spice-gtk3-0.33-6.el7.ppc64le
pygobject3-devel-3.22.0-1.el7.ppc64le
systemtap-runtime-3.1-3.el7.ppc64le
nss-softokn-freebl-devel-3.28.3-6.el7.ppc64le
libgee-0.18.1-1.el7.ppc64le
perl-PlRPC-0.2020-14.el7.noarch
python34-libs-3.4.5-4.el7.ppc64le
json-c-0.11-4.el7_0.ppc64le
plymouth-plugin-two-step-0.8.9-0.28.20140113.el7.centos.ppc64le
gnome-font-viewer-3.22.0-1.el7.ppc64le
sssd-client-1.15.2-50.el7.ppc64le
libXext-1.3.3-3.el7.ppc64le
nspr-devel-4.13.1-1.0.el7_3.ppc64le
perl-Algorithm-Diff-1.1902-17.el7.noarch
tcp_wrappers-libs-7.6-77.el7.ppc64le
libgdata-devel-0.17.8-1.el7.ppc64le
gnome-screenshot-3.22.0-1.el7.ppc64le
mtdev-1.1.5-5.el7.ppc64le
mesa-libEGL-17.0.1-6.20170307.el7.ppc64le
libpng-devel-1.5.13-7.el7_2.ppc64le
perl-Digest-SHA1-2.13-9.el7.ppc64le
libdhash-0.4.3-27.el7.ppc64le
phonon-devel-4.6.0-10.el7.ppc64le
qt3-ODBC-3.3.8b-51.el7.ppc64le
systemd-219-42.el7.ppc64le
libXinerama-1.1.3-2.1.el7.ppc64le
gdb-7.6.1-100.el7.ppc64le
perl-File-Listing-6.04-7.el7.noarch
jasper-libs-1.900.1-31.el7.ppc64le
ibus-setup-1.5.3-13.el7.noarch
spice-vdagent-0.14.0-14.el7.ppc64le
PackageKit-glib-1.1.5-1.el7.centos.ppc64le
libXmu-1.1.2-2.el7.ppc64le
atkmm-2.24.2-1.el7.ppc64le
perl-Sys-Syslog-0.33-3.el7.ppc64le
libXdmcp-1.1.2-6.el7.ppc64le
kdelibs-devel-4.14.8-6.el7_3.ppc64le
targetcli-2.1.fb46-1.el7.noarch
libcgroup-0.41-13.el7.ppc64le
qt-x11-4.8.5-13.el7.ppc64le
libxcb-devel-1.12-1.el7.ppc64le
perl-HTML-Format-2.10-7.el7.noarch
libsss_idmap-1.15.2-50.el7.ppc64le
kactivities-4.10.5-3.el7.ppc64le
httpd-devel-2.4.6-67.el7.centos.ppc64le
abrt-2.1.11-48.el7.centos.ppc64le
java-1.7.0-openjdk-headless-1.7.0.141-2.6.10.5.el7.ppc64le
apr-devel-1.4.8-3.el7.ppc64le
cdparanoia-10.2-17.el7.ppc64le
libpcap-1.5.3-9.el7.ppc64le
libkworkspace-4.11.19-8.el7.ppc64le
dbus-glib-devel-0.100-7.el7.ppc64le
crontabs-1.11-6.20121102git.el7.noarch
libXi-devel-1.7.9-1.el7.ppc64le
gnome-menus-3.13.3-3.el7.ppc64le
libieee1284-devel-0.2.11-15.el7.ppc64le
kmod-libs-20-15.el7.ppc64le
kde-runtime-4.10.5-8.el7.ppc64le
mod_ssl-2.4.6-67.el7.centos.ppc64le
cyrus-sasl-2.1.26-21.el7.ppc64le
libXScrnSaver-1.2.2-6.1.el7.ppc64le
python-augeas-0.5.0-2.el7.noarch
LibRaw-0.14.8-5.el7.20120830git98d925.ppc64le
hyphen-2.8.6-5.el7.ppc64le
kdenetwork-krdc-libs-4.10.5-8.el7_0.ppc64le
opal-prd-5.5.0-1.el7.ppc64le
rdma-core-13-7.el7.ppc64le
pulseaudio-10.0-3.el7.ppc64le
python-sssdconfig-1.15.2-50.el7.noarch
libisofs-1.2.8-4.el7.ppc64le
libverto-0.2.5-4.el7.ppc64le
kdesdk-kmtrace-devel-4.10.5-6.el7.ppc64le
systemd-devel-219-42.el7.ppc64le
mesa-dri-drivers-17.0.1-6.20170307.el7.ppc64le
clutter-1.26.0-1.el7.ppc64le
fipscheck-1.4.1-6.el7.ppc64le
dwz-0.11-3.el7.ppc64le
boost-regex-1.53.0-27.el7.ppc64le
libXaw-1.0.13-4.el7.ppc64le
gcc-gfortran-4.8.5-16.el7.ppc64le
systemd-python-219-42.el7.ppc64le
zenity-3.22.0-1.el7.ppc64le
boost-atomic-1.53.0-27.el7.ppc64le
rpm-libs-4.11.3-25.el7.ppc64le
GeoIP-1.5.0-11.el7.ppc64le
libksane-devel-4.10.5-4.el7.ppc64le
rubygem-bundler-1.7.8-3.el7.noarch
git-1.8.3.1-11.el7.ppc64le
brasero-libs-3.12.1-2.el7.ppc64le
c-ares-1.10.0-3.el7.ppc64le
libnfsidmap-0.25-17.el7.ppc64le
cdparanoia-libs-10.2-17.el7.ppc64le
tk-8.5.13-6.el7.ppc64le
libhugetlbfs-devel-2.16-12.el7.ppc64le
NetworkManager-wifi-1.8.0-9.el7.ppc64le
libcanberra-gtk2-0.30-5.el7.ppc64le
hostname-3.13-3.el7.ppc64le
redland-1.0.16-6.el7.ppc64le
libdaemon-0.14-7.el7.ppc64le
brasero-3.12.1-2.el7.ppc64le
cups-devel-1.6.3-29.el7.ppc64le
qca2-2.0.3-7.el7.ppc64le
pangomm-2.40.1-1.el7.ppc64le
libnetfilter_conntrack-1.0.6-1.el7_3.ppc64le
sip-devel-4.14.6-4.el7.ppc64le
perl-parent-0.225-244.el7.noarch
libkkc-0.3.1-9.el7.ppc64le
crypto-utils-2.4.1-42.el7.ppc64le
lvm2-2.02.171-8.el7.ppc64le
poppler-glib-0.26.5-16.el7.ppc64le
crash-7.1.9-2.el7.ppc64le
libbluray-0.2.3-5.el7.ppc64le
perl-Filter-1.49-3.el7.ppc64le
control-center-3.22.2-5.el7.ppc64le
c-ares-devel-1.10.0-3.el7.ppc64le
sysstat-10.1.5-12.el7.ppc64le
mesa-libGL-devel-17.0.1-6.20170307.el7.ppc64le
python-pwquality-1.2.3-4.el7.ppc64le
liblouis-python-2.5.2-10.el7.noarch
perl-PathTools-3.40-5.el7.ppc64le
gnome-shell-extension-apps-menu-3.22.2-10.el7.noarch
hunspell-devel-1.3.2-15.el7.ppc64le
policycoreutils-python-2.5-17.1.el7.ppc64le
libwnck3-3.20.1-1.el7.ppc64le
gsettings-desktop-schemas-devel-3.22.0-1.el7.ppc64le
lsof-4.87-4.el7.ppc64le
perl-Getopt-Long-2.40-2.el7.noarch
nfs-utils-1.3.0-0.48.el7.ppc64le
mtr-0.85-7.el7.ppc64le
autofs-5.0.7-69.el7.ppc64le
cairo-devel-1.14.8-2.el7.ppc64le
xorg-x11-xbitmaps-1.1.1-6.el7.noarch
libreport-2.1.11-38.el7.centos.ppc64le
perl-XML-Parser-2.41-10.el7.ppc64le
libvirt-daemon-driver-storage-3.2.0-14.el7.ppc64le
python2-caribou-0.4.21-1.el7.noarch
fontpackages-filesystem-1.44-8.el7.noarch
perl-Test-Pod-1.48-3.el7.noarch
libuuid-devel-2.23.2-43.el7.ppc64le
perl-Package-Constants-0.02-292.el7.noarch
gnutls-3.3.26-9.el7.ppc64le
libreport-cli-2.1.11-38.el7.centos.ppc64le
gettext-common-devel-0.19.8.1-2.el7.noarch
cups-filters-1.0.35-22.el7.ppc64le
xkeyboard-config-2.20-1.el7.noarch
bison-3.0.4-1.el7.ppc64le
compat-libcolord1-1.0.4-1.el7.ppc64le
perl-Digest-MD5-2.52-3.el7.ppc64le
gnutls-dane-3.3.26-9.el7.ppc64le
libusbx-devel-1.0.20-1.el7.ppc64le
initial-setup-0.3.9.40-1.el7.centos.ppc64le
libchamplain-gtk-0.12.15-1.el7.ppc64le
libreport-filesystem-2.1.11-38.el7.centos.ppc64le
m17n-contrib-1.1.14-3.el7.noarch
newt-python-0.52.15-4.el7.ppc64le
perl-Locale-Maketext-1.23-3.el7.noarch
libvirt-daemon-driver-nodedev-3.2.0-14.el7.ppc64le
perl-ExtUtils-Install-1.58-292.el7.noarch
libvirt-3.2.0-14.el7.ppc64le
gnome-themes-standard-3.22.2-1.el7.ppc64le
gl-manpages-1.1-7.20130122.el7.noarch
lohit-gujarati-fonts-2.5.3-2.el7.noarch
python-backports-ssl_match_hostname-3.4.0.2-4.el7.noarch
perl-local-lib-1.008010-4.el7.noarch
rest-0.8.0-1.el7.ppc64le
perl-Module-Build-0.40.05-2.el7.noarch
ibus-kkc-1.5.18-7.el7.ppc64le
webkitgtk4-plugin-process-gtk2-2.14.7-2.el7.ppc64le
basesystem-10.0-7.el7.centos.noarch
madan-fonts-2.000-11.el7.noarch
python-beaker-1.5.4-10.el7.noarch
boost-locale-1.53.0-27.el7.ppc64le
dleyna-core-0.5.0-1.el7.ppc64le
liberation-sans-fonts-1.07.2-15.el7.noarch
tk-devel-8.5.13-6.el7.ppc64le
gnome-packagekit-updater-3.22.1-2.el7.ppc64le
cim-schema-2.33.0-6.el7.noarch
lohit-assamese-fonts-2.5.3-2.el7.noarch
tagsoup-1.2.1-8.el7.noarch
libshout-2.2.2-11.el7.ppc64le
ntpdate-4.2.6p5-25.el7.centos.2.ppc64le
libproxy-0.4.11-10.el7.ppc64le
gvfs-gphoto2-1.30.4-3.el7.ppc64le
gspell-1.2.3-1.el7.ppc64le
libstdc++-4.8.5-16.el7.ppc64le
sil-nuosu-fonts-2.1.1-5.el7.noarch
python-ntplib-0.3.2-1.el7.noarch
bc-1.06.95-13.el7.ppc64le
libvirt-daemon-driver-lxc-3.2.0-14.el7.ppc64le
libreport-anaconda-2.1.11-38.el7.centos.ppc64le
kdepimlibs-devel-4.10.5-4.el7.ppc64le
unique3-3.0.2-8.el7.ppc64le
freetype-2.4.11-15.el7.ppc64le
lohit-marathi-fonts-2.5.3-2.el7.noarch
python2-cryptography-1.7.2-1.el7.ppc64le
libss-1.42.9-10.el7.ppc64le
kernel-tools-libs-3.10.0-693.el7.ppc64le
libsysfs-2.1.0-16.el7.ppc64le
ibus-hangul-1.4.2-10.el7.ppc64le
freerdp-1.0.2-10.el7.ppc64le
popt-1.13-16.el7.ppc64le
open-sans-fonts-1.10-1.el7.noarch
bind-libs-lite-9.9.4-50.el7.ppc64le
lksctp-tools-1.0.17-2.el7.ppc64le
sssd-common-pac-1.15.2-50.el7.ppc64le
libtiff-4.0.3-27.el7_3.ppc64le
gnome-desktop3-devel-3.22.2-2.el7.ppc64le
cdrdao-1.2.3-20.el7.ppc64le
expat-2.1.0-10.el7_3.ppc64le
latrace-0.5.11-6.1.el7.ppc64le
perl-Net-SSLeay-1.55-6.el7.ppc64le
cups-libs-1.6.3-29.el7.ppc64le
dmraid-events-1.0.0.rc16-28.el7.ppc64le
rubygem-io-console-0.4.2-30.el7.ppc64le
gutenprint-cups-5.2.9-18.el7.ppc64le
xorg-x11-server-Xorg-1.19.3-11.el7.ppc64le
libtalloc-2.1.9-1.el7.ppc64le
iwl6000g2b-firmware-17.168.5.2-56.el7.noarch
nss-sysinit-3.28.4-8.el7.ppc64le
glib2-2.50.3-3.el7.ppc64le
rpm-python-4.11.3-25.el7.ppc64le
ustr-1.0.4-16.el7.ppc64le
gucharmap-3.18.2-1.el7.ppc64le
xorg-x11-drv-dummy-0.3.7-1.el7.ppc64le
libogg-1.3.0-7.el7.ppc64le
iwl6000-firmware-9.221.4.1-56.el7.noarch
docbook-dtds-1.0-60.el7.noarch
xorg-x11-proto-devel-7.7-20.el7.noarch
pygpgme-0.3-9.el7.ppc64le
openssh-7.4p1-11.el7.ppc64le
cheese-3.22.1-1.el7.ppc64le
jline-1.0-8.el7.noarch
libcap-2.22-9.el7.ppc64le
ivtv-firmware-20080701-26.el7.noarch
perl-Pod-LaTeX-0.61-2.el7.noarch
enchant-1.6.0-8.el7.ppc64le
python2-ipalib-4.5.0-20.el7.centos.noarch
tog-pegasus-libs-2.14.1-5.el7.ppc64le
firstboot-19.12-1.el7.ppc64le
gupnp-dlna-0.10.5-1.el7.ppc64le
which-2.20-7.el7.ppc64le
epel-release-7-9.noarch
perl-Net-Daemon-0.48-5.el7.noarch
libcroco-0.6.11-1.el7.ppc64le
liboauth-devel-0.9.7-4.el7.ppc64le
libhangul-0.1.0-8.el7.ppc64le
eog-3.20.5-2.el7.ppc64le
plymouth-theme-charge-0.8.9-0.28.20140113.el7.centos.ppc64le
libcollection-0.6.2-27.el7.ppc64le
perl-Locale-Codes-3.26-2.el7.noarch
pygobject2-2.28.6-11.el7.ppc64le
libXdamage-1.1.4-4.1.el7.ppc64le
libestr-0.1.9-2.el7.ppc64le
PackageKit-gtk3-module-1.1.5-1.el7.centos.ppc64le
libgweather-devel-3.20.4-1.el7.ppc64le
xz-5.2.2-1.el7.ppc64le
perl-WWW-RobotRules-6.02-5.el7.noarch
libICE-devel-1.0.9-9.el7.ppc64le
libXft-2.3.2-2.el7.ppc64le
cryptsetup-libs-1.7.4-3.el7.ppc64le
alsa-plugins-pulseaudio-1.1.1-1.el7.ppc64le
glx-utils-8.2.0-3.el7.ppc64le
speex-1.2-0.19.rc1.el7.ppc64le
perl-HTTP-Negotiate-6.01-5.el7.noarch
libtirpc-0.2.4-0.10.el7.ppc64le
pulseaudio-libs-glib2-10.0-3.el7.ppc64le
mesa-libgbm-17.0.1-6.20170307.el7.ppc64le
pulseaudio-libs-devel-10.0-3.el7.ppc64le
imsettings-1.6.3-9.el7.ppc64le
hunspell-en-US-0.20121024-6.el7.noarch
perl-IO-Socket-IP-0.21-4.el7.noarch
nss-util-devel-3.28.4-3.el7.ppc64le
libXxf86vm-1.1.4-1.el7.ppc64le
hwdata-0.252-8.6.el7.ppc64le
kernel-tools-3.10.0-693.el7.ppc64le
nepomuk-core-libs-4.10.5-5.el7.ppc64le
exiv2-libs-0.23-6.el7.ppc64le
perl-libwww-perl-6.05-2.el7.noarch
p11-kit-devel-0.23.5-3.el7.ppc64le
librsvg2-2.40.16-1.el7.ppc64le
libsmbclient-4.6.2-8.el7.ppc64le
abrt-console-notification-2.1.11-48.el7.centos.ppc64le
kdesdk-okteta-libs-4.10.5-6.el7.ppc64le
boost-chrono-1.53.0-27.el7.ppc64le
iw-4.3-1.el7.ppc64le
libcom_err-devel-1.42.9-10.el7.ppc64le
akonadi-1.9.2-4.el7.ppc64le
accountsservice-libs-0.6.45-2.el7.ppc64le
wvdial-1.61-9.el7.ppc64le
libkexiv2-devel-4.10.5-3.el7.ppc64le
libmpc-1.0.1-3.el7.ppc64le
lm_sensors-devel-3.4.0-4.20160601gitf9185e5.el7.ppc64le
meanwhile-1.1.0-12.el7.ppc64le
libXt-devel-1.1.5-3.el7.ppc64le
plymouth-scripts-0.8.9-0.28.20140113.el7.centos.ppc64le
mod_fcgid-2.3.9-4.el7.ppc64le
kdepim-runtime-libs-4.10.5-3.el7.ppc64le
mesa-libglapi-17.0.1-6.20170307.el7.ppc64le
hunspell-en-GB-0.20121024-6.el7.noarch
sip-4.14.6-4.el7.ppc64le
cairomm-1.12.0-1.el7.ppc64le
abrt-addon-xorg-2.1.11-48.el7.centos.ppc64le
ModemManager-1.6.0-2.el7.ppc64le
kdenetwork-krdc-devel-4.10.5-8.el7_0.ppc64le
libieee1284-0.2.11-15.el7.ppc64le
highlight-3.13-3.el7.ppc64le
pyOpenSSL-0.13.1-3.el7.ppc64le
gtk-update-icon-cache-3.22.10-4.el7.ppc64le
NetworkManager-1.8.0-9.el7.ppc64le
crda-3.13_2016.02.08-1.el7.ppc64le
kdesdk-kompare-libs-4.10.5-6.el7.ppc64le
newt-0.52.15-4.el7.ppc64le
xcb-util-0.4.0-2.el7.ppc64le
automake-1.13.4-3.el7.noarch
libgweather-3.20.4-1.el7.ppc64le
lockdev-1.0.4-0.13.20111007git.el7.ppc64le
man-db-2.6.3-9.el7.ppc64le
gd-2.0.35-26.el7.ppc64le
exempi-2.2.0-8.el7.ppc64le
curl-7.29.0-42.el7.ppc64le
snappy-1.1.0-3.el7.ppc64le
libreport-gtk-2.1.11-38.el7.centos.ppc64le
unbound-libs-1.4.20-34.el7.ppc64le
tcpdump-4.9.0-5.el7.ppc64le
sane-backends-drivers-scanners-1.0.24-9.el7.ppc64le
libedit-3.0-12.20121213cvs.el7.ppc64le
liboauth-0.9.7-4.el7.ppc64le
libmpcdec-1.2.6-12.el7.ppc64le
libnm-gtk-1.8.0-3.el7.ppc64le
grub2-tools-extra-2.02-0.64.el7.centos.ppc64le
libitm-devel-4.8.5-16.el7.ppc64le
libdmx-1.1.3-3.el7.ppc64le
wavpack-4.60.1-9.el7.ppc64le
rasqal-0.9.30-4.el7.ppc64le
autogen-libopts-5.18-5.el7.ppc64le
gnome-bluetooth-libs-3.20.1-1.el7.ppc64le
qt-settings-19-23.5.el7.centos.noarch
libxslt-devel-1.1.28-5.el7.ppc64le
grilo-plugins-0.3.4-1.el7.ppc64le
SDL-1.2.15-14.el7.ppc64le
sip-macros-4.14.6-4.el7.ppc64le
iptables-1.4.21-18.0.1.el7.centos.ppc64le
gstreamer-plugins-good-0.10.31-13.el7.ppc64le
qjson-0.8.1-4.el7.ppc64le
perl-Test-Pod-Coverage-1.08-21.el7.noarch
pcp-conf-3.11.8-7.el7.ppc64le
perl-podlators-2.5.1-3.el7.noarch
libcurl-devel-7.29.0-42.el7.ppc64le
graphite2-devel-1.3.6-1.el7_2.ppc64le
pygtk2-2.24.0-9.el7.ppc64le
kexec-tools-2.0.14-17.el7.ppc64le
iptables-devel-1.4.21-18.0.1.el7.centos.ppc64le
gnome-shell-3.22.3-17.el7.ppc64le
perl-Carp-1.26-244.el7.noarch
liblouis-2.5.2-10.el7.ppc64le
dvd+rw-tools-7.1-15.el7.ppc64le
ptlib-2.10.10-6.el7.ppc64le
samba-common-libs-4.6.2-8.el7.ppc64le
gvfs-devel-1.30.4-3.el7.ppc64le
gnome-shell-extension-launch-new-instance-3.22.2-10.el7.noarch
perl-libs-5.16.3-292.el7.ppc64le
libselinux-utils-2.5-11.el7.ppc64le
libsepol-devel-2.5-6.el7.ppc64le
festival-lib-1.96-28.el7.ppc64le
oddjob-0.31.5-4.el7.ppc64le
latencytop-tui-0.5-13.el7.ppc64le
libvirt-daemon-driver-storage-core-3.2.0-14.el7.ppc64le
perl-Data-Dumper-2.145-3.el7.ppc64le
libreport-python-2.1.11-38.el7.centos.ppc64le
libical-devel-1.0.1-1.el7.ppc64le
libmx-1.4.7-10.el7.ppc64le
cups-pk-helper-0.2.6-2.el7.ppc64le
=== TEST BEGIN ===
Install prefix /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install
BIOS directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/share/qemu
firmware path /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/share/qemu-firmware
binary directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/bin
library directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/lib
module directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/lib/qemu
libexec directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/libexec
include directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/include
config directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/etc
local state directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/var
Manual directory /var/tmp/patchew-tester-tmp-lmn4s2rx/src/install/share/man
ELF interp prefix /usr/gnemul/qemu-%M
Source path /var/tmp/patchew-tester-tmp-lmn4s2rx/src
GIT binary git
GIT submodules ui/keycodemapdb dtc capstone
C compiler cc
Host C compiler cc
C++ compiler c++
Objective-C compiler cc
ARFLAGS rv
CFLAGS -O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 -g
QEMU_CFLAGS -I/usr/include/pixman-1 -I$(SRC_PATH)/dtc/libfdt -Werror -pthread -I/usr/include/glib-2.0 -I/usr/lib64/glib-2.0/include -DNCURSES_WIDECHAR -m64 -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -Wendif-labels -Wno-missing-include-dirs -Wempty-body -Wnested-externs -Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers -Wold-style-declaration -Wold-style-definition -Wtype-limits -fstack-protector-strong -Wno-missing-braces -I/usr/include/p11-kit-1 -I/usr/include/libpng15 -I$(SRC_PATH)/capstone/include
LDFLAGS -Wl,--warn-common -m64 -g
make make
install install
python python -B
smbd /usr/sbin/smbd
module support no
host CPU ppc64
host big endian no
target list aarch64-softmmu alpha-softmmu arm-softmmu cris-softmmu i386-softmmu lm32-softmmu m68k-softmmu microblazeel-softmmu microblaze-softmmu mips64el-softmmu mips64-softmmu mipsel-softmmu mips-softmmu moxie-softmmu nios2-softmmu or1k-softmmu ppc64-softmmu ppcemb-softmmu ppc-softmmu s390x-softmmu sh4eb-softmmu sh4-softmmu sparc64-softmmu sparc-softmmu tricore-softmmu unicore32-softmmu x86_64-softmmu xtensaeb-softmmu xtensa-softmmu aarch64-linux-user alpha-linux-user armeb-linux-user arm-linux-user cris-linux-user hppa-linux-user i386-linux-user m68k-linux-user microblazeel-linux-user microblaze-linux-user mips64el-linux-user mips64-linux-user mipsel-linux-user mips-linux-user mipsn32el-linux-user mipsn32-linux-user nios2-linux-user or1k-linux-user ppc64abi32-linux-user ppc64le-linux-user ppc64-linux-user ppc-linux-user s390x-linux-user sh4eb-linux-user sh4-linux-user sparc32plus-linux-user sparc64-linux-user sparc-linux-user tilegx-linux-user x86_64-linux-user
gprof enabled no
sparse enabled no
strip binaries yes
profiler no
static build no
SDL support yes (1.2.15)
GTK support yes (3.22.10)
GTK GL support no
VTE support no
TLS priority NORMAL
GNUTLS support yes
GNUTLS rnd yes
libgcrypt no
libgcrypt kdf no
nettle yes (2.7.1)
nettle kdf yes
libtasn1 yes
curses support yes
virgl support no
curl support yes
mingw32 support no
Audio drivers oss
Block whitelist (rw)
Block whitelist (ro)
VirtFS support yes
Multipath support no
VNC support yes
VNC SASL support yes
VNC JPEG support yes
VNC PNG support yes
xen support no
brlapi support no
bluez support no
Documentation no
PIE no
vde support no
netmap support no
Linux AIO support yes
ATTR/XATTR support yes
Install blobs yes
KVM support yes
HAX support no
TCG support yes
TCG debug enabled no
TCG interpreter no
RDMA support yes
fdt support yes
preadv support yes
fdatasync yes
madvise yes
posix_madvise yes
libcap-ng support yes
vhost-net support yes
vhost-scsi support yes
vhost-vsock support yes
vhost-user support yes
Trace backends log
spice support no
rbd support no
xfsctl support no
smartcard support no
libusb yes
usb net redir no
OpenGL support no
OpenGL dmabufs no
libiscsi support no
libnfs support no
build guest agent yes
QGA VSS support no
QGA w32 disk info no
QGA MSI support no
seccomp support no
coroutine backend ucontext
coroutine pool yes
debug stack usage no
crypto afalg no
GlusterFS support no
gcov gcov
gcov enabled no
TPM support yes
libssh2 support no
TPM passthrough no
TPM emulator yes
QOM debugging yes
Live block migration yes
lzo support no
snappy support no
bzip2 support yes
NUMA host support yes
tcmalloc support no
jemalloc support no
avx2 optimization no
replication support yes
VxHS block device no
capstone git
GEN aarch64-softmmu/config-devices.mak.tmp
GEN alpha-softmmu/config-devices.mak.tmp
GEN arm-softmmu/config-devices.mak.tmp
GEN cris-softmmu/config-devices.mak.tmp
GEN i386-softmmu/config-devices.mak.tmp
GEN lm32-softmmu/config-devices.mak.tmp
GEN m68k-softmmu/config-devices.mak.tmp
GEN cris-softmmu/config-devices.mak
GEN microblazeel-softmmu/config-devices.mak.tmp
GEN alpha-softmmu/config-devices.mak
GEN lm32-softmmu/config-devices.mak
GEN aarch64-softmmu/config-devices.mak
GEN microblaze-softmmu/config-devices.mak.tmp
GEN m68k-softmmu/config-devices.mak
GEN arm-softmmu/config-devices.mak
GEN i386-softmmu/config-devices.mak
GEN mips64el-softmmu/config-devices.mak.tmp
GEN mips64-softmmu/config-devices.mak.tmp
GEN mipsel-softmmu/config-devices.mak.tmp
GEN mips-softmmu/config-devices.mak.tmp
GEN moxie-softmmu/config-devices.mak.tmp
GEN nios2-softmmu/config-devices.mak.tmp
GEN microblazeel-softmmu/config-devices.mak
GEN or1k-softmmu/config-devices.mak.tmp
GEN microblaze-softmmu/config-devices.mak
GEN ppc64-softmmu/config-devices.mak.tmp
GEN ppc-softmmu/config-devices.mak.tmp
GEN ppcemb-softmmu/config-devices.mak.tmp
GEN s390x-softmmu/config-devices.mak.tmp
GEN sparc64-softmmu/config-devices.mak.tmp
GEN unicore32-softmmu/config-devices.mak.tmp
GEN nios2-softmmu/config-devices.mak
GEN sparc-softmmu/config-devices.mak.tmp
GEN sh4-softmmu/config-devices.mak.tmp
GEN tricore-softmmu/config-devices.mak.tmp
GEN x86_64-softmmu/config-devices.mak.tmp
GEN sh4eb-softmmu/config-devices.mak.tmp
GEN aarch64-linux-user/config-devices.mak.tmp
GEN alpha-linux-user/config-devices.mak.tmp
GEN xtensa-softmmu/config-devices.mak.tmp
GEN mips64-softmmu/config-devices.mak
GEN arm-linux-user/config-devices.mak.tmp
GEN armeb-linux-user/config-devices.mak.tmp
GEN xtensaeb-softmmu/config-devices.mak.tmp
GEN microblaze-linux-user/config-devices.mak.tmp
GEN moxie-softmmu/config-devices.mak
GEN hppa-linux-user/config-devices.mak.tmp
GEN mips64el-linux-user/config-devices.mak.tmp
GEN tricore-softmmu/config-devices.mak
GEN cris-linux-user/config-devices.mak.tmp
GEN xtensa-softmmu/config-devices.mak
GEN mipsel-softmmu/config-devices.mak
GEN mips-softmmu/config-devices.mak
GEN m68k-linux-user/config-devices.mak.tmp
GEN mips-linux-user/config-devices.mak.tmp
GEN mipsel-linux-user/config-devices.mak.tmp
GEN microblazeel-linux-user/config-devices.mak.tmp
GEN mips64-linux-user/config-devices.mak.tmp
GEN ppc-softmmu/config-devices.mak
GEN i386-linux-user/config-devices.mak.tmp
GEN sparc-softmmu/config-devices.mak
GEN arm-linux-user/config-devices.mak
GEN mipsn32el-linux-user/config-devices.mak.tmp
GEN mipsn32-linux-user/config-devices.mak.tmp
GEN mips64el-softmmu/config-devices.mak
GEN aarch64-linux-user/config-devices.mak
GEN nios2-linux-user/config-devices.mak.tmp
GEN or1k-linux-user/config-devices.mak.tmp
GEN sh4eb-linux-user/config-devices.mak.tmp
GEN ppc64-linux-user/config-devices.mak.tmp
GEN ppc64le-linux-user/config-devices.mak.tmp
GEN s390x-linux-user/config-devices.mak.tmp
GEN ppc-linux-user/config-devices.mak.tmp
GEN sparc32plus-linux-user/config-devices.mak.tmp
GEN sparc64-linux-user/config-devices.mak.tmp
GEN sh4-linux-user/config-devices.mak.tmp
GEN ppc64abi32-linux-user/config-devices.mak.tmp
GEN s390x-softmmu/config-devices.mak
GIT ui/keycodemapdb dtc capstone
GEN x86_64-linux-user/config-devices.mak.tmp
GEN config-host.h
GEN tilegx-linux-user/config-devices.mak.tmp
GEN cris-linux-user/config-devices.mak
GEN qemu-options.def
GEN ppcemb-softmmu/config-devices.mak
GEN microblaze-linux-user/config-devices.mak
GEN sparc64-softmmu/config-devices.mak
GEN x86_64-softmmu/config-devices.mak
GEN qmp-commands.h
GEN qapi-visit.h
GEN qapi-types.h
GEN mipsn32el-linux-user/config-devices.mak
GEN qapi-types.c
GEN armeb-linux-user/config-devices.mak
GEN qapi-visit.c
GEN qapi-event.c
GEN qmp-introspect.c
GEN alpha-linux-user/config-devices.mak
GEN sh4eb-linux-user/config-devices.mak
GEN qmp-marshal.c
GEN qmp-introspect.h
GEN trace/generated-tcg-tracers.h
GEN trace/generated-helpers.h
GEN trace/generated-helpers.c
GEN module_block.h
GEN qapi-event.h
GEN sparc-linux-user/config-devices.mak.tmp
GEN trace/generated-helpers-wrappers.h
GEN sh4-softmmu/config-devices.mak
GEN unicore32-softmmu/config-devices.mak
GEN xtensaeb-softmmu/config-devices.mak
GEN m68k-linux-user/config-devices.mak
GEN mips64el-linux-user/config-devices.mak
GEN mipsel-linux-user/config-devices.mak
GEN x86_64-linux-user/config-devices.mak
GEN tests/test-qapi-types.h
GEN hppa-linux-user/config-devices.mak
GEN ppc64abi32-linux-user/config-devices.mak
GEN mips-linux-user/config-devices.mak
GEN ppc64le-linux-user/config-devices.mak
GEN ppc64-linux-user/config-devices.mak
GEN tests/test-qmp-commands.h
GEN tests/test-qapi-visit.h
GEN microblazeel-linux-user/config-devices.mak
GEN sparc32plus-linux-user/config-devices.mak
GEN tests/test-qapi-event.h
GEN tests/test-qmp-introspect.h
GEN or1k-linux-user/config-devices.mak
GEN or1k-softmmu/config-devices.mak
GEN sh4eb-softmmu/config-devices.mak
GEN i386-linux-user/config-devices.mak
GEN mipsn32-linux-user/config-devices.mak
GEN ppc64-softmmu/config-devices.mak
GEN mips64-linux-user/config-devices.mak
GEN nios2-linux-user/config-devices.mak
GEN ppc-linux-user/config-devices.mak
GEN s390x-linux-user/config-devices.mak
GEN sh4-linux-user/config-devices.mak
GEN sparc64-linux-user/config-devices.mak
GEN tilegx-linux-user/config-devices.mak
GEN util/trace.h
GEN sparc-linux-user/config-devices.mak
GEN trace-root.h
GEN crypto/trace.h
GEN io/trace.h
GEN migration/trace.h
GEN block/trace.h
GEN chardev/trace.h
GEN hw/block/trace.h
GEN hw/block/dataplane/trace.h
GEN hw/char/trace.h
GEN hw/intc/trace.h
GEN hw/net/trace.h
GEN hw/virtio/trace.h
GEN hw/audio/trace.h
GEN hw/misc/trace.h
GEN hw/usb/trace.h
GEN hw/scsi/trace.h
GEN hw/nvram/trace.h
GEN hw/display/trace.h
GEN hw/input/trace.h
GEN hw/timer/trace.h
GEN hw/dma/trace.h
GEN hw/sparc/trace.h
GEN hw/sd/trace.h
GEN hw/isa/trace.h
GEN hw/mem/trace.h
GEN hw/i386/trace.h
GEN hw/i386/xen/trace.h
GEN hw/9pfs/trace.h
GEN hw/ppc/trace.h
GEN hw/pci/trace.h
GEN hw/s390x/trace.h
GEN hw/vfio/trace.h
GEN hw/acpi/trace.h
GEN hw/arm/trace.h
GEN hw/alpha/trace.h
GEN hw/xen/trace.h
GEN hw/ide/trace.h
GEN ui/trace.h
GEN audio/trace.h
GEN net/trace.h
GEN target/arm/trace.h
GEN target/i386/trace.h
GEN target/mips/trace.h
GEN target/sparc/trace.h
GEN target/s390x/trace.h
GEN target/ppc/trace.h
GEN qom/trace.h
GEN linux-user/trace.h
GEN qapi/trace.h
GEN accel/tcg/trace.h
GEN accel/kvm/trace.h
GEN nbd/trace.h
GEN scsi/trace.h
GEN trace-root.c
GEN util/trace.c
GEN crypto/trace.c
GEN io/trace.c
GEN migration/trace.c
GEN block/trace.c
GEN chardev/trace.c
GEN hw/block/trace.c
GEN hw/block/dataplane/trace.c
GEN hw/char/trace.c
GEN hw/intc/trace.c
GEN hw/net/trace.c
GEN hw/virtio/trace.c
GEN hw/audio/trace.c
GEN hw/misc/trace.c
GEN hw/usb/trace.c
GEN hw/scsi/trace.c
GEN hw/nvram/trace.c
GEN hw/display/trace.c
GEN hw/input/trace.c
GEN hw/timer/trace.c
GEN hw/dma/trace.c
GEN hw/sparc/trace.c
GEN hw/sd/trace.c
GEN hw/isa/trace.c
GEN hw/mem/trace.c
GEN hw/i386/trace.c
GEN hw/i386/xen/trace.c
GEN hw/9pfs/trace.c
GEN hw/ppc/trace.c
GEN hw/pci/trace.c
GEN hw/s390x/trace.c
GEN hw/vfio/trace.c
GEN hw/acpi/trace.c
GEN hw/arm/trace.c
GEN hw/alpha/trace.c
GEN hw/xen/trace.c
GEN hw/ide/trace.c
GEN ui/trace.c
GEN audio/trace.c
GEN net/trace.c
GEN target/arm/trace.c
GEN target/i386/trace.c
GEN target/mips/trace.c
GEN target/sparc/trace.c
GEN target/s390x/trace.c
GEN target/ppc/trace.c
GEN qom/trace.c
GEN linux-user/trace.c
GEN qapi/trace.c
GEN accel/tcg/trace.c
GEN accel/kvm/trace.c
GEN nbd/trace.c
GEN scsi/trace.c
GEN config-all-devices.mak
mkdir -p dtc/libfdt
mkdir -p dtc/tests
GEN ui/input-keymap-linux-to-qcode.c
GEN ui/input-keymap-qcode-to-qnum.c
GEN ui/input-keymap-qnum-to-qcode.c
CC cs.o
CC utils.o
CC SStream.o
CC MCInstrDesc.o
CC MCRegisterInfo.o
CC arch/ARM/ARMDisassembler.o
CC arch/ARM/ARMInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/dumptrees.c
CC arch/ARM/ARMMapping.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/trees.S
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/testutils.c
CC arch/ARM/ARMModule.o
CC arch/AArch64/AArch64BaseInfo.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/value-labels.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/truncated_property.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/check_path.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/subnode_iterate.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/overlay.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/asm_tree_dump.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/property_iterate.c
CC arch/AArch64/AArch64Disassembler.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/overlay_bad_fixup.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/integer-expressions.c
CC arch/AArch64/AArch64InstPrinter.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/utilfdt_test.c
CC arch/AArch64/AArch64Mapping.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/dtbs_equal_unordered.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/path_offset_aliases.c
CC arch/AArch64/AArch64Module.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/incbin.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/extra-terminating-null.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/dtb_reverse.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/add_subnode_with_nops.c
CC arch/Mips/MipsDisassembler.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/phandle_format.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/references.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/dtbs_equal_ordered.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/path-references.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/boot-cpuid.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/string_escapes.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/propname_escapes.c
CC arch/Mips/MipsInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/del_node.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/del_property.c
CC arch/Mips/MipsMapping.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/appendprop2.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/rw_tree1.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/setprop.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/appendprop1.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/set_name.c
CC arch/Mips/MipsModule.o
CC arch/PowerPC/PPCInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/open_pack.c
CC arch/PowerPC/PPCDisassembler.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/mangle-layout.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/nopulate.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/move_and_save.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/sw_tree1.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/nop_node.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/setprop_inplace.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/nop_property.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/addr_size_cells.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/notfound.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/stringlist.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/sized_cells.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/get_alias.c
CC arch/PowerPC/PPCMapping.o
CC arch/PowerPC/PPCModule.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/node_offset_by_compatible.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/node_check_compatible.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/node_offset_by_phandle.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/node_offset_by_prop_value.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/char_literal.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/parent_offset.c
CC arch/Sparc/SparcDisassembler.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/supernode_atdepth_offset.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/get_path.c
CC arch/Sparc/SparcInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/get_phandle.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/getprop.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/get_name.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/path_offset.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/find_property.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/subnode_offset.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/get_mem_rsv.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_overlay.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/tests/root_node.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_addresses.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_empty_tree.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_rw.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_sw.c
CC arch/Sparc/SparcMapping.o
CC arch/Sparc/SparcModule.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_strerror.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_wip.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt_ro.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/util.c
CC arch/SystemZ/SystemZDisassembler.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/libfdt/fdt.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/fdtput.c
CC arch/SystemZ/SystemZInstPrinter.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/fdtget.c
LEX convert-dtsv0-lexer.lex.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/fdtdump.c
CC arch/SystemZ/SystemZMapping.o
CC arch/SystemZ/SystemZModule.o
BISON dtc-parser.tab.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/livetree.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/fstree.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/flattree.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/dtc.c
CC arch/SystemZ/SystemZMCTargetDesc.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/srcpos.c
CC arch/X86/X86DisassemblerDecoder.o
CC arch/X86/X86Disassembler.o
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/treesource.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/data.c
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/checks.c
LEX dtc-lexer.lex.c
CC arch/X86/X86IntelInstPrinter.o
CC arch/X86/X86Module.o
CC arch/X86/X86Mapping.o
CC arch/X86/X86ATTInstPrinter.o
CC arch/XCore/XCoreDisassembler.o
CC arch/XCore/XCoreMapping.o
CC arch/XCore/XCoreInstPrinter.o
CC arch/XCore/XCoreModule.o
CC MCInst.o
DEP convert-dtsv0-lexer.lex.c
DEP dtc-parser.tab.c
DEP dtc-lexer.lex.c
CHK version_gen.h
UPD version_gen.h
DEP /var/tmp/patchew-tester-tmp-lmn4s2rx/src/dtc/util.c
CC libfdt/fdt.o
CC libfdt/fdt_ro.o
CC libfdt/fdt_wip.o
CC libfdt/fdt_sw.o
CC libfdt/fdt_rw.o
CC libfdt/fdt_strerror.o
CC libfdt/fdt_empty_tree.o
CC libfdt/fdt_addresses.o
CC libfdt/fdt_overlay.o
AR libfdt/libfdt.a
ar: creating libfdt/libfdt.a
a - libfdt/fdt.o
a - libfdt/fdt_ro.o
a - libfdt/fdt_wip.o
a - libfdt/fdt_sw.o
a - libfdt/fdt_rw.o
a - libfdt/fdt_strerror.o
a - libfdt/fdt_empty_tree.o
a - libfdt/fdt_addresses.o
a - libfdt/fdt_overlay.o
AR libcapstone.a
ar: creating /var/tmp/patchew-tester-tmp-lmn4s2rx/src/build/capstone/libcapstone.a
mkdir -p dtc/libfdt
mkdir -p dtc/tests
make[1]: `/var/tmp/patchew-tester-tmp-lmn4s2rx/src/build/capstone/libcapstone.a' is up to date.
GEN qga/qapi-generated/qga-qapi-types.h
CC tests/qemu-iotests/socket_scm_helper.o
GEN qga/qapi-generated/qga-qapi-visit.h
GEN qga/qapi-generated/qga-qmp-commands.h
GEN qga/qapi-generated/qga-qapi-types.c
GEN qga/qapi-generated/qga-qapi-visit.c
GEN qga/qapi-generated/qga-qmp-marshal.c
CC qmp-introspect.o
CC qapi-types.o
CC qapi-visit.o
CC qapi-event.o
CC qapi/qapi-visit-core.o
CC qapi/qapi-dealloc-visitor.o
CC qapi/qobject-input-visitor.o
CC qapi/qobject-output-visitor.o
CC qapi/qmp-registry.o
CC qapi/qmp-dispatch.o
CC qapi/string-input-visitor.o
CC qapi/string-output-visitor.o
CC qapi/opts-visitor.o
CC qapi/qapi-clone-visitor.o
CC qapi/qmp-event.o
CC qapi/qapi-util.o
CC qobject/qnum.o
CC qobject/qdict.o
CC qobject/qstring.o
CC qobject/qlist.o
CC qobject/qbool.o
CC qobject/qnull.o
CC qobject/qjson.o
CC qobject/qlit.o
CC qobject/qobject.o
CC qobject/json-lexer.o
CC qobject/json-streamer.o
CC trace/control.o
CC trace/qmp.o
CC util/osdep.o
CC qobject/json-parser.o
CC util/cutils.o
CC util/qemu-timer-common.o
CC util/bufferiszero.o
CC util/lockcnt.o
CC util/async.o
CC util/thread-pool.o
CC util/unicode.o
CC util/aiocb.o
CC util/qemu-timer.o
CC util/main-loop.o
CC util/iohandler.o
CC util/compatfd.o
CC util/mmap-alloc.o
CC util/aio-posix.o
CC util/oslib-posix.o
CC util/qemu-openpty.o
CC util/memfd.o
CC util/path.o
CC util/host-utils.o
CC util/qemu-thread-posix.o
CC util/event_notifier-posix.o
CC util/bitops.o
CC util/bitmap.o
CC util/hbitmap.o
CC util/module.o
CC util/fifo8.o
CC util/envlist.o
CC util/cacheinfo.o
CC util/acl.o
CC util/id.o
CC util/error.o
CC util/qemu-error.o
CC util/iov.o
CC util/qemu-config.o
CC util/qemu-sockets.o
CC util/uri.o
CC util/notify.o
CC util/qemu-option.o
CC util/qemu-progress.o
CC util/keyval.o
CC util/hexdump.o
CC util/crc32c.o
CC util/throttle.o
CC util/uuid.o
CC util/readline.o
CC util/rcu.o
CC util/getauxval.o
CC util/qemu-coroutine-lock.o
CC util/qemu-coroutine.o
CC util/qemu-coroutine-io.o
CC util/qemu-coroutine-sleep.o
CC util/coroutine-ucontext.o
CC util/buffer.o
CC util/timed-average.o
CC util/base64.o
CC util/log.o
CC util/pagesize.o
CC util/qdist.o
CC util/qht.o
CC util/range.o
CC util/stats64.o
CC util/systemd.o
CC trace-root.o
CC util/trace.o
CC crypto/trace.o
CC io/trace.o
CC migration/trace.o
CC block/trace.o
CC chardev/trace.o
CC hw/block/trace.o
CC hw/block/dataplane/trace.o
CC hw/char/trace.o
CC hw/intc/trace.o
CC hw/net/trace.o
CC hw/virtio/trace.o
CC hw/audio/trace.o
CC hw/usb/trace.o
CC hw/misc/trace.o
CC hw/scsi/trace.o
CC hw/nvram/trace.o
CC hw/display/trace.o
CC hw/input/trace.o
CC hw/timer/trace.o
CC hw/dma/trace.o
CC hw/sparc/trace.o
CC hw/sd/trace.o
CC hw/isa/trace.o
CC hw/mem/trace.o
CC hw/i386/trace.o
CC hw/i386/xen/trace.o
CC hw/9pfs/trace.o
CC hw/ppc/trace.o
CC hw/pci/trace.o
CC hw/s390x/trace.o
CC hw/vfio/trace.o
CC hw/acpi/trace.o
CC hw/alpha/trace.o
CC hw/arm/trace.o
CC hw/xen/trace.o
CC hw/ide/trace.o
CC ui/trace.o
CC audio/trace.o
CC net/trace.o
CC target/arm/trace.o
CC target/mips/trace.o
CC target/i386/trace.o
CC target/sparc/trace.o
CC target/s390x/trace.o
CC target/ppc/trace.o
CC qom/trace.o
CC linux-user/trace.o
CC qapi/trace.o
CC accel/tcg/trace.o
CC accel/kvm/trace.o
CC nbd/trace.o
CC scsi/trace.o
CC stubs/arch-query-cpu-def.o
CC stubs/arch-query-cpu-model-expansion.o
CC crypto/pbkdf-stub.o
CC stubs/arch-query-cpu-model-comparison.o
CC stubs/arch-query-cpu-model-baseline.o
CC stubs/bdrv-next-monitor-owned.o
CC stubs/blk-commit-all.o
CC stubs/blockdev-close-all-bdrv-states.o
CC stubs/clock-warp.o
CC stubs/cpu-get-clock.o
CC stubs/cpu-get-icount.o
CC stubs/dump.o
CC stubs/error-printf.o
CC stubs/fdset.o
CC stubs/gdbstub.o
CC stubs/get-vm-name.o
CC stubs/iothread.o
CC stubs/iothread-lock.o
CC stubs/is-daemonized.o
CC stubs/linux-aio.o
CC stubs/migr-blocker.o
CC stubs/machine-init-done.o
CC stubs/change-state-handler.o
CC stubs/monitor.o
CC stubs/notify-event.o
CC stubs/qtest.o
CC stubs/set-fd-handler.o
CC stubs/runstate-check.o
CC stubs/replay.o
CC stubs/slirp.o
CC stubs/sysbus.o
CC stubs/tpm.o
CC stubs/trace-control.o
CC stubs/uuid.o
CC stubs/vm-stop.o
CC stubs/qmp_pc_dimm.o
CC stubs/vmstate.o
CC stubs/target-monitor-defs.o
CC stubs/target-get-monitor-def.o
CC stubs/pc_madt_cpu_entry.o
CC stubs/vmgenid.o
CC stubs/xen-common.o
CC stubs/pci-host-piix.o
CC stubs/xen-hvm.o
CC contrib/ivshmem-client/ivshmem-client.o
CC contrib/ivshmem-client/main.o
CC contrib/ivshmem-server/ivshmem-server.o
CC contrib/ivshmem-server/main.o
CC qemu-nbd.o
CC block.o
CC blockjob.o
CC qemu-io-cmds.o
CC replication.o
CC block/raw-format.o
CC block/qcow.o
CC block/vdi.o
CC block/vmdk.o
CC block/bochs.o
CC block/cloop.o
CC block/vpc.o
CC block/vvfat.o
CC block/dmg.o
CC block/qcow2.o
CC block/qcow2-refcount.o
CC block/qcow2-cluster.o
CC block/qcow2-cache.o
CC block/qcow2-bitmap.o
CC block/qcow2-snapshot.o
CC block/qed.o
CC block/qed-l2-cache.o
CC block/qed-table.o
CC block/qed-cluster.o
CC block/qed-check.o
CC block/vhdx.o
CC block/quorum.o
CC block/vhdx-log.o
CC block/vhdx-endian.o
CC block/parallels.o
CC block/blkdebug.o
CC block/blkverify.o
CC block/blkreplay.o
CC block/block-backend.o
CC block/snapshot.o
CC block/qapi.o
CC block/file-posix.o
CC block/linux-aio.o
CC block/null.o
CC block/mirror.o
CC block/commit.o
CC block/io.o
CC block/throttle-groups.o
CC block/nbd.o
CC block/nbd-client.o
CC block/sheepdog.o
CC block/accounting.o
CC block/dirty-bitmap.o
CC block/write-threshold.o
CC block/backup.o
CC block/replication.o
CC block/throttle.o
CC block/crypto.o
CC nbd/server.o
CC nbd/client.o
CC nbd/common.o
CC scsi/utils.o
CC scsi/pr-manager.o
CC scsi/pr-manager-helper.o
CC block/curl.o
CC block/dmg-bz2.o
CC crypto/init.o
CC crypto/hash.o
CC crypto/hash-nettle.o
CC crypto/hmac.o
CC crypto/hmac-nettle.o
CC crypto/aes.o
CC crypto/desrfb.o
CC crypto/cipher.o
CC crypto/tlscreds.o
CC crypto/tlscredsanon.o
CC crypto/tlscredsx509.o
CC crypto/tlssession.o
CC crypto/secret.o
CC crypto/pbkdf.o
CC crypto/random-gnutls.o
CC crypto/pbkdf-nettle.o
CC crypto/ivgen.o
CC crypto/ivgen-essiv.o
CC crypto/afsplit.o
CC crypto/ivgen-plain.o
CC crypto/ivgen-plain64.o
CC crypto/xts.o
CC crypto/block.o
CC crypto/block-qcow.o
CC crypto/block-luks.o
CC io/channel.o
CC io/channel-buffer.o
CC io/channel-command.o
CC io/channel-file.o
CC io/channel-socket.o
CC io/channel-tls.o
CC io/channel-websock.o
CC io/channel-util.o
CC io/channel-watch.o
CC io/dns-resolver.o
CC io/task.o
CC qom/object.o
CC qom/container.o
CC qom/qom-qobject.o
CC qom/object_interfaces.o
GEN qemu-img-cmds.h
CC fsdev/virtfs-proxy-helper.o
CC qemu-io.o
CC fsdev/9p-marshal.o
CC fsdev/9p-iov-marshal.o
CC scsi/qemu-pr-helper.o
CC blockdev.o
CC qemu-bridge-helper.o
CC blockdev-nbd.o
CC iothread.o
CC bootdevice.o
CC qdev-monitor.o
CC device-hotplug.o
CC os-posix.o
CC bt-host.o
CC bt-vhci.o
CC dma-helpers.o
CC vl.o
CC tpm.o
CC device_tree.o
CC qmp-marshal.o
CC qmp.o
CC hmp.o
CC cpus-common.o
CC audio/audio.o
CC audio/noaudio.o
CC audio/wavaudio.o
CC audio/mixeng.o
CC audio/sdlaudio.o
CC audio/ossaudio.o
CC audio/wavcapture.o
CC backends/rng.o
CC backends/rng-egd.o
CC backends/tpm.o
CC backends/rng-random.o
CC backends/hostmem.o
CC backends/hostmem-ram.o
CC backends/hostmem-file.o
CC backends/cryptodev.o
CC backends/cryptodev-builtin.o
CC chardev/msmouse.o
CC chardev/wctablet.o
CC block/stream.o
CC chardev/testdev.o
CC disas/alpha.o
CC disas/arm.o
CXX disas/arm-a64.o
CC disas/cris.o
CC disas/hppa.o
CC disas/i386.o
CC disas/m68k.o
CC disas/microblaze.o
CC disas/mips.o
CC disas/nios2.o
CC disas/moxie.o
CC disas/ppc.o
CC disas/s390.o
CC disas/sh4.o
CC disas/lm32.o
CC disas/sparc.o
CXX disas/libvixl/vixl/utils.o
CXX disas/libvixl/vixl/compiler-intrinsics.o
CXX disas/libvixl/vixl/a64/instructions-a64.o
CXX disas/libvixl/vixl/a64/decoder-a64.o
CXX disas/libvixl/vixl/a64/disasm-a64.o
CC fsdev/qemu-fsdev.o
CC fsdev/qemu-fsdev-opts.o
CC fsdev/qemu-fsdev-throttle.o
CC fsdev/qemu-fsdev-dummy.o
CC hw/9pfs/9p.o
CC hw/9pfs/9p-util.o
CC hw/9pfs/9p-local.o
CC hw/9pfs/9p-xattr.o
CC hw/9pfs/9p-xattr-user.o
CC hw/9pfs/9p-posix-acl.o
CC hw/9pfs/coth.o
CC hw/9pfs/cofs.o
CC hw/9pfs/codir.o
CC hw/9pfs/cofile.o
CC hw/9pfs/9p-synth.o
CC hw/9pfs/coxattr.o
CC hw/9pfs/9p-handle.o
CC hw/9pfs/9p-proxy.o
CC hw/acpi/piix4.o
CC hw/acpi/pcihp.o
CC hw/acpi/core.o
CC hw/acpi/ich9.o
CC hw/acpi/tco.o
CC hw/acpi/cpu_hotplug.o
CC hw/acpi/memory_hotplug.o
CC hw/acpi/cpu.o
CC hw/acpi/nvdimm.o
CC hw/acpi/vmgenid.o
CC hw/acpi/acpi_interface.o
CC hw/acpi/bios-linker-loader.o
CC hw/acpi/aml-build.o
CC hw/acpi/ipmi.o
CC hw/acpi/acpi-stub.o
CC hw/acpi/ipmi-stub.o
CC hw/audio/sb16.o
CC hw/audio/es1370.o
CC hw/audio/ac97.o
CC hw/audio/fmopl.o
CC hw/audio/adlib.o
CC hw/audio/gus.o
CC hw/audio/gusemu_hal.o
CC hw/audio/gusemu_mixer.o
CC hw/audio/cs4231a.o
CC hw/audio/intel-hda.o
CC hw/audio/hda-codec.o
CC hw/audio/pcspk.o
CC hw/audio/pl041.o
CC hw/audio/wm8750.o
CC hw/audio/lm4549.o
CC hw/audio/cs4231.o
CC hw/audio/marvell_88w8618.o
CC hw/audio/milkymist-ac97.o
CC hw/audio/soundhw.o
CC hw/block/block.o
CC hw/block/cdrom.o
CC hw/block/hd-geometry.o
CC hw/block/fdc.o
CC hw/block/m25p80.o
CC hw/block/nand.o
CC hw/block/pflash_cfi01.o
CC hw/block/pflash_cfi02.o
CC hw/block/ecc.o
CC hw/block/onenand.o
CC hw/block/nvme.o
CC hw/bt/core.o
CC hw/bt/l2cap.o
CC hw/bt/sdp.o
CC hw/bt/hci.o
CC hw/bt/hid.o
CC hw/bt/hci-csr.o
CC hw/char/ipoctal232.o
CC hw/char/escc.o
CC hw/char/parallel.o
CC hw/char/pl011.o
CC hw/char/serial.o
CC hw/char/serial-isa.o
CC hw/char/serial-pci.o
CC hw/char/virtio-console.o
CC hw/char/xilinx_uartlite.o
CC hw/char/cadence_uart.o
CC hw/char/etraxfs_ser.o
CC hw/char/cmsdk-apb-uart.o
CC hw/char/debugcon.o
CC hw/char/imx_serial.o
CC hw/char/grlib_apbuart.o
CC hw/char/lm32_juart.o
CC hw/char/lm32_uart.o
CC hw/char/milkymist-uart.o
CC hw/char/sclpconsole.o
CC hw/char/sclpconsole-lm.o
CC hw/core/qdev.o
CC hw/core/qdev-properties.o
CC hw/core/bus.o
CC hw/core/reset.o
CC hw/core/fw-path-provider.o
CC hw/core/irq.o
CC hw/core/nmi.o
CC hw/core/hotplug.o
CC hw/core/empty_slot.o
CC hw/core/stream.o
CC hw/core/ptimer.o
CC hw/core/sysbus.o
CC hw/core/machine.o
CC hw/core/loader.o
CC hw/core/loader-fit.o
CC hw/core/qdev-properties-system.o
CC hw/core/register.o
CC hw/core/or-irq.o
CC hw/core/platform-bus.o
CC hw/cpu/core.o
CC hw/display/ads7846.o
CC hw/display/cirrus_vga.o
CC hw/display/g364fb.o
CC hw/display/jazz_led.o
CC hw/display/pl110.o
CC hw/display/ssd0303.o
CC hw/display/vga-pci.o
CC hw/display/ssd0323.o
CC hw/display/vga-isa.o
CC hw/display/vga-isa-mm.o
CC hw/display/vmware_vga.o
CC hw/display/blizzard.o
CC hw/display/exynos4210_fimd.o
CC hw/display/framebuffer.o
CC hw/display/milkymist-vgafb.o
CC hw/display/tc6393xb.o
CC hw/dma/puv3_dma.o
CC hw/dma/rc4030.o
CC hw/dma/pl080.o
CC hw/dma/pl330.o
CC hw/dma/i82374.o
CC hw/dma/i8257.o
CC hw/dma/xilinx_axidma.o
CC hw/dma/xlnx-zynq-devcfg.o
CC hw/dma/sparc32_dma.o
CC hw/dma/sun4m_iommu.o
CC hw/dma/etraxfs_dma.o
CC hw/gpio/pl061.o
CC hw/gpio/max7310.o
CC hw/gpio/puv3_gpio.o
CC hw/gpio/zaurus.o
CC hw/gpio/mpc8xxx.o
CC hw/gpio/gpio_key.o
CC hw/i2c/core.o
CC hw/i2c/smbus.o
CC hw/i2c/smbus_eeprom.o
CC hw/i2c/i2c-ddc.o
CC hw/i2c/versatile_i2c.o
CC hw/i2c/smbus_ich9.o
CC hw/i2c/pm_smbus.o
CC hw/i2c/bitbang_i2c.o
CC hw/i2c/exynos4210_i2c.o
CC hw/i2c/imx_i2c.o
CC hw/i2c/aspeed_i2c.o
CC hw/ide/core.o
CC hw/ide/atapi.o
CC hw/ide/qdev.o
CC hw/ide/pci.o
CC hw/ide/isa.o
CC hw/ide/piix.o
CC hw/ide/cmd646.o
CC hw/ide/macio.o
CC hw/ide/mmio.o
CC hw/ide/via.o
CC hw/ide/microdrive.o
CC hw/ide/ahci.o
CC hw/ide/ich.o
CC hw/ide/ahci-allwinner.o
CC hw/input/adb.o
CC hw/input/hid.o
CC hw/input/lm832x.o
CC hw/input/pckbd.o
CC hw/input/pl050.o
CC hw/input/ps2.o
CC hw/input/stellaris_input.o
CC hw/input/vmmouse.o
CC hw/input/virtio-input.o
CC hw/input/tsc2005.o
CC hw/input/virtio-input-hid.o
CC hw/input/virtio-input-host.o
CC hw/intc/heathrow_pic.o
CC hw/intc/i8259_common.o
CC hw/intc/i8259.o
CC hw/intc/pl190.o
CC hw/intc/puv3_intc.o
CC hw/intc/xilinx_intc.o
CC hw/intc/etraxfs_pic.o
CC hw/intc/imx_avic.o
CC hw/intc/lm32_pic.o
CC hw/intc/realview_gic.o
CC hw/intc/ioapic_common.o
CC hw/intc/slavio_intctl.o
CC hw/intc/arm_gic_common.o
CC hw/intc/arm_gic.o
CC hw/intc/arm_gicv2m.o
CC hw/intc/arm_gicv3_common.o
CC hw/intc/arm_gicv3.o
CC hw/intc/arm_gicv3_dist.o
CC hw/intc/arm_gicv3_redist.o
CC hw/intc/arm_gicv3_its_common.o
CC hw/intc/openpic.o
CC hw/intc/intc.o
CC hw/ipack/ipack.o
CC hw/ipack/tpci200.o
CC hw/ipmi/ipmi.o
CC hw/ipmi/ipmi_bmc_sim.o
CC hw/ipmi/ipmi_bmc_extern.o
CC hw/ipmi/isa_ipmi_kcs.o
CC hw/ipmi/isa_ipmi_bt.o
CC hw/isa/isa-bus.o
CC hw/isa/apm.o
CC hw/isa/i82378.o
CC hw/isa/pc87312.o
CC hw/isa/piix4.o
CC hw/isa/vt82c686.o
CC hw/mem/pc-dimm.o
CC hw/mem/nvdimm.o
CC hw/misc/applesmc.o
CC hw/misc/max111x.o
CC hw/misc/tmp105.o
CC hw/misc/tmp421.o
CC hw/misc/debugexit.o
CC hw/misc/sga.o
CC hw/misc/pc-testdev.o
CC hw/misc/pci-testdev.o
CC hw/misc/edu.o
CC hw/misc/unimp.o
CC hw/misc/vmcoreinfo.o
CC hw/misc/arm_l2x0.o
CC hw/misc/arm_integrator_debug.o
CC hw/misc/a9scu.o
CC hw/misc/arm11scu.o
CC hw/misc/puv3_pm.o
CC hw/misc/macio/macio.o
CC hw/misc/macio/cuda.o
CC hw/misc/macio/mac_dbdma.o
CC hw/net/dp8393x.o
CC hw/net/ne2000.o
CC hw/net/eepro100.o
CC hw/net/pcnet-pci.o
CC hw/net/e1000.o
CC hw/net/pcnet.o
CC hw/net/e1000x_common.o
CC hw/net/net_tx_pkt.o
CC hw/net/net_rx_pkt.o
CC hw/net/e1000e.o
CC hw/net/e1000e_core.o
CC hw/net/rtl8139.o
CC hw/net/vmxnet3.o
CC hw/net/smc91c111.o
CC hw/net/lan9118.o
CC hw/net/ne2000-isa.o
CC hw/net/opencores_eth.o
CC hw/net/xgmac.o
CC hw/net/mipsnet.o
CC hw/net/xilinx_axienet.o
CC hw/net/allwinner_emac.o
CC hw/net/imx_fec.o
CC hw/net/stellaris_enet.o
CC hw/net/cadence_gem.o
CC hw/net/lance.o
CC hw/net/sunhme.o
CC hw/net/ftgmac100.o
CC hw/net/sungem.o
CC hw/net/rocker/rocker_fp.o
CC hw/net/rocker/rocker_desc.o
CC hw/net/rocker/rocker_world.o
CC hw/net/rocker/rocker.o
CC hw/net/rocker/rocker_of_dpa.o
CC hw/nvram/eeprom93xx.o
CC hw/nvram/ds1225y.o
CC hw/nvram/fw_cfg.o
CC hw/nvram/chrp_nvram.o
CC hw/nvram/mac_nvram.o
CC hw/pci-bridge/pci_bridge_dev.o
CC hw/pci-bridge/pcie_root_port.o
CC hw/pci-bridge/gen_pcie_root_port.o
CC hw/pci-bridge/pcie_pci_bridge.o
CC hw/pci-bridge/pci_expander_bridge.o
CC hw/pci-bridge/xio3130_upstream.o
CC hw/pci-bridge/xio3130_downstream.o
CC hw/pci-bridge/ioh3420.o
CC hw/pci-bridge/i82801b11.o
CC hw/pci-bridge/dec.o
CC hw/pci-host/pam.o
CC hw/pci-host/prep.o
CC hw/pci-host/grackle.o
CC hw/pci-host/uninorth.o
CC hw/pci-host/ppce500.o
CC hw/pci-host/versatile.o
CC hw/pci-host/apb.o
CC hw/pci-host/bonito.o
CC hw/pci-host/piix.o
CC hw/pci-host/q35.o
CC hw/pci-host/gpex.o
CC hw/pci-host/xilinx-pcie.o
CC hw/pci/pci.o
CC hw/pci/pci_bridge.o
CC hw/pci/msix.o
CC hw/pci/msi.o
CC hw/pci/shpc.o
CC hw/pci/slotid_cap.o
CC hw/pci/pci_host.o
CC hw/pci/pcie_host.o
CC hw/pci/pcie.o
CC hw/pci/pcie_aer.o
CC hw/pci/pcie_port.o
CC hw/pci/pci-stub.o
CC hw/pcmcia/pcmcia.o
CC hw/scsi/scsi-disk.o
CC hw/scsi/scsi-generic.o
CC hw/scsi/scsi-bus.o
CC hw/scsi/lsi53c895a.o
CC hw/scsi/mptsas.o
CC hw/scsi/mptconfig.o
CC hw/scsi/mptendian.o
CC hw/scsi/megasas.o
CC hw/scsi/vmw_pvscsi.o
CC hw/scsi/esp.o
CC hw/scsi/esp-pci.o
CC hw/sd/pl181.o
CC hw/sd/ssi-sd.o
CC hw/sd/sd.o
CC hw/sd/core.o
CC hw/sd/sdhci.o
CC hw/smbios/smbios.o
CC hw/smbios/smbios_type_38.o
CC hw/smbios/smbios-stub.o
CC hw/smbios/smbios_type_38-stub.o
CC hw/ssi/pl022.o
CC hw/ssi/ssi.o
CC hw/ssi/xilinx_spi.o
CC hw/ssi/xilinx_spips.o
CC hw/ssi/aspeed_smc.o
CC hw/ssi/stm32f2xx_spi.o
CC hw/ssi/mss-spi.o
CC hw/timer/arm_timer.o
CC hw/timer/arm_mptimer.o
CC hw/timer/armv7m_systick.o
CC hw/timer/a9gtimer.o
CC hw/timer/ds1338.o
CC hw/timer/cadence_ttc.o
CC hw/timer/hpet.o
CC hw/timer/i8254_common.o
CC hw/timer/i8254.o
CC hw/timer/m48t59.o
CC hw/timer/pl031.o
CC hw/timer/puv3_ost.o
CC hw/timer/m48t59-isa.o
CC hw/timer/twl92230.o
CC hw/timer/xilinx_timer.o
CC hw/timer/slavio_timer.o
CC hw/timer/etraxfs_timer.o
CC hw/timer/imx_epit.o
CC hw/timer/imx_gpt.o
CC hw/timer/grlib_gptimer.o
CC hw/timer/lm32_timer.o
CC hw/timer/milkymist-sysctl.o
CC hw/timer/stm32f2xx_timer.o
CC hw/timer/sun4v-rtc.o
CC hw/timer/aspeed_timer.o
CC hw/timer/cmsdk-apb-timer.o
CC hw/timer/mss-timer.o
CC hw/tpm/tpm_tis.o
CC hw/tpm/tpm_emulator.o
CC hw/tpm/tpm_util.o
CC hw/usb/core.o
CC hw/usb/combined-packet.o
CC hw/usb/bus.o
CC hw/usb/libhw.o
CC hw/usb/desc.o
CC hw/usb/desc-msos.o
CC hw/usb/hcd-uhci.o
CC hw/usb/hcd-ohci.o
CC hw/usb/hcd-ehci.o
CC hw/usb/hcd-ehci-pci.o
CC hw/usb/hcd-ehci-sysbus.o
CC hw/usb/hcd-xhci.o
CC hw/usb/hcd-xhci-nec.o
CC hw/usb/hcd-musb.o
CC hw/usb/dev-hub.o
CC hw/usb/dev-hid.o
CC hw/usb/dev-wacom.o
CC hw/usb/dev-uas.o
CC hw/usb/dev-storage.o
CC hw/usb/dev-audio.o
CC hw/usb/dev-serial.o
CC hw/usb/dev-network.o
CC hw/usb/dev-bluetooth.o
CC hw/usb/dev-smartcard-reader.o
CC hw/usb/dev-mtp.o
CC hw/usb/host-libusb.o
CC hw/usb/host-legacy.o
CC hw/usb/host-stub.o
CC hw/virtio/virtio-rng.o
CC hw/virtio/virtio-pci.o
CC hw/virtio/virtio-bus.o
CC hw/virtio/virtio-mmio.o
CC hw/virtio/vhost-stub.o
CC hw/watchdog/watchdog.o
CC hw/watchdog/wdt_ib700.o
CC hw/watchdog/wdt_i6300esb.o
CC hw/watchdog/wdt_diag288.o
CC hw/watchdog/wdt_aspeed.o
CC migration/migration.o
CC migration/socket.o
CC migration/fd.o
CC migration/exec.o
CC migration/tls.o
CC migration/channel.o
CC migration/savevm.o
CC migration/colo-comm.o
CC migration/colo.o
CC migration/colo-failover.o
CC migration/vmstate.o
CC migration/vmstate-types.o
CC migration/page_cache.o
CC migration/qemu-file.o
CC migration/global_state.o
CC migration/qemu-file-channel.o
CC migration/xbzrle.o
CC migration/postcopy-ram.o
CC migration/qjson.o
CC migration/rdma.o
CC migration/block.o
CC net/net.o
CC net/queue.o
CC net/checksum.o
CC net/util.o
CC net/hub.o
CC net/socket.o
CC net/eth.o
CC net/dump.o
CC net/l2tpv3.o
CC net/vhost-user.o
CC net/slirp.o
CC net/filter.o
CC net/filter-buffer.o
CC net/filter-mirror.o
CC net/colo-compare.o
CC net/colo.o
CC net/filter-rewriter.o
CC net/filter-replay.o
CC net/tap.o
CC net/tap-linux.o
CC qom/cpu.o
CC replay/replay.o
CC replay/replay-internal.o
CC replay/replay-events.o
CC replay/replay-time.o
CC replay/replay-input.o
CC replay/replay-char.o
CC replay/replay-snapshot.o
CC replay/replay-net.o
CC replay/replay-audio.o
CC slirp/cksum.o
CC slirp/if.o
CC slirp/ip_icmp.o
CC slirp/ip6_icmp.o
CC slirp/ip6_input.o
CC slirp/ip6_output.o
CC slirp/ip_input.o
CC slirp/ip_output.o
CC slirp/dnssearch.o
CC slirp/dhcpv6.o
CC slirp/slirp.o
CC slirp/mbuf.o
CC slirp/misc.o
CC slirp/sbuf.o
CC slirp/socket.o
CC slirp/tcp_input.o
CC slirp/tcp_output.o
CC slirp/tcp_subr.o
CC slirp/tcp_timer.o
CC slirp/udp.o
CC slirp/bootp.o
CC slirp/udp6.o
CC slirp/tftp.o
CC slirp/arp_table.o
CC slirp/ndp_table.o
CC slirp/ncsi.o
CC ui/keymaps.o
CC ui/console.o
CC ui/cursor.o
CC ui/qemu-pixman.o
CC ui/input.o
CC ui/input-keymap.o
CC ui/input-legacy.o
CC ui/input-linux.o
CC ui/sdl.o
CC ui/sdl_zoom.o
CC ui/x_keymap.o
CC ui/curses.o
CC ui/vnc.o
CC ui/vnc-enc-zlib.o
CC ui/vnc-enc-hextile.o
CC ui/vnc-enc-tight.o
CC ui/vnc-palette.o
CC ui/vnc-enc-zrle.o
CC ui/vnc-auth-vencrypt.o
CC ui/vnc-auth-sasl.o
CC ui/vnc-ws.o
CC ui/gtk.o
CC ui/vnc-jobs.o
CC chardev/char.o
CC chardev/char-fd.o
CC chardev/char-fe.o
CC chardev/char-file.o
CC chardev/char-io.o
CC chardev/char-mux.o
CC chardev/char-null.o
CC chardev/char-parallel.o
CC chardev/char-pipe.o
CC chardev/char-pty.o
CC chardev/char-ringbuf.o
CC chardev/char-serial.o
CC chardev/char-socket.o
CC chardev/char-stdio.o
CC chardev/char-udp.o
CCAS spapr-rtas/spapr-rtas.o
LINK tests/qemu-iotests/socket_scm_helper
CC qga/commands.o
CC qga/guest-agent-command-state.o
CC qga/main.o
CC qga/commands-posix.o
CC qga/channel-posix.o
CC qga/qapi-generated/qga-qapi-visit.o
CC qga/qapi-generated/qga-qapi-types.o
Building spapr-rtas/spapr-rtas.img
CC qga/qapi-generated/qga-qmp-marshal.o
CC qemu-img.o
Building spapr-rtas/spapr-rtas.bin
rm spapr-rtas.img spapr-rtas.o
AR libqemuutil.a
LINK qemu-ga
LINK ivshmem-client
LINK ivshmem-server
LINK qemu-nbd
LINK qemu-img
LINK qemu-io
LINK fsdev/virtfs-proxy-helper
LINK scsi/qemu-pr-helper
LINK qemu-bridge-helper
GEN ppc-linux-user/config-target.h
GEN mips64el-linux-user/config-target.h
GEN i386-linux-user/config-target.h
GEN m68k-linux-user/config-target.h
CC i386-linux-user/exec.o
CC i386-linux-user/tcg/tcg.o
CC i386-linux-user/tcg/tcg-op.o
CC i386-linux-user/tcg/tcg-op-vec.o
CC i386-linux-user/tcg/tcg-op-gvec.o
CC ppc-linux-user/exec.o
CC ppc-linux-user/tcg/tcg.o
CC ppc-linux-user/tcg/tcg-op.o
CC i386-linux-user/tcg/tcg-common.o
GEN alpha-linux-user/config-target.h
CC i386-linux-user/tcg/optimize.o
CC ppc-linux-user/tcg/tcg-op-vec.o
CC i386-linux-user/fpu/softfloat.o
CC ppc-linux-user/tcg/tcg-op-gvec.o
CC mips64el-linux-user/exec.o
CC mips64el-linux-user/tcg/tcg.o
CC ppc-linux-user/tcg/tcg-common.o
CC ppc-linux-user/tcg/optimize.o
CC mips64el-linux-user/tcg/tcg-op.o
CC mips64el-linux-user/tcg/tcg-op-vec.o
CC ppc-linux-user/fpu/softfloat.o
GEN tilegx-linux-user/config-target.h
CC i386-linux-user/disas.o
GEN aarch64-linux-user/config-target.h
CC alpha-linux-user/exec.o
GEN microblaze-linux-user/config-target.h
CC ppc-linux-user/disas.o
CC mips64el-linux-user/tcg/tcg-op-gvec.o
GEN i386-linux-user/gdbstub-xml.c
CC alpha-linux-user/tcg/tcg.o
CC i386-linux-user/accel/stubs/hax-stub.o
CC i386-linux-user/accel/stubs/kvm-stub.o
CC mips64el-linux-user/tcg/optimize.o
CC ppc-linux-user/gdbstub.o
CC i386-linux-user/accel/tcg/tcg-runtime-gvec.o
CC alpha-linux-user/tcg/tcg-op.o
CC mips64el-linux-user/fpu/softfloat.o
GEN cris-linux-user/config-target.h
CC mips64el-linux-user/disas.o
CC ppc-linux-user/thunk.o
CC ppc-linux-user/accel/stubs/hax-stub.o
CC alpha-linux-user/tcg/tcg-op-vec.o
GEN ppc-linux-user/gdbstub-xml.c
CC i386-linux-user/accel/tcg/cpu-exec-common.o
CC i386-linux-user/gdbstub.o
CC mips64el-linux-user/gdbstub.o
CC mips64el-linux-user/tcg/tcg-common.o
GEN microblazeel-linux-user/config-target.h
GEN mips64-linux-user/config-target.h
CC m68k-linux-user/exec.o
CC i386-linux-user/accel/tcg/tcg-runtime.o
CC i386-linux-user/accel/tcg/cpu-exec.o
CC i386-linux-user/thunk.o
CC aarch64-linux-user/exec.o
GEN ppc64abi32-linux-user/config-target.h
GEN sparc-linux-user/config-target.h
CC microblaze-linux-user/exec.o
CC tilegx-linux-user/exec.o
CC cris-linux-user/exec.o
CC microblazeel-linux-user/exec.o
CC mips64-linux-user/exec.o
GEN sparc32plus-linux-user/config-target.h
CC ppc64abi32-linux-user/exec.o
CC sparc-linux-user/exec.o
GEN sh4eb-linux-user/config-target.h
GEN mipsel-linux-user/config-target.h
GEN sh4-linux-user/config-target.h
GEN mipsn32-linux-user/config-target.h
GEN or1k-linux-user/config-target.h
CC sparc32plus-linux-user/exec.o
GEN hppa-linux-user/config-target.h
CC s390x-linux-user/gen-features
GEN sparc64-linux-user/config-target.h
CC sh4eb-linux-user/exec.o
CC mipsel-linux-user/exec.o
GEN mips-linux-user/config-target.h
GEN armeb-linux-user/config-target.h
CC or1k-linux-user/exec.o
CC sh4-linux-user/exec.o
CC sparc64-linux-user/exec.o
CC mipsn32-linux-user/exec.o
GEN ppc64-linux-user/config-target.h
GEN arm-linux-user/config-target.h
GEN mipsn32el-linux-user/config-target.h
CC hppa-linux-user/exec.o
CC mipsel-linux-user/tcg/tcg.o
GEN nios2-linux-user/config-target.h
GEN ppc64le-linux-user/config-target.h
CC mips-linux-user/exec.o
CC nios2-linux-user/exec.o
CC arm-linux-user/exec.o
CC armeb-linux-user/exec.o
GEN x86_64-linux-user/config-target.h
GEN sparc-softmmu/hmp-commands.h
CC ppc64-linux-user/exec.o
CC armeb-linux-user/tcg/tcg.o
CC mipsn32el-linux-user/exec.o
CC hppa-linux-user/tcg/tcg.o
CC ppc64le-linux-user/exec.o
CC x86_64-linux-user/exec.o
CC sh4-linux-user/tcg/tcg.o
CC mipsn32el-linux-user/tcg/tcg.o
GEN s390x-linux-user/config-target.h
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC sh4eb-linux-user/tcg/tcg.o
CC ppc-linux-user/accel/stubs/kvm-stub.o
CC mipsel-linux-user/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
GEN s390x-linux-user/gen-features.h
cc1: all warnings being treated as errors
cc1: all warnings being treated as errors
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4eb-linux-user/tcg/tcg-op.o
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc32plus-linux-user/tcg/tcg.o
CC ppc64abi32-linux-user/tcg/tcg.o
GEN mips-softmmu/hmp-commands.h
CC s390x-linux-user/exec.o
CC ppc64abi32-linux-user/tcg/tcg-op.o
GEN unicore32-softmmu/hmp-commands.h
GEN sparc-softmmu/hmp-commands-info.h
GEN moxie-softmmu/hmp-commands.h
CC ppc64abi32-linux-user/tcg/tcg-op-vec.o
CC tilegx-linux-user/tcg/tcg.o
GEN cris-softmmu/hmp-commands.h
CC hppa-linux-user/tcg/tcg-op.o
CC sparc-linux-user/tcg/tcg.o
GEN microblazeel-softmmu/hmp-commands.h
GEN mips-softmmu/hmp-commands-info.h
GEN xtensaeb-softmmu/hmp-commands.h
CC s390x-linux-user/tcg/tcg.o
GEN moxie-softmmu/hmp-commands-info.h
CC sparc64-linux-user/tcg/tcg.o
GEN or1k-softmmu/hmp-commands.h
GEN sparc-softmmu/config-target.h
CC sparc-softmmu/exec.o
GEN xtensaeb-softmmu/hmp-commands-info.h
GEN nios2-softmmu/hmp-commands.h
GEN moxie-softmmu/config-target.h
CC ppc64abi32-linux-user/tcg/tcg-op-gvec.o
GEN xtensaeb-softmmu/config-target.h
CC moxie-softmmu/exec.o
GEN cris-softmmu/hmp-commands-info.h
CC moxie-softmmu/tcg/tcg.o
GEN mips-softmmu/config-target.h
GEN s390x-softmmu/hmp-commands.h
CC tilegx-linux-user/tcg/tcg-op.o
CC mipsn32el-linux-user/tcg/tcg-op.o
CC xtensaeb-softmmu/exec.o
GEN or1k-softmmu/hmp-commands-info.h
GEN microblazeel-softmmu/hmp-commands-info.h
GEN xtensa-softmmu/hmp-commands.h
GEN unicore32-softmmu/hmp-commands-info.h
CC mipsn32el-linux-user/tcg/tcg-op-vec.o
GEN ppcemb-softmmu/hmp-commands.h
CC mips-softmmu/exec.o
CC microblazeel-linux-user/tcg/tcg.o
CC m68k-linux-user/tcg/tcg.o
GEN microblaze-softmmu/hmp-commands.h
GEN cris-softmmu/config-target.h
CC m68k-linux-user/tcg/tcg-op.o
CC cris-linux-user/tcg/tcg.o
CC or1k-linux-user/tcg/tcg.o
CC m68k-linux-user/tcg/tcg-op-vec.o
CC cris-softmmu/exec.o
GEN nios2-softmmu/hmp-commands-info.h
GEN or1k-softmmu/config-target.h
GEN alpha-softmmu/hmp-commands.h
GEN m68k-softmmu/hmp-commands.h
GEN ppc64-softmmu/hmp-commands.h
GEN microblazeel-softmmu/config-target.h
CC mipsn32-linux-user/tcg/tcg.o
CC mips64-linux-user/tcg/tcg.o
CC aarch64-linux-user/tcg/tcg.o
GEN tricore-softmmu/hmp-commands.h
GEN unicore32-softmmu/config-target.h
GEN mips64el-softmmu/hmp-commands.h
GEN tricore-softmmu/hmp-commands-info.h
CC or1k-softmmu/exec.o
CC microblazeel-softmmu/exec.o
GEN lm32-softmmu/hmp-commands.h
GEN s390x-softmmu/hmp-commands-info.h
GEN lm32-softmmu/hmp-commands-info.h
CC unicore32-softmmu/exec.o
CC ppc64abi32-linux-user/tcg/tcg-common.o
GEN sparc64-softmmu/hmp-commands.h
GEN sparc64-softmmu/hmp-commands-info.h
CC s390x-linux-user/tcg/tcg-op.o
GEN mips64-softmmu/hmp-commands.h
CC microblaze-linux-user/tcg/tcg.o
GEN mipsel-softmmu/hmp-commands.h
GEN nios2-softmmu/config-target.h
GEN xtensa-softmmu/hmp-commands-info.h
CC xtensaeb-softmmu/tcg/tcg.o
GEN ppcemb-softmmu/hmp-commands-info.h
GEN ppc64-softmmu/hmp-commands-info.h
CC nios2-linux-user/tcg/tcg.o
GEN microblaze-softmmu/hmp-commands-info.h
CC nios2-softmmu/exec.o
GEN xtensa-softmmu/config-target.h
CC xtensaeb-softmmu/tcg/tcg-op.o
CC cris-linux-user/tcg/tcg-op.o
CC or1k-softmmu/tcg/tcg.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC sh4eb-linux-user/tcg/tcg-op-vec.o
GEN sh4eb-softmmu/hmp-commands.h
GEN mips64el-softmmu/hmp-commands-info.h
GEN tricore-softmmu/config-target.h
GEN m68k-softmmu/hmp-commands-info.h
CC ppc64le-linux-user/tcg/tcg.o
GEN mips64el-softmmu/config-target.h
CC s390x-softmmu/gen-features
GEN alpha-softmmu/hmp-commands-info.h
CC xtensa-softmmu/exec.o
CC mips-linux-user/tcg/tcg.o
GEN ppc64-softmmu/config-target.h
CC ppc64abi32-linux-user/tcg/optimize.o
GEN ppcemb-softmmu/config-target.h
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC tricore-softmmu/exec.o
GEN microblaze-softmmu/config-target.h
GEN mips64-softmmu/hmp-commands-info.h
CC x86_64-linux-user/tcg/tcg.o
CC sparc64-linux-user/tcg/tcg-op.o
CC unicore32-softmmu/tcg/tcg.o
CC ppcemb-softmmu/exec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC ppc64-softmmu/exec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/accel/tcg/tcg-runtime-gvec.c: In function ‘helper_gvec_shl8i’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/accel/tcg/tcg-runtime-gvec.c:353:26: internal compiler error: in emit_move_insn, at expr.c:3495
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
^
CC microblaze-softmmu/exec.o
GEN ppc-softmmu/hmp-commands.h
CC arm-linux-user/tcg/tcg.o
GEN sparc64-softmmu/config-target.h
cc1: all warnings being treated as errors
CC mips64el-softmmu/exec.o
make[1]: *** [tcg/tcg-op-vec.o] Error 1
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
GEN m68k-softmmu/config-target.h
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC sparc64-softmmu/exec.o
CC arm-linux-user/tcg/tcg-op.o
GEN lm32-softmmu/config-target.h
GEN mipsel-softmmu/hmp-commands-info.h
GEN alpha-softmmu/config-target.h
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://bugzilla.redhat.com/bugzilla> for instructions.
CC cris-linux-user/tcg/tcg-op-vec.o
CC arm-linux-user/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
CC m68k-softmmu/exec.o
GEN ppc-softmmu/hmp-commands-info.h
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
GEN sh4eb-softmmu/hmp-commands-info.h
GEN mips64-softmmu/config-target.h
CC xtensa-softmmu/tcg/tcg.o
CC lm32-softmmu/exec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC alpha-softmmu/exec.o
GEN s390x-softmmu/config-target.h
cc1: all warnings being treated as errors
GEN ppc-softmmu/config-target.h
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
GEN s390x-softmmu/gen-features.h
CC mips64-softmmu/exec.o
CC moxie-softmmu/tcg/tcg-op.o
CC ppc64-linux-user/tcg/tcg.o
GEN sh4eb-softmmu/config-target.h
CC ppc-softmmu/exec.o
CC s390x-softmmu/exec.o
GEN mipsel-softmmu/config-target.h
GEN i386-softmmu/hmp-commands.h
CC sh4eb-softmmu/exec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC mipsel-softmmu/exec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC moxie-softmmu/tcg/tcg-op-vec.o
GEN arm-softmmu/hmp-commands.h
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC aarch64-linux-user/tcg/tcg-op.o
GEN sh4-softmmu/hmp-commands.h
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC alpha-softmmu/tcg/tcg.o
GEN i386-softmmu/hmp-commands-info.h
GEN aarch64-softmmu/hmp-commands.h
GEN x86_64-softmmu/hmp-commands.h
CC unicore32-softmmu/tcg/tcg-op.o
GEN i386-softmmu/config-target.h
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC i386-softmmu/exec.o
CC microblazeel-linux-user/tcg/tcg-op.o
GEN aarch64-softmmu/hmp-commands-info.h
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
GEN sh4-softmmu/hmp-commands-info.h
GEN arm-softmmu/hmp-commands-info.h
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
CC microblazeel-softmmu/tcg/tcg.o
GEN aarch64-softmmu/config-target.h
CC aarch64-softmmu/exec.o
GEN x86_64-softmmu/hmp-commands-info.h
GEN arm-softmmu/config-target.h
GEN sh4-softmmu/config-target.h
CC aarch64-softmmu/tcg/tcg.o
CC sh4-softmmu/exec.o
CC arm-softmmu/exec.o
GEN x86_64-softmmu/config-target.h
CC x86_64-softmmu/exec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC tricore-softmmu/tcg/tcg.o
CC mips64-linux-user/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc64-linux-user/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC microblaze-softmmu/tcg/tcg.o
CC aarch64-softmmu/tcg/tcg-op.o
CC unicore32-softmmu/tcg/tcg-op-vec.o
CC mipsn32-linux-user/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC x86_64-softmmu/tcg/tcg.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC armeb-linux-user/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc-linux-user/tcg/tcg-op.o
CC mips64el-softmmu/tcg/tcg.o
Preprocessed source stored into /tmp/cc8jl9UX.out file, please attach this to your bugreport.
make[1]: *** [accel/tcg/tcg-runtime-gvec.o] Error 1
CC mips64-linux-user/tcg/tcg-op-vec.o
CC aarch64-linux-user/tcg/tcg-op-vec.o
CC xtensaeb-softmmu/tcg/tcg-op-vec.o
CC nios2-linux-user/tcg/tcg-op.o
make: *** [subdir-mipsn32el-linux-user] Error 2
make: *** Waiting for unfinished jobs....
CC s390x-linux-user/tcg/tcg-op-vec.o
CC cris-softmmu/tcg/tcg.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64el-softmmu/tcg/tcg-op.o
CC mips64el-softmmu/tcg/tcg-op-vec.o
CC microblaze-softmmu/tcg/tcg-op.o
CC or1k-softmmu/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC s390x-linux-user/tcg/tcg-op-gvec.o
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mips64-linux-user/tcg/tcg-op-gvec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC cris-softmmu/tcg/tcg-op.o
CC cris-softmmu/tcg/tcg-op-vec.o
CC sparc32plus-linux-user/tcg/tcg-op.o
CC microblaze-linux-user/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC microblaze-linux-user/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC lm32-softmmu/tcg/tcg.o
CC or1k-linux-user/tcg/tcg-op.o
CC mipsel-softmmu/tcg/tcg.o
make: *** [subdir-alpha-linux-user] Error 2
CC mipsel-linux-user/tcg/tcg-op-vec.o
CC nios2-softmmu/tcg/tcg.o
CC alpha-softmmu/tcg/tcg-op.o
CC alpha-softmmu/tcg/tcg-op-vec.o
CC s390x-softmmu/tcg/tcg.o
CC ppc64le-linux-user/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC mips-softmmu/tcg/tcg.o
CC microblaze-linux-user/tcg/tcg-op-gvec.o
cc1: all warnings being treated as errors
CC arm-softmmu/tcg/tcg.o
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC arm-softmmu/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC sparc-softmmu/tcg/tcg.o
CC tricore-softmmu/tcg/tcg-op.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc32plus-linux-user/tcg/tcg-op-vec.o
CC sh4-linux-user/tcg/tcg-op.o
CC alpha-softmmu/tcg/tcg-op-gvec.o
make: *** [subdir-s390x-linux-user] Error 2
CC mipsel-softmmu/tcg/tcg-op.o
CC aarch64-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC x86_64-softmmu/tcg/tcg-op.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppc64-softmmu/tcg/tcg.o
CC microblaze-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc-linux-user/tcg/tcg-op-vec.o
CC mipsn32-linux-user/tcg/tcg-op-vec.o
CC mipsel-linux-user/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC s390x-softmmu/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC sparc-softmmu/tcg/tcg-op.o
CC microblaze-softmmu/tcg/tcg-op-gvec.o
CC nios2-linux-user/tcg/tcg-op-vec.o
CC tilegx-linux-user/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppc64-softmmu/tcg/tcg-op.o
CC mips-linux-user/tcg/tcg-op.o
CC ppc64-softmmu/tcg/tcg-op-vec.o
CC m68k-softmmu/tcg/tcg.o
CC arm-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC microblazeel-linux-user/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
CC hppa-linux-user/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC armeb-linux-user/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC xtensa-softmmu/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make: *** [subdir-m68k-linux-user] Error 2
CC sparc-softmmu/tcg/tcg-op-vec.o
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC mips64-softmmu/tcg/tcg.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC s390x-softmmu/tcg/tcg-op-vec.o
make: *** [subdir-i386-linux-user] Error 2
CC sparc64-softmmu/tcg/tcg.o
CC x86_64-linux-user/tcg/tcg-op.o
CC mips-softmmu/tcg/tcg-op.o
CC ppc64-softmmu/tcg/tcg-op-gvec.o
CC s390x-softmmu/tcg/tcg-op-gvec.o
make: *** [subdir-sh4eb-linux-user] Error 2
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC nios2-linux-user/tcg/tcg-op-gvec.o
CC s390x-softmmu/tcg/tcg-common.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4eb-softmmu/tcg/tcg.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC mips-softmmu/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make: *** [subdir-mipsel-linux-user] Error 2
CC mipsel-softmmu/tcg/tcg-op-vec.o
CC arm-softmmu/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
CC i386-softmmu/tcg/tcg.o
make: *** [subdir-microblazeel-linux-user] Error 2
CC tilegx-linux-user/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
make: *** [subdir-cris-linux-user] Error 2
CC mips-linux-user/tcg/tcg-op-vec.o
CC m68k-softmmu/tcg/tcg-op.o
CC ppcemb-softmmu/tcg/tcg.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC lm32-softmmu/tcg/tcg-op.o
CC armeb-linux-user/tcg/tcg-op-gvec.o
CC arm-softmmu/tcg/tcg-common.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [subdir-moxie-softmmu] Error 2
CC nios2-softmmu/tcg/tcg-op.o
CC or1k-linux-user/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [subdir-sparc64-linux-user] Error 2
CC ppc64-softmmu/tcg/tcg-common.o
CC mips-softmmu/tcg/tcg-op-gvec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC m68k-softmmu/tcg/tcg-op-vec.o
CC sh4-linux-user/tcg/tcg-op-vec.o
CC mipsel-softmmu/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
cc1: all warnings being treated as errors
CC ppc64-linux-user/tcg/tcg-op.o
make: *** [subdir-hppa-linux-user] Error 2
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC or1k-linux-user/tcg/tcg-op-gvec.o
CC tricore-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppcemb-softmmu/tcg/tcg-op.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
CC ppc64le-linux-user/tcg/tcg-op-vec.o
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [subdir-mips64-linux-user] Error 2
CC mips-softmmu/tcg/tcg-common.o
CC xtensa-softmmu/tcg/tcg-op-vec.o
CC mips-softmmu/tcg/optimize.o
CC x86_64-linux-user/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC mips64-softmmu/tcg/tcg-op.o
CC x86_64-softmmu/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC i386-softmmu/tcg/tcg-op.o
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC sh4eb-softmmu/tcg/tcg-op.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make: *** [subdir-tilegx-linux-user] Error 2
CC tricore-softmmu/tcg/tcg-op-gvec.o
make: *** [subdir-ppc64abi32-linux-user] Error 2
CC sh4eb-softmmu/tcg/tcg-op-vec.o
CC sh4eb-softmmu/tcg/tcg-op-gvec.o
make: *** [subdir-unicore32-softmmu] Error 2
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC i386-softmmu/tcg/tcg-op-vec.o
CC mips-linux-user/tcg/tcg-op-gvec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC mipsel-softmmu/tcg/tcg-common.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC ppc64le-linux-user/tcg/tcg-op-gvec.o
CC or1k-softmmu/tcg/tcg-op-vec.o
CC mips64-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC sh4eb-softmmu/tcg/tcg-common.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4-softmmu/tcg/tcg.o
cc1: all warnings being treated as errors
make: *** [subdir-ppc-linux-user] Error 2
make: *** [subdir-xtensaeb-softmmu] Error 2
CC ppc-softmmu/tcg/tcg.o
CC sh4-softmmu/tcg/tcg-op.o
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4-linux-user/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4eb-softmmu/tcg/optimize.o
CC mips-softmmu/fpu/softfloat.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC x86_64-softmmu/tcg/tcg-op-gvec.o
CC microblazeel-softmmu/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC or1k-softmmu/tcg/tcg-op-gvec.o
cc1: all warnings being treated as errors
cc1: all warnings being treated as errors
CC ppc64le-linux-user/tcg/tcg-common.o
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
CC microblazeel-softmmu/tcg/tcg-op-vec.o
CC ppc64-linux-user/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
CC ppc-softmmu/tcg/tcg-op.o
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC x86_64-softmmu/tcg/tcg-common.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make: *** [subdir-armeb-linux-user] Error 2
CC mips64-softmmu/tcg/tcg-op-gvec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
CC nios2-softmmu/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC i386-softmmu/tcg/tcg-op-gvec.o
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC sh4-softmmu/tcg/tcg-op-vec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC microblazeel-softmmu/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
make: *** [subdir-arm-linux-user] Error 2
CC microblazeel-softmmu/tcg/tcg-common.o
cc1: all warnings being treated as errors
make: *** [subdir-aarch64-linux-user] Error 2
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC x86_64-softmmu/tcg/optimize.o
CC i386-softmmu/tcg/tcg-common.o
CC ppc64-linux-user/tcg/tcg-op-gvec.o
make: *** [subdir-aarch64-softmmu] Error 2
CC i386-softmmu/tcg/optimize.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC sh4-softmmu/tcg/tcg-op-gvec.o
CC ppcemb-softmmu/tcg/tcg-op-vec.o
CC mips-linux-user/tcg/tcg-common.o
CC lm32-softmmu/tcg/tcg-op-vec.o
CC microblazeel-softmmu/tcg/optimize.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC x86_64-softmmu/fpu/softfloat.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC x86_64-linux-user/tcg/tcg-op-gvec.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4-softmmu/tcg/tcg-common.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sh4-softmmu/tcg/optimize.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
CC nios2-softmmu/tcg/tcg-op-gvec.o
CC x86_64-linux-user/tcg/tcg-common.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc-softmmu/tcg/tcg-op-vec.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc-softmmu/tcg/tcg-op-gvec.o
CC sh4-softmmu/fpu/softfloat.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC lm32-softmmu/tcg/tcg-op-gvec.o
CC ppc-softmmu/tcg/tcg-common.o
CC sh4-softmmu/disas.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
cc1: all warnings being treated as errors
cc1: all warnings being treated as errors
CC mips64-softmmu/tcg/tcg-common.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc-softmmu/tcg/optimize.o
CC lm32-softmmu/tcg/tcg-common.o
make[1]: *** [tcg/tcg-op-vec.o] Error 1
CC nios2-softmmu/tcg/tcg-common.o
CC lm32-softmmu/tcg/optimize.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC nios2-softmmu/tcg/optimize.o
CC lm32-softmmu/fpu/softfloat.o
CC ppc64-linux-user/tcg/tcg-common.o
make: *** [subdir-microblaze-softmmu] Error 2
CC ppc64-linux-user/tcg/optimize.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC lm32-softmmu/disas.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC nios2-softmmu/fpu/softfloat.o
CC lm32-softmmu/arch_init.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
make: *** [subdir-or1k-linux-user] Error 2
CC lm32-softmmu/cpus.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [subdir-mipsn32-linux-user] Error 2
CC ppc-softmmu/fpu/softfloat.o
CC ppc64-linux-user/fpu/softfloat.o
CC lm32-softmmu/monitor.o
CC sparc64-softmmu/tcg/tcg-op.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
CC sparc64-softmmu/tcg/tcg-op-vec.o
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC sparc64-softmmu/tcg/tcg-op-gvec.o
CC ppc64-linux-user/disas.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC ppc-softmmu/disas.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
cc1: all warnings being treated as errors
GEN ppc-softmmu/gdbstub-xml.c
make[1]: *** [tcg/tcg-op-vec.o] Error 1
CC sparc64-softmmu/tcg/tcg-common.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppcemb-softmmu/tcg/tcg-op-gvec.o
make: *** [subdir-sparc-linux-user] Error 2
CC ppc-softmmu/arch_init.o
CC sparc64-softmmu/tcg/optimize.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
CC ppcemb-softmmu/tcg/tcg-common.o
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppcemb-softmmu/tcg/optimize.o
CC sparc64-softmmu/fpu/softfloat.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC sparc64-softmmu/disas.o
CC ppc-softmmu/cpus.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC ppcemb-softmmu/fpu/softfloat.o
CC sparc64-softmmu/arch_init.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC sparc64-softmmu/cpus.o
CC ppc-softmmu/monitor.o
CC ppcemb-softmmu/disas.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppc-softmmu/gdbstub.o
GEN ppcemb-softmmu/gdbstub-xml.c
CC ppcemb-softmmu/arch_init.o
CC ppc-softmmu/balloon.o
CC ppcemb-softmmu/cpus.o
CC ppcemb-softmmu/monitor.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC sparc64-softmmu/monitor.o
CC ppc-softmmu/ioport.o
make: *** [subdir-mips64el-linux-user] Error 2
CC ppcemb-softmmu/gdbstub.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppcemb-softmmu/balloon.o
CC ppc-softmmu/numa.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC ppc-softmmu/qtest.o
CC sparc64-softmmu/gdbstub.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppcemb-softmmu/ioport.o
CC sparc64-softmmu/balloon.o
CC ppcemb-softmmu/numa.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC sparc64-softmmu/ioport.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
CC ppc-softmmu/memory.o
CC ppcemb-softmmu/qtest.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
CC ppc-softmmu/dump.o
CC ppc-softmmu/memory_mapping.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
CC ppc-softmmu/migration/ram.o
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c: In function ‘tcg_gen_gvec_2’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-gvec.c:533:9: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
CC ppc-softmmu/accel/accel.o
CC ppc-softmmu/accel/kvm/kvm-all.o
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-gvec.o] Error 1
make[1]: *** Waiting for unfinished jobs....
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c: In function ‘do_shifti’:
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: implicit declaration of function ‘tcg_can_emit_vec_op’ [-Werror=implicit-function-declaration]
can = tcg_can_emit_vec_op(opc, type, vece);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:402:5: error: nested extern declaration of ‘tcg_can_emit_vec_op’ [-Werror=nested-externs]
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: implicit declaration of function ‘tcg_expand_vec_op’ [-Werror=implicit-function-declaration]
tcg_expand_vec_op(opc, type, vece, ri, ai, i);
^
/var/tmp/patchew-tester-tmp-lmn4s2rx/src/tcg/tcg-op-vec.c:410:9: error: nested extern declaration of ‘tcg_expand_vec_op’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
make[1]: *** [tcg/tcg-op-vec.o] Error 1
make: *** [subdir-or1k-softmmu] Error 2
make: *** [subdir-microblaze-linux-user] Error 2
make: *** [subdir-nios2-linux-user] Error 2
make: *** [subdir-alpha-softmmu] Error 2
make: *** [subdir-xtensa-softmmu] Error 2
make: *** [subdir-sparc32plus-linux-user] Error 2
make: *** [subdir-mips64el-softmmu] Error 2
make: *** [subdir-mips-linux-user] Error 2
make: *** [subdir-cris-softmmu] Error 2
make: *** [subdir-mipsel-softmmu] Error 2
make: *** [subdir-ppc64le-linux-user] Error 2
make: *** [subdir-sh4-linux-user] Error 2
make: *** [subdir-sparc-softmmu] Error 2
make: *** [subdir-tricore-softmmu] Error 2
make: *** [subdir-x86_64-linux-user] Error 2
make: *** [subdir-arm-softmmu] Error 2
make: *** [subdir-microblazeel-softmmu] Error 2
make: *** [subdir-m68k-softmmu] Error 2
make: *** [subdir-s390x-softmmu] Error 2
make: *** [subdir-sh4eb-softmmu] Error 2
make: *** [subdir-ppc64-softmmu] Error 2
make: *** [subdir-i386-softmmu] Error 2
make: *** [subdir-mips64-softmmu] Error 2
make: *** [subdir-mips-softmmu] Error 2
make: *** [subdir-sparc64-softmmu] Error 2
make: *** [subdir-ppc64-linux-user] Error 2
make: *** [subdir-x86_64-softmmu] Error 2
make: *** [subdir-lm32-softmmu] Error 2
make: *** [subdir-ppc-softmmu] Error 2
make: *** [subdir-sh4-softmmu] Error 2
make: *** [subdir-ppcemb-softmmu] Error 2
make: *** [subdir-nios2-softmmu] Error 2
=== OUTPUT END ===
Test command exited with code: 2
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 36+ messages in thread* Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations
2017-11-21 21:25 [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Richard Henderson
` (29 preceding siblings ...)
2017-11-21 22:44 ` no-reply
@ 2017-11-27 16:09 ` Timothy Pearson
30 siblings, 0 replies; 36+ messages in thread
From: Timothy Pearson @ 2017-11-27 16:09 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Just as a note, I've been watching these series with great interest.
Once the changes settle down / are mergeable we will be looking to
implement vector <--> vector support between a couple of other
architectures.
Thanks for working on this!
On 11/21/2017 03:25 PM, Richard Henderson wrote:
> Quite a lot has changed since last time.
>
> The representation has changed such that the vector length and element
> size is stored in the TCGOp structure. The functions have changed such
> that the element size is passed explicitly rather than being encoded in
> the function name.
>
> I've added additional operations for multiply, immediate shifts, compares,
> element interleaves, and widening. I believe this is all we'll need for
> implementing ARM SVE, so I'll leave off for now.
>
> This has been tested vs aa64 risu on both x86_64 and aa64 hosts.
>
>
> r~
>
>
> Richard Henderson (26):
> tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*
> tcg: Dynamically allocate TCGOps
> tcg: Generalize TCGOp parameters
> tcg: Add types and basic operations for host vectors
> tcg: Add generic vector expanders
> tcg: Allow multiple word entries into the constant pool
> tcg: Add tcg_signed_cond
> target/arm: Align vector registers
> target/arm: Use vector infrastructure for aa64 add/sub/logic
> target/arm: Use vector infrastructure for aa64 mov/not/neg
> target/arm: Use vector infrastructure for aa64 dup/movi
> tcg/i386: Add vector operations
> tcg: Add tcg_expand_vec_op and tcg-target.opc.h
> tcg: Add generic vector ops for interleave
> target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn
> tcg: Add generic vector ops for constant shifts
> target/arm: Use vector infrastructure for aa64 constant shifts
> tcg: Add generic vector ops for comparisons
> target/arm: Use vector infrastructure for aa64 compares
> tcg/i386: Add vector operations/expansions for shift/cmp/interleave
> tcg: Add generic vector ops for multiplication
> target/arm: Use vector infrastructure for aa64 multiplies
> tcg: Add generic vector ops for extension
> target/arm: Use vector infrastructure for aa64 widening shifts
> tcg/i386: Add vector operations/expansions for mul/extend
> tcg/aarch64: Add vector operations
>
> Makefile.target | 4 +-
> accel/tcg/tcg-runtime.h | 102 +++
> include/exec/gen-icount.h | 9 +-
> include/qemu/queue.h | 5 +
> target/arm/cpu.h | 2 +-
> target/arm/translate.h | 10 +-
> tcg/aarch64/tcg-target.h | 30 +-
> tcg/aarch64/tcg-target.opc.h | 3 +
> tcg/i386/tcg-target.h | 46 +-
> tcg/i386/tcg-target.opc.h | 11 +
> tcg/tcg-gvec-desc.h | 49 +
> tcg/tcg-op-gvec.h | 219 +++++
> tcg/tcg-op.h | 55 +-
> tcg/tcg-opc.h | 59 ++
> tcg/tcg.h | 135 ++-
> accel/tcg/tcg-runtime-gvec.c | 616 +++++++++++++
> target/alpha/translate.c | 22 +-
> target/arm/translate-a64.c | 1135 ++++++++++++++++-------
> target/arm/translate.c | 31 +-
> target/cris/translate.c | 4 +-
> target/hppa/translate.c | 63 +-
> target/i386/translate.c | 13 +-
> target/lm32/translate.c | 2 -
> target/m68k/translate.c | 14 +-
> target/microblaze/translate.c | 4 -
> target/mips/translate.c | 2 +-
> target/nios2/translate.c | 6 +-
> target/ppc/translate.c | 2 +-
> target/s390x/translate.c | 42 +-
> target/sh4/translate.c | 2 +-
> target/sparc/translate.c | 2 +-
> target/tilegx/translate.c | 10 +-
> target/unicore32/translate.c | 4 +-
> tcg/aarch64/tcg-target.inc.c | 674 +++++++++++++-
> tcg/i386/tcg-target.inc.c | 1325 +++++++++++++++++++++++++--
> tcg/optimize.c | 20 +-
> tcg/tcg-op-gvec.c | 2010 +++++++++++++++++++++++++++++++++++++++++
> tcg/tcg-op-vec.c | 566 ++++++++++++
> tcg/tcg-op.c | 24 -
> tcg/tcg-pool.inc.c | 115 ++-
> tcg/tcg.c | 286 ++++--
> accel/tcg/Makefile.objs | 2 +-
> tcg/README | 148 +++
> 43 files changed, 7107 insertions(+), 776 deletions(-)
> create mode 100644 tcg/aarch64/tcg-target.opc.h
> create mode 100644 tcg/i386/tcg-target.opc.h
> create mode 100644 tcg/tcg-gvec-desc.h
> create mode 100644 tcg/tcg-op-gvec.h
> create mode 100644 accel/tcg/tcg-runtime-gvec.c
> create mode 100644 tcg/tcg-op-gvec.c
> create mode 100644 tcg/tcg-op-vec.c
>
--
Timothy Pearson
Raptor Engineering
+1 (415) 727-8645 (direct line)
+1 (512) 690-0200 (switchboard)
https://www.raptorengineering.com
^ permalink raw reply [flat|nested] 36+ messages in thread