From: Thomas Gleixner <tglx@linutronix.de>
To: Christoph Hellwig <hch@infradead.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver
Date: Mon, 10 Sep 2018 15:45:42 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.1809101544560.1292@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20180910133902.GB21593@infradead.org>
On Mon, 10 Sep 2018, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 03:37:31PM +0200, Thomas Gleixner wrote:
> > > > Just a few weeks ago you said the contrary:
> > > >
> > > > http://lists.infradead.org/pipermail/linux-riscv/2018-August/000943.html
> > >
> > > Sigh. Yes. Now that you remind me.
> >
> > Just for clarification. I had the impression that Anup was trying to wire
> > up more than just the timer interrupt, but that doesn't seem to be the
> > case.
>
> He has an irqchip that is called from the RISC-V exception handler
> when the interrupt flag is set in scause and then dispatches to one
> of: IPI, timer, actual irqchip.
So the per cpu timer is the only per cpu interrupt and that thing is used
unconditionally, right?
Thanks,
tglx
WARNING: multiple messages have this Message-ID (diff)
From: tglx@linutronix.de (Thomas Gleixner)
To: linux-riscv@lists.infradead.org
Subject: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver
Date: Mon, 10 Sep 2018 15:45:42 +0200 (CEST) [thread overview]
Message-ID: <alpine.DEB.2.21.1809101544560.1292@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20180910133902.GB21593@infradead.org>
On Mon, 10 Sep 2018, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 03:37:31PM +0200, Thomas Gleixner wrote:
> > > > Just a few weeks ago you said the contrary:
> > > >
> > > > http://lists.infradead.org/pipermail/linux-riscv/2018-August/000943.html
> > >
> > > Sigh. Yes. Now that you remind me.
> >
> > Just for clarification. I had the impression that Anup was trying to wire
> > up more than just the timer interrupt, but that doesn't seem to be the
> > case.
>
> He has an irqchip that is called from the RISC-V exception handler
> when the interrupt flag is set in scause and then dispatches to one
> of: IPI, timer, actual irqchip.
So the per cpu timer is the only per cpu interrupt and that thing is used
unconditionally, right?
Thanks,
tglx
next prev parent reply other threads:[~2018-09-10 13:45 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-06 12:36 [PATCH v2 0/5] New RISC-V Local Interrupt Controller Driver Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 1/5] RISC-V: self-contained IPI handling routine Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 2/5] RISC-V: No need to pass scause as arg to do_IRQ() Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 14:06 ` Christoph Hellwig
2018-09-06 14:06 ` Christoph Hellwig
2018-09-06 14:19 ` Anup Patel
2018-09-06 14:19 ` Anup Patel
2018-09-08 10:46 ` Thomas Gleixner
2018-09-08 10:46 ` Thomas Gleixner
2018-09-10 13:29 ` Christoph Hellwig
2018-09-10 13:29 ` Christoph Hellwig
2018-09-10 13:34 ` Thomas Gleixner
2018-09-10 13:34 ` Thomas Gleixner
2018-09-10 13:37 ` Thomas Gleixner
2018-09-10 13:37 ` Thomas Gleixner
2018-09-10 13:39 ` Christoph Hellwig
2018-09-10 13:39 ` Christoph Hellwig
2018-09-10 13:45 ` Thomas Gleixner [this message]
2018-09-10 13:45 ` Thomas Gleixner
2018-09-10 13:49 ` Christoph Hellwig
2018-09-10 13:49 ` Christoph Hellwig
2018-09-10 14:29 ` Anup Patel
2018-09-10 14:29 ` Anup Patel
2018-09-10 16:07 ` Thomas Gleixner
2018-09-10 16:07 ` Thomas Gleixner
2018-09-10 16:11 ` Christoph Hellwig
2018-09-10 16:11 ` Christoph Hellwig
2018-09-10 16:35 ` Anup Patel
2018-09-10 16:35 ` Anup Patel
2018-09-10 16:39 ` Christoph Hellwig
2018-09-10 16:39 ` Christoph Hellwig
2018-09-10 17:11 ` Anup Patel
2018-09-10 17:11 ` Anup Patel
2018-09-10 19:37 ` Thomas Gleixner
2018-09-10 19:37 ` Thomas Gleixner
2018-09-10 22:19 ` Christoph Hellwig
2018-09-10 22:19 ` Christoph Hellwig
2018-09-11 3:57 ` Anup Patel
2018-09-11 3:57 ` Anup Patel
2018-09-11 6:22 ` Christoph Hellwig
2018-09-11 6:22 ` Christoph Hellwig
2018-09-10 22:16 ` Christoph Hellwig
2018-09-10 22:16 ` Christoph Hellwig
2018-09-10 16:13 ` Christoph Hellwig
2018-09-10 16:13 ` Christoph Hellwig
2018-09-10 16:32 ` Anup Patel
2018-09-10 16:32 ` Anup Patel
2018-09-10 16:35 ` Christoph Hellwig
2018-09-10 16:35 ` Christoph Hellwig
2018-09-10 16:38 ` Anup Patel
2018-09-10 16:38 ` Anup Patel
2018-09-17 14:14 ` Christoph Hellwig
2018-09-17 14:14 ` Christoph Hellwig
2018-09-17 14:28 ` Anup Patel
2018-09-17 14:28 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-06 12:36 ` [PATCH v2 4/5] clocksource: riscv_timer: Make timer interrupt as a per-CPU interrupt Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 5/5] RISC-V: Remove do_IRQ() function Anup Patel
2018-09-06 12:36 ` Anup Patel
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