From: Paul Walmsley <paul.walmsley@sifive.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Yash Shah <yash.shah@sifive.com>,
linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org,
palmer@sifive.com, paul.walmsley@sifive.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, aou@eecs.berkeley.edu, mchehab@kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller
Date: Sun, 24 Mar 2019 17:16:17 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1903241705460.8028@viisi.sifive.com> (raw)
In-Reply-To: <20190312092842.GC28589@zn.tnic>
On Tue, 12 Mar 2019, Borislav Petkov wrote:
> Please no EDAC drivers for a single functional unit with RAS
> capabilities. Rather, a sifive_edac or riscv_edac driver which covers
> the whole platform or even architecture and contains support for all the
> RAS functionality there. See altera_edac, for example.
Looking at the Synopsys, Highbank, PowerPC 4xx, and TI EDAC drivers, all
of those are clearly for IP block error management, rather than platform
error management. Has the upstream guidance changed since those drivers
were merged?
The core issue for us is that we don't have a generalized "ECC management"
IP block. And I would just as soon not fake one in the DT data, since the
general DT guidance is that the data in DT is meant to describe the actual
hardware.
Would it make more sense to put this driver outside of drivers/edac?
- Paul
WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <paul.walmsley@sifive.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Yash Shah <yash.shah@sifive.com>,
linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org,
palmer@sifive.com, paul.walmsley@sifive.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, aou@eecs.berkeley.edu, mchehab@kernel.org,
devicetree@vger.kernel.org
Subject: [2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller
Date: Sun, 24 Mar 2019 17:16:17 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1903241705460.8028@viisi.sifive.com> (raw)
On Tue, 12 Mar 2019, Borislav Petkov wrote:
> Please no EDAC drivers for a single functional unit with RAS
> capabilities. Rather, a sifive_edac or riscv_edac driver which covers
> the whole platform or even architecture and contains support for all the
> RAS functionality there. See altera_edac, for example.
Looking at the Synopsys, Highbank, PowerPC 4xx, and TI EDAC drivers, all
of those are clearly for IP block error management, rather than platform
error management. Has the upstream guidance changed since those drivers
were merged?
The core issue for us is that we don't have a generalized "ECC management"
IP block. And I would just as soon not fake one in the DT data, since the
general DT guidance is that the data in DT is meant to describe the actual
hardware.
Would it make more sense to put this driver outside of drivers/edac?
- Paul
WARNING: multiple messages have this Message-ID (diff)
From: Paul Walmsley <paul.walmsley@sifive.com>
To: Borislav Petkov <bp@alien8.de>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
aou@eecs.berkeley.edu, palmer@sifive.com,
linux-kernel@vger.kernel.org, Yash Shah <yash.shah@sifive.com>,
robh+dt@kernel.org, paul.walmsley@sifive.com,
linux-riscv@lists.infradead.org, mchehab@kernel.org,
linux-edac@vger.kernel.org
Subject: Re: [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller
Date: Sun, 24 Mar 2019 17:16:17 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1903241705460.8028@viisi.sifive.com> (raw)
In-Reply-To: <20190312092842.GC28589@zn.tnic>
On Tue, 12 Mar 2019, Borislav Petkov wrote:
> Please no EDAC drivers for a single functional unit with RAS
> capabilities. Rather, a sifive_edac or riscv_edac driver which covers
> the whole platform or even architecture and contains support for all the
> RAS functionality there. See altera_edac, for example.
Looking at the Synopsys, Highbank, PowerPC 4xx, and TI EDAC drivers, all
of those are clearly for IP block error management, rather than platform
error management. Has the upstream guidance changed since those drivers
were merged?
The core issue for us is that we don't have a generalized "ECC management"
IP block. And I would just as soon not fake one in the DT data, since the
general DT guidance is that the data in DT is meant to describe the actual
hardware.
Would it make more sense to put this driver outside of drivers/edac?
- Paul
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next prev parent reply other threads:[~2019-03-25 0:16 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-12 9:20 [PATCH 0/2] L2 Cache EDAC Support for HiFive Unleashed Yash Shah
2019-03-12 9:20 ` Yash Shah
2019-03-12 9:20 ` Yash Shah
2019-03-12 9:21 ` [PATCH 1/2] edac: sifive: Add DT documentation for SiFive L2 cache Controller Yash Shah
2019-03-12 9:21 ` Yash Shah
2019-03-12 9:21 ` [1/2] " Yash Shah
2019-03-28 13:16 ` [PATCH 1/2] " Rob Herring
2019-03-28 13:16 ` Rob Herring
2019-03-28 13:16 ` [1/2] " Rob Herring
2019-03-28 18:47 ` [PATCH 1/2] " James Morse
2019-03-28 18:47 ` James Morse
2019-03-28 18:47 ` [1/2] " James Morse
2019-03-29 14:11 ` [PATCH 1/2] " Rob Herring
2019-03-29 14:11 ` Rob Herring
2019-03-29 14:11 ` [1/2] " Rob Herring
2019-03-29 14:27 ` [PATCH 1/2] " Borislav Petkov
2019-03-29 14:27 ` Borislav Petkov
2019-03-29 14:27 ` [1/2] " Borislav Petkov
2019-03-29 19:41 ` [PATCH 1/2] " Rob Herring
2019-03-29 19:41 ` Rob Herring
2019-03-29 19:41 ` [1/2] " Rob Herring
2019-03-29 20:24 ` [PATCH 1/2] " Borislav Petkov
2019-03-29 20:24 ` Borislav Petkov
2019-03-29 20:24 ` [1/2] " Borislav Petkov
2019-04-04 1:04 ` [PATCH 1/2] " Rob Herring
2019-04-04 1:04 ` Rob Herring
2019-04-04 1:04 ` [1/2] " Rob Herring
2019-04-01 16:36 ` [PATCH 1/2] " James Morse
2019-04-01 16:36 ` James Morse
2019-04-01 16:36 ` [1/2] " James Morse
2019-04-04 1:17 ` [PATCH 1/2] " Rob Herring
2019-04-04 1:17 ` Rob Herring
2019-04-04 1:17 ` [1/2] " Rob Herring
2019-03-12 9:21 ` [PATCH 2/2] sifive: edac: Add EDAC driver for Sifive l2 Cache Controller Yash Shah
2019-03-12 9:21 ` Yash Shah
2019-03-12 9:21 ` [2/2] " Yash Shah
2019-03-12 9:28 ` [PATCH 2/2] " Borislav Petkov
2019-03-12 9:28 ` Borislav Petkov
2019-03-12 9:28 ` [2/2] " Borislav Petkov
2019-03-25 0:16 ` Paul Walmsley [this message]
2019-03-25 0:16 ` [PATCH 2/2] " Paul Walmsley
2019-03-25 0:16 ` [2/2] " Paul Walmsley
2019-03-25 6:54 ` [PATCH 2/2] " Borislav Petkov
2019-03-25 6:54 ` Borislav Petkov
2019-03-25 6:54 ` [2/2] " Borislav Petkov
2019-03-25 21:18 ` [PATCH 2/2] " Paul Walmsley
2019-03-25 21:18 ` Paul Walmsley
2019-03-25 21:18 ` [2/2] " Paul Walmsley
2019-03-25 21:47 ` [PATCH 2/2] " Borislav Petkov
2019-03-25 21:47 ` Borislav Petkov
2019-03-25 21:47 ` [2/2] " Borislav Petkov
2019-03-12 16:31 ` [PATCH 2/2] " Paul Walmsley
2019-03-12 16:31 ` Paul Walmsley
2019-03-12 16:31 ` [2/2] " Paul Walmsley
2019-03-12 16:32 ` [PATCH 0/2] L2 Cache EDAC Support for HiFive Unleashed Paul Walmsley
2019-03-12 16:32 ` Paul Walmsley
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