[Qemu-devel] [PATCH 0/7] MIPS: IEEE 754-2008 features support

* [Qemu-devel] [PATCH 0/7] MIPS: IEEE 754-2008 features support
@ 2014-12-09  1:54 Maciej W. Rozycki
  2014-12-09  1:54 ` [Qemu-devel] [PATCH 1/7] softfloat: Fix sNaN handling in FP conversion operations Maciej W. Rozycki
                   ` (8 more replies)
  0 siblings, 9 replies; 43+ messages in thread
From: Maciej W. Rozycki @ 2014-12-09  1:54 UTC (permalink / raw)
  To: qemu-devel; +Cc: Leon Alrae, Thomas Schwinge, Aurelien Jarno

Hi,

 This patch series comprises changes to QEMU, both the MIPS backend and 
generic SoftFloat support code, to support IEEE 754-2008 features 
introduced to revision 3.50 of the MIPS Architecture as follows.

1. IEEE 754-2008 NaN encoding.

   As many of you have been aware it has been a long practice for software 
   using IEEE 754 floating-point arithmetic run on MIPS processors to use 
   an encoding of Not-a-Number (NaN) data different to one used by 
   software run on other processors.  And as of IEEE 754-2008 revision [1] 
   this encoding does not follow one recommended in the standard, as 
   specified in section 6.2.1, where it is stated that quiet NaNs should 
   have the first bit (d1) of their significand set to 1 while signalling 
   NaNs should have that bit set to 0, but MIPS software interprets the 
   two bits in the opposite manner.

   As from revision 3.50 [2][3] the MIPS Architecture provides for 
   processors that support the IEEE 754-2008 preferred NaN encoding 
   format. 

   A new ELF file header flag has been allocated to be set for 2008-NaN 
   binaries so that hardware can be configured accordingly by whatever 
   means are used to load the binary where support for both the 2008 and 
   legacy NaN encoding is present.  For hardware where only a single NaN 
   encoding is supported the flag can be used to reject incompatible 
   software.

2. IEEE 754-2008 non-arithmetic ABS and NEG instructions.

   As many of you have been aware MIPS ABS.fmt and NEG.fmt instructions 
   have not supported correct standard-compliant operation on a NaN 
   argument as the architecture has considered them arithmetic and 
   required to signal an Invalid Operation exception (that may or may not 
   be trapped; in the latter case a quiet NaN is produced).  As a result 
   in cases where standard compliance is required GCC has to emit longer 
   sequences to move the value given from the FPU to the CPU, use an 
   integer logical operation to adjust the sign bit manually, and then 
   move the result back to FPU.

   As from Sep 2012 the MIPS Architecture provides for processors that
   support the IEEE 754-2008 requirement that operations on bit strings, 
   that among others include ABS and NEG, are non-arithmetic and never 
   signal an exception.

 These features are addressed by this series as follows:

1. NaN data encodings.

   Handling is straightforward, although changes were tedious, spanning 
   many places in the MIPS backend and SoftFloat.  Data variables 
   providing NaN bit patterns are replaced with functions returning same 
   and then all functions and macros involved parametrised so as to select 
   the appropriate bit pattern according to the SoftFloat status state, 
   where a flag is added to select between the NaN formats where 
   applicable.  Credit goes to Thomas for making changes to SoftFloat in 
   self-contained incremental steps.

   The MIPS backend is then updated to handle the hardware side and 
   configure SoftFloat, just as with the other SoftFloat modes, according 
   to the FCSR NAN2008 bit.  This bit is preset according to the processor 
   definition used -- the architecture permits the bit to be either 
   read/write or read-only and, in the latter case, hardwired to 0 or 1 
   according to the interpretation implemented by a given processor.

2. ABS.fmt and NEG.fmt instructions.

   These were incorrectly already implemented as non-arithmetic.  No 
   existing MIPS processor provided this semantics until now, and not with 
   the FCSR ABS2008 bit set to 0.

   The old definitions therefore now serve the new semantics and new 
   implementations have been added to support the expected legacy 
   arithmetic treatment, according to the FCSR ABS2008 bit.  Again, this 
   bit is preset according to the processor definition used and can also 
   be read/write or read-only and if the latter, hardwired to 0 or 1.

 Both the implementation of the CTC1 instruction and the GDB stub have 
been updated to respect the properties of the new FCSR bits.

 I rigorously tested this set of changes by running full GCC, G++ and 
glibc mips-linux-gnu toolchain test suites under Linux (Debian Wheezy) run 
in QEMU in the system emulation mode, for the following multilibs:

-EB
-EB -mips16
-EB -mmicromips
-EB -mabi=n32
-EB -mabi=64

and the -EL variants of same.  Of these standard MIPS o32 testing was
run on a 24Kf processor and n64/n32 testing was run on a 5KEf processor,
using a 32-bit and a 64-bit kernel respectively.  MIPS16 o32 testing was
run on an artificial 5KEf-mips16 processor -- like a real 5KEf one, but
with the MIPS16 ASE enabled, and a 64-bit kernel.  Finally microMIPS o32
testing was run on an artificial 24Kf-micromips processor -- like a real
24Kf one, but with the microMIPS ASE enabled, and a 32-bit kernel built
as microMIPS code itself.  This covered the legacy NaN mode only and 
assured no regression has been introduced by these changes.

 I also rigorously tested this set of changes by running full GCC, G++ and 
glibc mips-linux-gnu toolchain test suites under QEMU in the Linux user 
emulation mode, for the following multilibs:

-EB
-EB -mips16
-EB -mmicromips
-EB -mabi=n32
-EB -mabi=64

-EB -mnan=2008
-EB -mnan=2008 -mips16
-EB -mnan=2008 -mmicromips
-EB -mnan=2008 -mabi=n32
-EB -mnan=2008 -mabi=64

-EB -msoft-float
-EB -msoft-float -mips16
-EB -msoft-float -mmicromips
-EB -msoft-float -mabi=n32
-EB -msoft-float -mabi=64

and the -EL variants of same.  Of those standard MIPS and MIPS16 o32 
testing was run on an artificial 24Kf-nan2008 processor -- like a real 
24Kf one, but with FCSR NAN2008 and ABS2008 bits writable.  Then microMIPS 
o32 testing was run on an artificial 24Kf-micromips-nan2008 processor -- 
like a real 24Kf one, but with the microMIPS ASE enabled and FCSR NAN2008 
and ABS2008 bits writable.  Finally n64/n32 testing was run on a 
5KEf-nan2008 processor -- like a real 5KEf, but with FCSR NAN2008 and 
ABS2008 bits writable.  Soft-float testing was run for a reference to 
ensure no critical errors were observed in hardware floating-point support 
compared to the same code built to use integer support only.

 Besides usual intermittent fluctuations in test results no problems have 
been spotted.  NB the user emulation mode is particularly problematic with 
the glibc test suite.

 Credit goes to Thomas for most of the SoftFloat changes, except from 1/7 
that I wrote from scratch based on his earlier MIPS-only implementation.  
With 2/7 through 6/7 I only ported the original changes to make them apply 
against and work with current trunk, including though not limited to new 
targets such as AArch64 and code such as MIPS MSA support added to QEMU 
since.  In 7/7 I did all the changes related to hardware and Thomas did 
the bits to configure SoftFloat.

 References:

[1] "IEEE Standard for Floating-Point Arithmetic", IEEE Computer 
    Society, IEEE Std 754-2008, 29 August 2008

[2] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
    MIPS32 Architecture", MIPS Technologies, Inc., Document Number:
    MD00082, Revision 3.50, September 20, 2012

[3] "MIPS Architecture For Programmers, Volume I-A: Introduction to the
    MIPS64 Architecture", MIPS Technologies, Inc., Document Number:
    MD00083, Revision 3.50, September 20, 2012

  Maciej

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