Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA

["Maciej W. Rozycki" <macro@linux-mips.org>]

On Wed, 13 May 2015, Leon Alrae wrote:

> > Certainly we do.  It's all in softmmu_template.h.
> 
> I believe the problem is that MSA vector register's size is 16-bytes
> (this DATA_SIZE isn't supported in softmmu_template) and MSA load/store
> is supposed to be atomic.

 Not really AFAICT.  Here's what the specification says[1]:

"The vector load instruction is atomic at the element level with no 
guaranteed ordering among elements, i.e. each element load is an atomic 
operation issued in no particular order with respect to the element's 
vector position."

and[2]:

"The vector store instruction is atomic at the element level with no 
guaranteed ordering among elements, i.e. each element store is an atomic 
operation issued in no particular order with respect to the element's 
vector position."

so you only need to get atomic up to 8 bytes (with LD.D and ST.D, less 
with the narrower vector elements), and that looks supported to me.

References:

[1] "MIPS Architecture for Programmers, Volume IV-j: The MIPS32 SIMD 
    Architecture Module", Revision 1.07, MIPS Technologies, Inc., 
    Document Number: MD00866, October 2, 2013, p. 314

[2] same, p. 414

  Maciej