* [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC
@ 2017-06-09 12:28 Kever Yang
2017-06-09 12:28 ` [U-Boot] [PATCH 1/7] rockchip: mkimage: add support for rk322x soc Kever Yang
` (6 more replies)
0 siblings, 7 replies; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
RK3229 is a Quad-core Cortex-A7 SoC, which supports:
- 4K 10bit H.264/H.265,VP9.
- 32KB internal memory;
- eMMC 4.5.1, SD3.0;
- DDR3, LPDDR2, LPDDR3;
- HDMI 2.0 output, 4K at 60Hz;
- USB2.0 OTG and USB2.0 host;
Kever Yang (7):
rockchip: mkimage: add support for rk322x soc
rockchip: rk322x: add clock driver
rockchip: rk322x: add pinctrl driver
rockchip: rk322x: add dts file
rockchip: rk322x: add basic soc support
rockchip: rk322x: add sysreset driver
rockchip: add evb_rk3229 board
arch/arm/dts/rk3229-evb.dts | 77 +++
arch/arm/dts/rk322x.dtsi | 710 ++++++++++++++++++++++++
arch/arm/include/asm/arch-rockchip/clock.h | 1 +
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 +++++++
arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 519 +++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 14 +
arch/arm/mach-rockchip/Makefile | 3 +
arch/arm/mach-rockchip/rk322x-board-spl.c | 77 +++
arch/arm/mach-rockchip/rk322x-board.c | 159 ++++++
arch/arm/mach-rockchip/rk322x/Kconfig | 18 +
arch/arm/mach-rockchip/rk322x/Makefile | 9 +
arch/arm/mach-rockchip/rk322x/clk_rk322x.c | 33 ++
arch/arm/mach-rockchip/rk322x/syscon_rk322x.c | 22 +
board/rockchip/evb_rk3229/Kconfig | 15 +
board/rockchip/evb_rk3229/MAINTAINERS | 6 +
board/rockchip/evb_rk3229/Makefile | 7 +
board/rockchip/evb_rk3229/evb_rk3229.c | 12 +
configs/evb-rk3229_defconfig | 44 ++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk322x.c | 413 ++++++++++++++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 295 ++++++++++
drivers/sysreset/sysreset_rk322x.c | 45 ++
include/configs/evb_rk3229.h | 60 ++
include/configs/rk322x_common.h | 92 +++
include/dt-bindings/clock/rk3228-cru.h | 247 +++++++++
tools/rkcommon.c | 1 +
28 files changed, 3106 insertions(+)
create mode 100644 arch/arm/dts/rk3229-evb.dts
create mode 100644 arch/arm/dts/rk322x.dtsi
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk322x.h
create mode 100644 arch/arm/mach-rockchip/rk322x-board-spl.c
create mode 100644 arch/arm/mach-rockchip/rk322x-board.c
create mode 100644 arch/arm/mach-rockchip/rk322x/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk322x/Makefile
create mode 100644 arch/arm/mach-rockchip/rk322x/clk_rk322x.c
create mode 100644 arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
create mode 100644 board/rockchip/evb_rk3229/Kconfig
create mode 100644 board/rockchip/evb_rk3229/MAINTAINERS
create mode 100644 board/rockchip/evb_rk3229/Makefile
create mode 100644 board/rockchip/evb_rk3229/evb_rk3229.c
create mode 100644 configs/evb-rk3229_defconfig
create mode 100644 drivers/clk/rockchip/clk_rk322x.c
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c
create mode 100644 drivers/sysreset/sysreset_rk322x.c
create mode 100644 include/configs/evb_rk3229.h
create mode 100644 include/configs/rk322x_common.h
create mode 100644 include/dt-bindings/clock/rk3228-cru.h
--
1.9.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 1/7] rockchip: mkimage: add support for rk322x soc
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
@ 2017-06-09 12:28 ` Kever Yang
2017-06-12 10:52 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 2/7] rockchip: rk322x: add clock driver Kever Yang
` (5 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
Add support for rk322x package header in mkimage tool.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index fd95abc..6e9595f 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -74,6 +74,7 @@ struct spl_info {
static struct spl_info spl_infos[] = {
{ "rk3036", "RK30", 0x1000, false, false },
{ "rk3188", "RK31", 0x8000 - 0x800, true, false },
+ { "rk322x", "RK32", 0x8000 - 0x1000, false, false },
{ "rk3288", "RK32", 0x8000, false, false },
{ "rk3328", "RK32", 0x8000 - 0x1000, false, false },
{ "rk3399", "RK33", 0x20000, false, true },
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 2/7] rockchip: rk322x: add clock driver
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
2017-06-09 12:28 ` [U-Boot] [PATCH 1/7] rockchip: mkimage: add support for rk322x soc Kever Yang
@ 2017-06-09 12:28 ` Kever Yang
2017-06-12 11:00 ` [U-Boot] [U-Boot,2/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 3/7] rockchip: rk322x: add pinctrl driver Kever Yang
` (4 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
Add clock driver init support for:
- cpu, bus clock init;
- emmc, sdmmc clock;
- ddr clock;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk322x.c | 413 ++++++++++++++++++++++++
3 files changed, 629 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h
create mode 100644 drivers/clk/rockchip/clk_rk322x.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
new file mode 100644
index 0000000..0a01f87
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK322X_H
+#define _ASM_ARCH_CRU_RK322X_H
+
+#include <common.h>
+
+#define MHz 1000000
+#define OSC_HZ (24 * MHz)
+
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (594 * MHz)
+
+#define CORE_PERI_HZ 150000000
+#define CORE_ACLK_HZ 300000000
+
+#define BUS_ACLK_HZ 148500000
+#define BUS_HCLK_HZ 148500000
+#define BUS_PCLK_HZ 74250000
+
+#define PERI_ACLK_HZ 148500000
+#define PERI_HCLK_HZ 148500000
+#define PERI_PCLK_HZ 74250000
+
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk322x_clk_priv {
+ struct rk322x_cru *cru;
+ ulong rate;
+};
+
+struct rk322x_cru {
+ struct rk322x_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ } pll[4];
+ unsigned int reserved0[4];
+ unsigned int cru_mode_con;
+ unsigned int cru_clksel_con[35];
+ unsigned int cru_clkgate_con[16];
+ unsigned int cru_softrst_con[9];
+ unsigned int cru_misc_con;
+ unsigned int reserved1[2];
+ unsigned int cru_glb_cnt_th;
+ unsigned int reserved2[3];
+ unsigned int cru_glb_rst_st;
+ unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
+ unsigned int cru_sdmmc_con[2];
+ unsigned int cru_sdio_con[2];
+ unsigned int reserved4[2];
+ unsigned int cru_emmc_con[2];
+ unsigned int reserved5[4];
+ unsigned int cru_glb_srst_fst_value;
+ unsigned int cru_glb_srst_snd_value;
+ unsigned int cru_pll_mask_con;
+};
+check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
+
+struct pll_div {
+ u32 refdiv;
+ u32 fbdiv;
+ u32 postdiv1;
+ u32 postdiv2;
+ u32 frac;
+};
+
+enum {
+ /* PLLCON0*/
+ PLL_BP_SHIFT = 15,
+ PLL_POSTDIV1_SHIFT = 12,
+ PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
+ PLL_FBDIV_SHIFT = 0,
+ PLL_FBDIV_MASK = 0xfff,
+
+ /* PLLCON1 */
+ PLL_RST_SHIFT = 14,
+ PLL_PD_SHIFT = 13,
+ PLL_PD_MASK = 1 << PLL_PD_SHIFT,
+ PLL_DSMPD_SHIFT = 12,
+ PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
+ PLL_LOCK_STATUS_SHIFT = 10,
+ PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
+ PLL_POSTDIV2_SHIFT = 6,
+ PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
+ PLL_REFDIV_SHIFT = 0,
+ PLL_REFDIV_MASK = 0x3f,
+
+ /* CRU_MODE */
+ GPLL_MODE_SHIFT = 12,
+ GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT,
+ GPLL_MODE_SLOW = 0,
+ GPLL_MODE_NORM,
+ CPLL_MODE_SHIFT = 8,
+ CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
+ CPLL_MODE_SLOW = 0,
+ CPLL_MODE_NORM,
+ DPLL_MODE_SHIFT = 4,
+ DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
+ DPLL_MODE_SLOW = 0,
+ DPLL_MODE_NORM,
+ APLL_MODE_SHIFT = 0,
+ APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
+ APLL_MODE_SLOW = 0,
+ APLL_MODE_NORM,
+
+ /* CRU_CLK_SEL0_CON */
+ BUS_ACLK_PLL_SEL_SHIFT = 13,
+ BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
+ BUS_ACLK_PLL_SEL_APLL = 0,
+ BUS_ACLK_PLL_SEL_GPLL,
+ BUS_ACLK_PLL_SEL_HDMIPLL,
+ BUS_ACLK_DIV_SHIFT = 8,
+ BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
+ CORE_CLK_PLL_SEL_SHIFT = 6,
+ CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT,
+ CORE_CLK_PLL_SEL_APLL = 0,
+ CORE_CLK_PLL_SEL_GPLL,
+ CORE_CLK_PLL_SEL_DPLL,
+ CORE_DIV_CON_SHIFT = 0,
+ CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
+
+ /* CRU_CLK_SEL1_CON */
+ BUS_PCLK_DIV_SHIFT = 12,
+ BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
+ BUS_HCLK_DIV_SHIFT = 8,
+ BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
+ CORE_ACLK_DIV_SHIFT = 4,
+ CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
+ CORE_PERI_DIV_SHIFT = 0,
+ CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
+
+ /* CRU_CLKSEL5_CON */
+ GMAC_OUT_PLL_SHIFT = 15,
+ GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT,
+ GMAC_OUT_DIV_SHIFT = 8,
+ GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT,
+ MAC_PLL_SEL_SHIFT = 7,
+ MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
+ RMII_EXTCLK_SLE_SHIFT = 5,
+ RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT,
+ RMII_EXTCLK_SEL_INT = 0,
+ RMII_EXTCLK_SEL_EXT,
+ CLK_MAC_DIV_SHIFT = 0,
+ CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT,
+
+ /* CRU_CLKSEL10_CON */
+ PERI_PCLK_DIV_SHIFT = 12,
+ PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT,
+ PERI_PLL_SEL_SHIFT = 10,
+ PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
+ PERI_PLL_CPLL = 0,
+ PERI_PLL_GPLL,
+ PERI_PLL_HDMIPLL,
+ PERI_HCLK_DIV_SHIFT = 8,
+ PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
+ PERI_ACLK_DIV_SHIFT = 0,
+ PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
+
+ /* CRU_CLKSEL11_CON */
+ EMMC_PLL_SHIFT = 12,
+ EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
+ EMMC_SEL_APLL = 0,
+ EMMC_SEL_DPLL,
+ EMMC_SEL_GPLL,
+ EMMC_SEL_24M,
+ SDIO_PLL_SHIFT = 10,
+ SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
+ SDIO_SEL_APLL = 0,
+ SDIO_SEL_DPLL,
+ SDIO_SEL_GPLL,
+ SDIO_SEL_24M,
+ MMC0_PLL_SHIFT = 8,
+ MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
+ MMC0_SEL_APLL = 0,
+ MMC0_SEL_DPLL,
+ MMC0_SEL_GPLL,
+ MMC0_SEL_24M,
+ MMC0_DIV_SHIFT = 0,
+ MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT,
+
+ /* CRU_CLKSEL12_CON */
+ EMMC_DIV_SHIFT = 8,
+ EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
+ SDIO_DIV_SHIFT = 0,
+ SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT,
+
+ /* CRU_CLKSEL26_CON */
+ DDR_CLK_PLL_SEL_SHIFT = 8,
+ DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT,
+ DDR_CLK_SEL_DPLL = 0,
+ DDR_CLK_SEL_GPLL,
+ DDR_CLK_SEL_APLL,
+ DDR_DIV_SEL_SHIFT = 0,
+ DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
+
+ /* CRU_CLKSEL27_CON */
+ VOP_DCLK_DIV_SHIFT = 8,
+ VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT,
+ VOP_PLL_SEL_SHIFT = 1,
+ VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT,
+
+ /* CRU_CLKSEL29_CON */
+ GMAC_CLK_SRC_SHIFT = 12,
+ GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
+
+ /* CRU_SOFTRST5_CON */
+ DDRCTRL_PSRST_SHIFT = 11,
+ DDRCTRL_SRST_SHIFT = 10,
+ DDRPHY_PSRST_SHIFT = 9,
+ DDRPHY_SRST_SHIFT = 8,
+};
+#endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index e404c0c..c50aff2 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
+obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
new file mode 100644
index 0000000..582ef88
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk322x.c
@@ -0,0 +1,413 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk322x.h>
+#include <asm/arch/hardware.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3228-cru.h>
+#include <linux/log2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+ VCO_MAX_HZ = 3200U * 1000000,
+ VCO_MIN_HZ = 800 * 1000000,
+ OUTPUT_MAX_HZ = 3200U * 1000000,
+ OUTPUT_MIN_HZ = 24 * 1000000,
+};
+
+#define RATE_TO_DIV(input_rate, output_rate) \
+ ((input_rate) / (output_rate) - 1);
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
+ .refdiv = _refdiv,\
+ .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
+ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
+ _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
+ OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
+ #hz "Hz cannot be hit with PLL "\
+ "divisors on line " __stringify(__LINE__));
+
+/* use interge mode*/
+static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
+static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
+
+static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
+ const struct pll_div *div)
+{
+ int pll_id = rk_pll_id(clk_id);
+ struct rk322x_pll *pll = &cru->pll[pll_id];
+
+ /* All PLLs have same VCO and output frequency range restrictions. */
+ uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
+ uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
+
+ debug("PLL at %x: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
+ pll, div->fbdiv, div->refdiv, div->postdiv1,
+ div->postdiv2, vco_hz, output_hz);
+ assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
+ output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
+
+ /* use interger mode */
+ rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
+ /* Power down */
+ rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+ rk_clrsetreg(&pll->con0,
+ PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
+ (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
+ rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+ (div->postdiv2 << PLL_POSTDIV2_SHIFT |
+ div->refdiv << PLL_REFDIV_SHIFT));
+
+ /* Power Up */
+ rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
+
+ /* waiting for pll lock */
+ while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
+ udelay(1);
+
+ return 0;
+}
+
+static void rkclk_init(struct rk322x_cru *cru)
+{
+ u32 aclk_div;
+ u32 hclk_div;
+ u32 pclk_div;
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK | APLL_MODE_MASK,
+ GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
+ APLL_MODE_SLOW << APLL_MODE_SHIFT);
+
+ /* init pll */
+ rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
+ rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
+
+ /*
+ * select apll as cpu/core clock pll source and
+ * set up dependent divisors for PERI and ACLK clocks.
+ * core hz : apll = 1:1
+ */
+ aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
+ assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
+
+ pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
+ assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
+ CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
+ 0 << CORE_DIV_CON_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
+ aclk_div << CORE_ACLK_DIV_SHIFT |
+ pclk_div << CORE_PERI_DIV_SHIFT);
+
+ /*
+ * select apll as pd_bus bus clock source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
+ assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
+
+ pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
+ assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
+
+ hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
+ assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
+
+ rk_clrsetreg(&cru->cru_clksel_con[0],
+ BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
+ BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
+ aclk_div << BUS_ACLK_DIV_SHIFT);
+
+ rk_clrsetreg(&cru->cru_clksel_con[1],
+ BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
+ pclk_div << BUS_PCLK_DIV_SHIFT |
+ hclk_div << BUS_HCLK_DIV_SHIFT);
+
+ /*
+ * select gpll as pd_peri bus clock source and
+ * set up dependent divisors for PCLK/HCLK and ACLK clocks.
+ */
+ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
+ assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
+
+ hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
+ assert((1 << hclk_div) * PERI_HCLK_HZ ==
+ PERI_ACLK_HZ && (hclk_div < 0x4));
+
+ pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
+ assert((1 << pclk_div) * PERI_PCLK_HZ ==
+ PERI_ACLK_HZ && pclk_div < 0x8);
+
+ rk_clrsetreg(&cru->cru_clksel_con[10],
+ PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
+ PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
+ PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
+ pclk_div << PERI_PCLK_DIV_SHIFT |
+ hclk_div << PERI_HCLK_DIV_SHIFT |
+ aclk_div << PERI_ACLK_DIV_SHIFT);
+
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con,
+ GPLL_MODE_MASK | APLL_MODE_MASK,
+ GPLL_MODE_NORM << GPLL_MODE_SHIFT |
+ APLL_MODE_NORM << APLL_MODE_SHIFT);
+}
+
+/* Get pll rate by id */
+static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
+ enum rk_clk_id clk_id)
+{
+ uint32_t refdiv, fbdiv, postdiv1, postdiv2;
+ uint32_t con;
+ int pll_id = rk_pll_id(clk_id);
+ struct rk322x_pll *pll = &cru->pll[pll_id];
+ static u8 clk_shift[CLK_COUNT] = {
+ 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
+ GPLL_MODE_SHIFT, 0xff
+ };
+ static u32 clk_mask[CLK_COUNT] = {
+ 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
+ GPLL_MODE_MASK, 0xff
+ };
+ uint shift;
+ uint mask;
+
+ con = readl(&cru->cru_mode_con);
+ shift = clk_shift[clk_id];
+ mask = clk_mask[clk_id];
+
+ switch ((con & mask) >> shift) {
+ case GPLL_MODE_SLOW:
+ return OSC_HZ;
+ case GPLL_MODE_NORM:
+
+ /* normal mode */
+ con = readl(&pll->con0);
+ postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
+ fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
+ con = readl(&pll->con1);
+ postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
+ refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
+ return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
+ default:
+ return 32768;
+ }
+}
+
+static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
+ int periph)
+{
+ uint src_rate;
+ uint div, mux;
+ u32 con;
+
+ switch (periph) {
+ case HCLK_EMMC:
+ case SCLK_EMMC:
+ con = readl(&cru->cru_clksel_con[11]);
+ mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
+ con = readl(&cru->cru_clksel_con[12]);
+ div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
+ break;
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ con = readl(&cru->cru_clksel_con[11]);
+ mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
+ div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
+ return DIV_TO_RATE(src_rate, div);
+}
+
+static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
+ int periph, uint freq)
+{
+ int src_clk_div;
+ int mux;
+
+ debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
+
+ /* mmc clock auto divide 2 in internal */
+ src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
+
+ if (src_clk_div > 0x7f) {
+ src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
+ mux = EMMC_SEL_24M;
+ } else {
+ mux = EMMC_SEL_GPLL;
+ }
+
+ switch (periph) {
+ case HCLK_EMMC:
+ case SCLK_EMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[11],
+ EMMC_PLL_MASK,
+ mux << EMMC_PLL_SHIFT);
+ rk_clrsetreg(&cru->cru_clksel_con[12],
+ EMMC_DIV_MASK,
+ (src_clk_div - 1) << EMMC_DIV_SHIFT);
+ break;
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ rk_clrsetreg(&cru->cru_clksel_con[11],
+ MMC0_PLL_MASK | MMC0_DIV_MASK,
+ mux << MMC0_PLL_SHIFT |
+ (src_clk_div - 1) << MMC0_DIV_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
+}
+
+static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
+{
+ struct pll_div dpll_cfg;
+
+ /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
+ switch (set_rate) {
+ case 400*MHz:
+ dpll_cfg = (struct pll_div)
+ {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+ break;
+ case 600*MHz:
+ dpll_cfg = (struct pll_div)
+ {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
+ break;
+ case 800*MHz:
+ dpll_cfg = (struct pll_div)
+ {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
+ break;
+ }
+
+ /* pll enter slow-mode */
+ rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+ DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
+ rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
+ /* PLL enter normal-mode */
+ rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
+ DPLL_MODE_NORM << DPLL_MODE_SHIFT);
+
+ return set_rate;
+}
+static ulong rk322x_clk_get_rate(struct clk *clk)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate, gclk_rate;
+
+ gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+ switch (clk->id) {
+ case 0 ... 63:
+ rate = rkclk_pll_get_rate(priv->cru, clk->id);
+ break;
+ case HCLK_EMMC:
+ case SCLK_EMMC:
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong new_rate, gclk_rate;
+
+ gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
+ switch (clk->id) {
+ case HCLK_EMMC:
+ case SCLK_EMMC:
+ case HCLK_SDMMC:
+ case SCLK_SDMMC:
+ new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
+ clk->id, rate);
+ break;
+ case CLK_DDR:
+ new_rate = rk322x_ddr_set_clk(priv->cru, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return new_rate;
+}
+
+static struct clk_ops rk322x_clk_ops = {
+ .get_rate = rk322x_clk_get_rate,
+ .set_rate = rk322x_clk_set_rate,
+};
+
+static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
+
+ return 0;
+}
+
+static int rk322x_clk_probe(struct udevice *dev)
+{
+ struct rk322x_clk_priv *priv = dev_get_priv(dev);
+
+ rkclk_init(priv->cru);
+
+ return 0;
+}
+
+static int rk322x_clk_bind(struct udevice *dev)
+{
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
+ if (ret)
+ debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
+
+ return 0;
+}
+
+static const struct udevice_id rk322x_clk_ids[] = {
+ { .compatible = "rockchip,rk3228-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk322x_cru) = {
+ .name = "clk_rk322x",
+ .id = UCLASS_CLK,
+ .of_match = rk322x_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
+ .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
+ .ops = &rk322x_clk_ops,
+ .bind = rk322x_clk_bind,
+ .probe = rk322x_clk_probe,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 3/7] rockchip: rk322x: add pinctrl driver
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
2017-06-09 12:28 ` [U-Boot] [PATCH 1/7] rockchip: mkimage: add support for rk322x soc Kever Yang
2017-06-09 12:28 ` [U-Boot] [PATCH 2/7] rockchip: rk322x: add clock driver Kever Yang
@ 2017-06-09 12:28 ` Kever Yang
2017-06-12 14:18 ` [U-Boot] [U-Boot,3/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 4/7] rockchip: rk322x: add dts file Kever Yang
` (3 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
Add init pinctrl driver support for:
- i2c;
- spi;
- uart;
- pwm;
- emmc/sdmmc;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 519 ++++++++++++++++++++++++
drivers/pinctrl/Kconfig | 10 +
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl_rk322x.c | 295 ++++++++++++++
4 files changed, 825 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk322x.h
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
new file mode 100644
index 0000000..26071c8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
@@ -0,0 +1,519 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK322X_H
+#define _ASM_ARCH_GRF_RK322X_H
+
+#include <common.h>
+
+struct rk322x_grf {
+ unsigned int gpio0a_iomux;
+ unsigned int gpio0b_iomux;
+ unsigned int gpio0c_iomux;
+ unsigned int gpio0d_iomux;
+
+ unsigned int gpio1a_iomux;
+ unsigned int gpio1b_iomux;
+ unsigned int gpio1c_iomux;
+ unsigned int gpio1d_iomux;
+
+ unsigned int gpio2a_iomux;
+ unsigned int gpio2b_iomux;
+ unsigned int gpio2c_iomux;
+ unsigned int gpio2d_iomux;
+
+ unsigned int gpio3a_iomux;
+ unsigned int gpio3b_iomux;
+ unsigned int gpio3c_iomux;
+ unsigned int gpio3d_iomux;
+
+ unsigned int reserved1[4];
+ unsigned int con_iomux;
+ unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
+ unsigned int gpio0_p[4];
+ unsigned int gpio1_p[4];
+ unsigned int gpio2_p[4];
+ unsigned int gpio3_p[4];
+ unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
+ unsigned int gpio0_e[4];
+ unsigned int gpio1_e[4];
+ unsigned int gpio2_e[4];
+ unsigned int gpio3_e[4];
+ unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
+ unsigned int soc_con[7];
+ unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
+ unsigned int soc_status[3];
+ unsigned int chip_id;
+ unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
+ unsigned int cpu_con[4];
+ unsigned int reserved7[4];
+ unsigned int cpu_status[2];
+ unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
+ unsigned int os_reg[8];
+ unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
+ unsigned int ddrc_stat;
+};
+check_member(rk322x_grf, ddrc_stat, 0x604);
+
+struct rk322x_sgrf {
+ unsigned int soc_con[11];
+ unsigned int busdmac_con[4];
+};
+
+/* GRF_GPIO0A_IOMUX */
+enum {
+ GPIO0A7_SHIFT = 14,
+ GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
+ GPIO0A7_GPIO = 0,
+ GPIO0A7_I2C3_SDA,
+ GPIO0A7_HDMI_DDCSDA,
+
+ GPIO0A6_SHIFT = 12,
+ GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
+ GPIO0A6_GPIO = 0,
+ GPIO0A6_I2C3_SCL,
+ GPIO0A6_HDMI_DDCSCL,
+
+ GPIO0A3_SHIFT = 6,
+ GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
+ GPIO0A3_GPIO = 0,
+ GPIO0A3_I2C1_SDA,
+ GPIO0A3_SDIO_CMD,
+
+ GPIO0A2_SHIFT = 4,
+ GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
+ GPIO0A2_GPIO = 0,
+ GPIO0A2_I2C1_SCL,
+
+ GPIO0A1_SHIFT = 2,
+ GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
+ GPIO0A1_GPIO = 0,
+ GPIO0A1_I2C0_SDA,
+
+ GPIO0A0_SHIFT = 0,
+ GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
+ GPIO0A0_GPIO = 0,
+ GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+ GPIO0B7_SHIFT = 14,
+ GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
+ GPIO0B7_GPIO = 0,
+ GPIO0B7_HDMI_HDP,
+
+ GPIO0B6_SHIFT = 12,
+ GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
+ GPIO0B6_GPIO = 0,
+ GPIO0B6_I2S_SDI,
+ GPIO0B6_SPI_CSN0,
+
+ GPIO0B5_SHIFT = 10,
+ GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
+ GPIO0B5_GPIO = 0,
+ GPIO0B5_I2S_SDO,
+ GPIO0B5_SPI_RXD,
+
+ GPIO0B3_SHIFT = 6,
+ GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
+ GPIO0B3_GPIO = 0,
+ GPIO0B3_I2S1_LRCKRX,
+ GPIO0B3_SPI_TXD,
+
+ GPIO0B1_SHIFT = 2,
+ GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
+ GPIO0B1_GPIO = 0,
+ GPIO0B1_I2S_SCLK,
+ GPIO0B1_SPI_CLK,
+
+ GPIO0B0_SHIFT = 0,
+ GPIO0B0_MASK = 3,
+ GPIO0B0_GPIO = 0,
+ GPIO0B0_I2S_MCLK,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+ GPIO0C4_SHIFT = 8,
+ GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
+ GPIO0C4_GPIO = 0,
+ GPIO0C4_HDMI_CECSDA,
+
+ GPIO0C1_SHIFT = 2,
+ GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
+ GPIO0C1_GPIO = 0,
+ GPIO0C1_UART0_RSTN,
+ GPIO0C1_CLK_OUT1,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+ GPIO0D6_SHIFT = 12,
+ GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
+ GPIO0D6_GPIO = 0,
+ GPIO0D6_SDIO_PWREN,
+ GPIO0D6_PWM11,
+
+
+ GPIO0D4_SHIFT = 8,
+ GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
+ GPIO0D4_GPIO = 0,
+ GPIO0D4_PWM2,
+
+ GPIO0D3_SHIFT = 6,
+ GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
+ GPIO0D3_GPIO = 0,
+ GPIO0D3_PWM1,
+
+ GPIO0D2_SHIFT = 4,
+ GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
+ GPIO0D2_GPIO = 0,
+ GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+ GPIO1A7_SHIFT = 14,
+ GPIO1A7_MASK = 1,
+ GPIO1A7_GPIO = 0,
+ GPIO1A7_SDMMC_WRPRT,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+ GPIO1B7_SHIFT = 14,
+ GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
+ GPIO1B7_GPIO = 0,
+ GPIO1B7_SDMMC_CMD,
+
+ GPIO1B6_SHIFT = 12,
+ GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
+ GPIO1B6_GPIO = 0,
+ GPIO1B6_SDMMC_PWREN,
+
+ GPIO1B4_SHIFT = 8,
+ GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
+ GPIO1B4_GPIO = 0,
+ GPIO1B4_SPI_CSN1,
+ GPIO1B4_PWM12,
+
+ GPIO1B3_SHIFT = 6,
+ GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
+ GPIO1B3_GPIO = 0,
+ GPIO1B3_UART1_RSTN,
+ GPIO1B3_PWM13,
+
+ GPIO1B2_SHIFT = 4,
+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
+ GPIO1B2_GPIO = 0,
+ GPIO1B2_UART1_SIN,
+ GPIO1B2_UART21_SIN,
+
+ GPIO1B1_SHIFT = 2,
+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
+ GPIO1B1_GPIO = 0,
+ GPIO1B1_UART1_SOUT,
+ GPIO1B1_UART21_SOUT,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+ GPIO1C7_SHIFT = 14,
+ GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
+ GPIO1C7_GPIO = 0,
+ GPIO1C7_NAND_CS3,
+ GPIO1C7_EMMC_RSTNOUT,
+
+ GPIO1C6_SHIFT = 12,
+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
+ GPIO1C6_GPIO = 0,
+ GPIO1C6_NAND_CS2,
+ GPIO1C6_EMMC_CMD,
+
+
+ GPIO1C5_SHIFT = 10,
+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
+ GPIO1C5_GPIO = 0,
+ GPIO1C5_SDMMC_D3,
+ GPIO1C5_JTAG_TMS,
+
+ GPIO1C4_SHIFT = 8,
+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
+ GPIO1C4_GPIO = 0,
+ GPIO1C4_SDMMC_D2,
+ GPIO1C4_JTAG_TCK,
+
+ GPIO1C3_SHIFT = 6,
+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
+ GPIO1C3_GPIO = 0,
+ GPIO1C3_SDMMC_D1,
+ GPIO1C3_UART2_SIN,
+
+ GPIO1C2_SHIFT = 4,
+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
+ GPIO1C2_GPIO = 0,
+ GPIO1C2_SDMMC_D0,
+ GPIO1C2_UART2_SOUT,
+
+ GPIO1C1_SHIFT = 2,
+ GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
+ GPIO1C1_GPIO = 0,
+ GPIO1C1_SDMMC_DETN,
+
+ GPIO1C0_SHIFT = 0,
+ GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
+ GPIO1C0_GPIO = 0,
+ GPIO1C0_SDMMC_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D7_SHIFT = 14,
+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
+ GPIO1D7_GPIO = 0,
+ GPIO1D7_NAND_D7,
+ GPIO1D7_EMMC_D7,
+
+ GPIO1D6_SHIFT = 12,
+ GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
+ GPIO1D6_GPIO = 0,
+ GPIO1D6_NAND_D6,
+ GPIO1D6_EMMC_D6,
+
+ GPIO1D5_SHIFT = 10,
+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
+ GPIO1D5_GPIO = 0,
+ GPIO1D5_NAND_D5,
+ GPIO1D5_EMMC_D5,
+
+ GPIO1D4_SHIFT = 8,
+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
+ GPIO1D4_GPIO = 0,
+ GPIO1D4_NAND_D4,
+ GPIO1D4_EMMC_D4,
+
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
+ GPIO1D3_GPIO = 0,
+ GPIO1D3_NAND_D3,
+ GPIO1D3_EMMC_D3,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
+ GPIO1D2_GPIO = 0,
+ GPIO1D2_NAND_D2,
+ GPIO1D2_EMMC_D2,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
+ GPIO1D1_GPIO = 0,
+ GPIO1D1_NAND_D1,
+ GPIO1D1_EMMC_D1,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
+ GPIO1D0_GPIO = 0,
+ GPIO1D0_NAND_D0,
+ GPIO1D0_EMMC_D0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+ GPIO2A7_SHIFT = 14,
+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
+ GPIO2A7_GPIO = 0,
+ GPIO2A7_NAND_DQS,
+ GPIO2A7_EMMC_CLKOUT,
+
+ GPIO2A5_SHIFT = 10,
+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
+ GPIO2A5_GPIO = 0,
+ GPIO2A5_NAND_WP,
+ GPIO2A5_EMMC_PWREN,
+
+ GPIO2A4_SHIFT = 8,
+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
+ GPIO2A4_GPIO = 0,
+ GPIO2A4_NAND_RDY,
+ GPIO2A4_EMMC_CMD,
+
+ GPIO2A3_SHIFT = 6,
+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
+ GPIO2A3_GPIO = 0,
+ GPIO2A3_NAND_RDN,
+ GPIO2A4_SPI1_CSN1,
+
+ GPIO2A2_SHIFT = 4,
+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
+ GPIO2A2_GPIO = 0,
+ GPIO2A2_NAND_WRN,
+ GPIO2A4_SPI1_CSN0,
+
+ GPIO2A1_SHIFT = 2,
+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
+ GPIO2A1_GPIO = 0,
+ GPIO2A1_NAND_CLE,
+ GPIO2A1_SPI1_TXD,
+
+ GPIO2A0_SHIFT = 0,
+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
+ GPIO2A0_GPIO = 0,
+ GPIO2A0_NAND_ALE,
+ GPIO2A0_SPI1_RXD,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+ GPIO2B7_SHIFT = 14,
+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
+ GPIO2B7_GPIO = 0,
+ GPIO2B7_GMAC_RXER,
+
+ GPIO2B6_SHIFT = 12,
+ GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
+ GPIO2B6_GPIO = 0,
+ GPIO2B6_GMAC_CLK,
+ GPIO2B6_MAC_LINK,
+
+ GPIO2B5_SHIFT = 10,
+ GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
+ GPIO2B5_GPIO = 0,
+ GPIO2B5_GMAC_TXEN,
+
+ GPIO2B4_SHIFT = 8,
+ GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
+ GPIO2B4_GPIO = 0,
+ GPIO2B4_GMAC_MDIO,
+
+ GPIO2B3_SHIFT = 6,
+ GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
+ GPIO2B3_GPIO = 0,
+ GPIO2B3_GMAC_RXCLK,
+
+ GPIO2B2_SHIFT = 4,
+ GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
+ GPIO2B2_GPIO = 0,
+ GPIO2B2_GMAC_CRS,
+
+ GPIO2B1_SHIFT = 2,
+ GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
+ GPIO2B1_GPIO = 0,
+ GPIO2B1_GMAC_TXCLK,
+
+
+ GPIO2B0_SHIFT = 0,
+ GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
+ GPIO2B0_GPIO = 0,
+ GPIO2B0_GMAC_RXDV,
+ GPIO2B0_MAC_SPEED_IOUT,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C7_SHIFT = 14,
+ GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
+ GPIO2C7_GPIO = 0,
+ GPIO2C7_GMAC_TXD3,
+
+ GPIO2C6_SHIFT = 12,
+ GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
+ GPIO2C6_GPIO = 0,
+ GPIO2C6_GMAC_TXD2,
+
+ GPIO2C5_SHIFT = 10,
+ GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
+ GPIO2C5_GPIO = 0,
+ GPIO2C5_I2C2_SCL,
+ GPIO2C5_GMAC_RXD2,
+
+ GPIO2C4_SHIFT = 8,
+ GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
+ GPIO2C4_GPIO = 0,
+ GPIO2C4_I2C2_SDA,
+ GPIO2C4_GMAC_RXD3,
+
+ GPIO2C3_SHIFT = 6,
+ GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
+ GPIO2C3_GPIO = 0,
+ GPIO2C3_GMAC_TXD0,
+
+ GPIO2C2_SHIFT = 4,
+ GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
+ GPIO2C2_GPIO = 0,
+ GPIO2C2_GMAC_TXD1,
+
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
+ GPIO2C1_GPIO = 0,
+ GPIO2C1_GMAC_RXD0,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
+ GPIO2C0_GPIO = 0,
+ GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+ GPIO2D1_SHIFT = 2,
+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
+ GPIO2D1_GPIO = 0,
+ GPIO2D1_GMAC_MDC,
+
+ GPIO2D0_SHIFT = 0,
+ GPIO2D0_MASK = 3,
+ GPIO2D0_GPIO = 0,
+ GPIO2D0_GMAC_COL,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+ GPIO3C6_SHIFT = 12,
+ GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
+ GPIO3C6_GPIO = 0,
+ GPIO3C6_DRV_VBUS1,
+
+ GPIO3C5_SHIFT = 10,
+ GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
+ GPIO3C5_GPIO = 0,
+ GPIO3C5_PWM10,
+
+ GPIO3C1_SHIFT = 2,
+ GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
+ GPIO3C1_GPIO = 0,
+ GPIO3C1_DRV_VBUS,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+ GPIO3D2_SHIFT = 4,
+ GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
+ GPIO3D2_GPIO = 0,
+ GPIO3D2_PWM3,
+};
+
+/* GRF_CON_IOMUX */
+enum {
+ CON_IOMUX_GMAC_SHIFT = 15,
+ CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
+ CON_IOMUX_UART1SEL_SHIFT = 11,
+ CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
+ CON_IOMUX_UART2SEL_SHIFT = 8,
+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
+ CON_IOMUX_UART2SEL_2 = 0,
+ CON_IOMUX_UART2SEL_21,
+ CON_IOMUX_EMMCSEL_SHIFT = 7,
+ CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
+ CON_IOMUX_PWM3SEL_SHIFT = 3,
+ CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
+ CON_IOMUX_PWM2SEL_SHIFT = 2,
+ CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
+ CON_IOMUX_PWM1SEL_SHIFT = 1,
+ CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
+ CON_IOMUX_PWM0SEL_SHIFT = 0,
+ CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
+};
+#endif
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 150c68d..7c5d269 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -177,6 +177,16 @@ config PINCTRL_ROCKCHIP_RK3188
the GPIO definitions and pin control functions for each available
multiplex function.
+config PINCTRL_ROCKCHIP_RK322X
+ bool "Rockchip rk322x pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip rk322x SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
+
config PINCTRL_ROCKCHIP_RK3288
bool "Rockchip rk3288 pin control driver"
depends on DM
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index a1c655d..5251771 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
+obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o
obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
new file mode 100644
index 0000000..5404008
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -0,0 +1,295 @@
+/*
+ * Pinctrl driver for Rockchip 3036 SoCs
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/grf_rk322x.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk322x_pinctrl_priv {
+ struct rk322x_grf *grf;
+};
+
+static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
+{
+ u32 mux_con = readl(&grf->con_iomux);
+
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ if (mux_con & CON_IOMUX_PWM0SEL_MASK)
+ rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
+ GPIO3C5_PWM10 << GPIO3C5_SHIFT);
+ else
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
+ GPIO0D2_PWM0 << GPIO0D2_SHIFT);
+ break;
+ case PERIPH_ID_PWM1:
+ if (mux_con & CON_IOMUX_PWM1SEL_MASK)
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
+ GPIO0D6_PWM11 << GPIO0D6_SHIFT);
+ else
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
+ GPIO0D3_PWM1 << GPIO0D3_SHIFT);
+ break;
+ case PERIPH_ID_PWM2:
+ if (mux_con & CON_IOMUX_PWM2SEL_MASK)
+ rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
+ GPIO1B4_PWM12 << GPIO1B4_SHIFT);
+ else
+ rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
+ GPIO0D4_PWM2 << GPIO0D4_SHIFT);
+ break;
+ case PERIPH_ID_PWM3:
+ if (mux_con & CON_IOMUX_PWM3SEL_MASK)
+ rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
+ GPIO1B3_PWM13 << GPIO1B3_SHIFT);
+ else
+ rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
+ GPIO3D2_PWM3 << GPIO3D2_SHIFT);
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A1_MASK | GPIO0A0_MASK,
+ GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
+ GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
+
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A3_MASK | GPIO0A2_MASK,
+ GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
+ GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio2c_iomux,
+ GPIO2C5_MASK | GPIO2C4_MASK,
+ GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
+ GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
+ break;
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio0a_iomux,
+ GPIO0A7_MASK | GPIO0A6_MASK,
+ GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
+ GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
+
+ break;
+ }
+}
+
+static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
+{
+ switch (cs) {
+ case 0:
+ rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
+ GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
+ break;
+ case 1:
+ rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
+ GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
+ break;
+ }
+ rk_clrsetreg(&grf->gpio0b_iomux,
+ GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
+ GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
+ GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
+ GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
+}
+
+static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
+{
+ u32 mux_con = readl(&grf->con_iomux);
+
+ switch (uart_id) {
+ case PERIPH_ID_UART1:
+ if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK | GPIO1B2_MASK,
+ GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
+ GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
+ break;
+ case PERIPH_ID_UART2:
+ if (mux_con & CON_IOMUX_UART2SEL_MASK)
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK | GPIO1B2_MASK,
+ GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
+ GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
+ else
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C3_MASK | GPIO1C2_MASK,
+ GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
+ GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
+ break;
+ }
+}
+
+static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
+{
+ switch (mmc_id) {
+ case PERIPH_ID_EMMC:
+ rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
+ GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
+ GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
+ GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
+ GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
+ GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
+ GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
+ GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
+ GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
+ rk_clrsetreg(&grf->gpio2a_iomux,
+ GPIO2A5_MASK | GPIO2A7_MASK,
+ GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
+ GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
+ rk_clrsetreg(&grf->gpio1c_iomux,
+ GPIO1C6_MASK | GPIO1C7_MASK,
+ GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
+ GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
+ break;
+ case PERIPH_ID_SDCARD:
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B6_MASK | GPIO1B7_MASK,
+ GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
+ GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
+ rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
+ GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
+ GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
+ GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
+ GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
+ GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
+ GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
+ break;
+ }
+}
+
+static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
+{
+ struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
+
+ debug("%s: func=%x, flags=%x\n", __func__, func, flags);
+ switch (func) {
+ case PERIPH_ID_PWM0:
+ case PERIPH_ID_PWM1:
+ case PERIPH_ID_PWM2:
+ case PERIPH_ID_PWM3:
+ pinctrl_rk322x_pwm_config(priv->grf, func);
+ break;
+ case PERIPH_ID_I2C0:
+ case PERIPH_ID_I2C1:
+ case PERIPH_ID_I2C2:
+ pinctrl_rk322x_i2c_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SPI0:
+ pinctrl_rk322x_spi_config(priv->grf, flags);
+ break;
+ case PERIPH_ID_UART0:
+ case PERIPH_ID_UART1:
+ case PERIPH_ID_UART2:
+ pinctrl_rk322x_uart_config(priv->grf, func);
+ break;
+ case PERIPH_ID_SDMMC0:
+ case PERIPH_ID_SDMMC1:
+ pinctrl_rk322x_sdmmc_config(priv->grf, func);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
+ struct udevice *periph)
+{
+ u32 cell[3];
+ int ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
+ "interrupts", cell, ARRAY_SIZE(cell));
+ if (ret < 0)
+ return -EINVAL;
+
+ switch (cell[1]) {
+ case 12:
+ return PERIPH_ID_SDCARD;
+ case 14:
+ return PERIPH_ID_EMMC;
+ case 36:
+ return PERIPH_ID_I2C0;
+ case 37:
+ return PERIPH_ID_I2C1;
+ case 38:
+ return PERIPH_ID_I2C2;
+ case 49:
+ return PERIPH_ID_SPI0;
+ case 50:
+ return PERIPH_ID_PWM0;
+ case 55:
+ return PERIPH_ID_UART0;
+ case 56:
+ return PERIPH_ID_UART1;
+ case 57:
+ return PERIPH_ID_UART2;
+ }
+ return -ENOENT;
+}
+
+static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
+ struct udevice *periph)
+{
+ int func;
+
+ func = rk322x_pinctrl_get_periph_id(dev, periph);
+ if (func < 0)
+ return func;
+ return rk322x_pinctrl_request(dev, func, 0);
+}
+
+static struct pinctrl_ops rk322x_pinctrl_ops = {
+ .set_state_simple = rk322x_pinctrl_set_state_simple,
+ .request = rk322x_pinctrl_request,
+ .get_periph_id = rk322x_pinctrl_get_periph_id,
+};
+
+static int rk322x_pinctrl_probe(struct udevice *dev)
+{
+ struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ debug("%s: grf=%p\n", __func__, priv->grf);
+ return 0;
+}
+
+static const struct udevice_id rk322x_pinctrl_ids[] = {
+ { .compatible = "rockchip,rk322x-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk322x) = {
+ .name = "pinctrl_rk322x",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk322x_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
+ .ops = &rk322x_pinctrl_ops,
+ .bind = dm_scan_fdt_dev,
+ .probe = rk322x_pinctrl_probe,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 4/7] rockchip: rk322x: add dts file
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
` (2 preceding siblings ...)
2017-06-09 12:28 ` [U-Boot] [PATCH 3/7] rockchip: rk322x: add pinctrl driver Kever Yang
@ 2017-06-09 12:28 ` Kever Yang
2017-06-12 14:18 ` [U-Boot] [U-Boot,4/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 5/7] rockchip: rk322x: add basic soc support Kever Yang
` (2 subsequent siblings)
6 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
The dts files are from kernel and with modify to adapt U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/rk3229-evb.dts | 77 ++++
arch/arm/dts/rk322x.dtsi | 710 +++++++++++++++++++++++++++++++++
include/dt-bindings/clock/rk3228-cru.h | 247 ++++++++++++
3 files changed, 1034 insertions(+)
create mode 100644 arch/arm/dts/rk3229-evb.dts
create mode 100644 arch/arm/dts/rk322x.dtsi
create mode 100644 include/dt-bindings/clock/rk3228-cru.h
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
new file mode 100644
index 0000000..ccdac1c
--- /dev/null
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+
+#include "rk322x.dtsi"
+
+/ {
+ model = "Rockchip RK3229 Evaluation board";
+ compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory at 60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ ext_gmac: ext_gmac {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&dmc {
+ rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>;
+ rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
+ 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
+ 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
+ 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
+ 0x0 0x924>;
+ rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
+ rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
+ 0 300 3 0 120>;
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
new file mode 100644
index 0000000..7237da4
--- /dev/null
+++ b/arch/arm/dts/rk322x.dtsi
@@ -0,0 +1,710 @@
+/*
+ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3228-cru.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ resets = <&cru SRST_CORE0>;
+ operating-points = <
+ /* KHz uV */
+ 816000 1000000
+ >;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1: cpu at f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ resets = <&cru SRST_CORE1>;
+ };
+
+ cpu2: cpu at f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ resets = <&cru SRST_CORE2>;
+ };
+
+ cpu3: cpu at f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ resets = <&cru SRST_CORE3>;
+ };
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma at 110f0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x110f0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ bus_intmem at 10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x9000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x9000>;
+ smp-sram at 0 {
+ compatible = "rockchip,rk322x-smp-sram";
+ reg = <0x00 0x10>;
+ };
+ ddr_sram: ddr-sram at 1000 {
+ compatible = "rockchip,rk322x-ddr-sram";
+ reg = <0x1000 0x8000>;
+ };
+ };
+
+ i2s1: i2s1 at 100b0000 {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100b0000 0x4000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+ dmas = <&pdma 14>, <&pdma 15>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_bus>;
+ status = "disabled";
+ };
+
+ i2s0: i2s0 at 100c0000 {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100c0000 0x4000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+ dmas = <&pdma 11>, <&pdma 12>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2s2: i2s2 at 100e0000 {
+ compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+ reg = <0x100e0000 0x4000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2s_clk", "i2s_hclk";
+ clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+ dmas = <&pdma 0>, <&pdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ grf: syscon at 11000000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3228-grf", "syscon";
+ reg = <0x11000000 0x1000>;
+ };
+
+ uart0: serial at 11010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x11010000 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart1: serial at 11020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x11020000 0x100>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial at 11030000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x11030000 0x100>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ i2c0: i2c at 11050000 {
+ compatible = "rockchip,rk3228-i2c";
+ reg = <0x11050000 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 11060000 {
+ compatible = "rockchip,rk3228-i2c";
+ reg = <0x11060000 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_xfer>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 11070000 {
+ compatible = "rockchip,rk3228-i2c";
+ reg = <0x11070000 0x1000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ status = "disabled";
+ };
+
+ i2c3: i2c at 11080000 {
+ compatible = "rockchip,rk3228-i2c";
+ reg = <0x11080000 0x1000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "i2c";
+ clocks = <&cru PCLK_I2C3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_xfer>;
+ status = "disabled";
+ };
+
+ pwm0: pwm at 110b0000 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0x110b0000 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_pin>;
+ status = "disabled";
+ };
+
+ pwm1: pwm at 110b0010 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0x110b0010 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm1_pin>;
+ status = "disabled";
+ };
+
+ pwm2: pwm at 110b0020 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0x110b0020 0x10>;
+ #pwm-cells = <3>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2_pin>;
+ status = "disabled";
+ };
+
+ pwm3: pwm at 110b0030 {
+ compatible = "rockchip,rk3288-pwm";
+ reg = <0x110b0030 0x10>;
+ #pwm-cells = <2>;
+ clocks = <&cru PCLK_PWM>;
+ clock-names = "pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_pin>;
+ status = "disabled";
+ };
+
+ timer: timer at 110c0000 {
+ compatible = "rockchip,rk3288-timer";
+ reg = <0x110c0000 0x20>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>, <&cru PCLK_TIMER>;
+ clock-names = "timer", "pclk";
+ };
+
+ cru: clock-controller at 110e0000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3228-cru";
+ reg = <0x110e0000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ assigned-clocks = <&cru PLL_GPLL>;
+ assigned-clock-rates = <594000000>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <70000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <75000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <90000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT 6>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
+ tsadc: tsadc at 11150000 {
+ compatible = "rockchip,rk3228-tsadc";
+ reg = <0x11150000 0x100>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ resets = <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb";
+ pinctrl-names = "init", "default", "sleep";
+ pinctrl-0 = <&otp_gpio>;
+ pinctrl-1 = <&otp_out>;
+ pinctrl-2 = <&otp_gpio>;
+ #thermal-sensor-cells = <0>;
+ rockchip,hw-tshut-temp = <95000>;
+ status = "disabled";
+ };
+
+ emmc: dwmmc at 30020000 {
+ compatible = "rockchip,rk3288-dw-mshc";
+ reg = <0x30020000 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <37500000>;
+ max-frequency = <37500000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+ bus-width = <8>;
+ default-sample-phase = <158>;
+ num-slots = <1>;
+ fifo-depth = <0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
+ resets = <&cru SRST_EMMC>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ gmac: ethernet at 30200000 {
+ compatible = "rockchip,rk3228-gmac";
+ reg = <0x30200000 0x10000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
+ <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
+ <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac";
+ resets = <&cru SRST_GMAC>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller at 32010000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x32011000 0x1000>,
+ <0x32012000 0x2000>,
+ <0x32014000 0x2000>,
+ <0x32016000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3228-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0 at 11110000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x11110000 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1 at 11120000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x11120000 0x100>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2 at 11130000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x11130000 0x100>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3 at 11140000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x11140000 0x100>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
+ emmc {
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ gmac {
+ rgmii_pins: rgmii-pins {
+ rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
+ <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
+ <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ rmii_pins: rmii-pins {
+ rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+ <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ phy_pins: phy-pins {
+ rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
+ <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c2 {
+ i2c2_xfer: i2c2-xfer {
+ rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ i2s1_bus: i2s1-bus {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
+ <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
+ <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ pwm0_pin: pwm0-pin {
+ rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1_pin: pwm1-pin {
+ rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2_pin: pwm2-pin {
+ rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3_pin: pwm3-pin {
+ rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc {
+ otp_gpio: otp-gpio {
+ rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ otp_out: otp-out {
+ rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
+ <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
+ <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2_xfer: uart2-xfer {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ uart2_cts: uart2-cts {
+ rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart2_rts: uart2-rts {
+ rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+ };
+
+ dmc: dmc at 11200000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3228-dmc", "syscon";
+ rockchip,cru = <&cru>;
+ rockchip,grf = <&grf>;
+ rockchip,msch = <&service_msch>;
+ reg = <0x11200000 0x3fc
+ 0x12000000 0x400>;
+ rockchip,sram = <&ddr_sram>;
+ };
+
+ service_msch: syscon at 31090000 {
+ u-boot,dm-pre-reloc;
+ compatible = "rockchip,rk3228-msch", "syscon";
+ reg = <0x31090000 0x2000>;
+ };
+};
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
new file mode 100644
index 0000000..b27e2b1
--- /dev/null
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
+ * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_DPLL 2
+#define PLL_CPLL 3
+#define PLL_GPLL 4
+#define ARMCLK 5
+
+/* sclk gates (special clocks) */
+#define SCLK_SPI0 65
+#define SCLK_NANDC 67
+#define SCLK_SDMMC 68
+#define SCLK_SDIO 69
+#define SCLK_EMMC 71
+#define SCLK_TSADC 72
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_I2S0 80
+#define SCLK_I2S1 81
+#define SCLK_I2S2 82
+#define SCLK_SPDIF 83
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_TIMER4 89
+#define SCLK_TIMER5 90
+#define SCLK_I2S_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO_DRV 115
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO_SAMPLE 119
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_VOP 122
+#define SCLK_HDMI_HDCP 123
+#define SCLK_MAC_SRC 124
+#define SCLK_MAC_EXTCLK 125
+#define SCLK_MAC 126
+#define SCLK_MAC_REFOUT 127
+#define SCLK_MAC_REF 128
+#define SCLK_MAC_RX 129
+#define SCLK_MAC_TX 130
+#define SCLK_MAC_PHY 131
+#define SCLK_MAC_OUT 132
+
+/* dclk gates */
+#define DCLK_VOP 190
+#define DCLK_HDMI_PHY 191
+
+/* aclk gates */
+#define ACLK_DMAC 194
+#define ACLK_PERI 210
+#define ACLK_VOP 211
+#define ACLK_GMAC 212
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_GRF 329
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_SPI0 338
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_TSADC 344
+#define PCLK_PWM 350
+#define PCLK_TIMER 353
+#define PCLK_PERI 363
+#define PCLK_HDMI_CTRL 364
+#define PCLK_HDMI_PHY 365
+#define PCLK_GMAC 367
+
+/* hclk gates */
+#define HCLK_I2S0_8CH 442
+#define HCLK_I2S1_8CH 443
+#define HCLK_I2S2_2CH 444
+#define HCLK_SPDIF_8CH 445
+#define HCLK_VOP 452
+#define HCLK_NANDC 453
+#define HCLK_SDMMC 456
+#define HCLK_SDIO 457
+#define HCLK_EMMC 459
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE0_PO 0
+#define SRST_CORE1_PO 1
+#define SRST_CORE2_PO 2
+#define SRST_CORE3_PO 3
+#define SRST_CORE0 4
+#define SRST_CORE1 5
+#define SRST_CORE2 6
+#define SRST_CORE3 7
+#define SRST_CORE0_DBG 8
+#define SRST_CORE1_DBG 9
+#define SRST_CORE2_DBG 10
+#define SRST_CORE3_DBG 11
+#define SRST_TOPDBG 12
+#define SRST_ACLK_CORE 13
+#define SRST_NOC 14
+#define SRST_L2C 15
+
+#define SRST_CPUSYS_H 18
+#define SRST_BUSSYS_H 19
+#define SRST_SPDIF 20
+#define SRST_INTMEM 21
+#define SRST_ROM 22
+#define SRST_OTG_ADP 23
+#define SRST_I2S0 24
+#define SRST_I2S1 25
+#define SRST_I2S2 26
+#define SRST_ACODEC_P 27
+#define SRST_DFIMON 28
+#define SRST_MSCH 29
+#define SRST_EFUSE1024 30
+#define SRST_EFUSE256 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_GPIO3 35
+#define SRST_PERIPH_NOC_A 36
+#define SRST_PERIPH_NOC_BUS_H 37
+#define SRST_PERIPH_NOC_P 38
+#define SRST_UART0 39
+#define SRST_UART1 40
+#define SRST_UART2 41
+#define SRST_PHYNOC 42
+#define SRST_I2C0 43
+#define SRST_I2C1 44
+#define SRST_I2C2 45
+#define SRST_I2C3 46
+
+#define SRST_PWM 48
+#define SRST_A53_GIC 49
+#define SRST_DAP 51
+#define SRST_DAP_NOC 52
+#define SRST_CRYPTO 53
+#define SRST_SGRF 54
+#define SRST_GRF 55
+#define SRST_GMAC 56
+#define SRST_PERIPH_NOC_H 58
+#define SRST_MACPHY 63
+
+#define SRST_DMA 64
+#define SRST_NANDC 68
+#define SRST_USBOTG 69
+#define SRST_OTGC 70
+#define SRST_USBHOST0 71
+#define SRST_HOST_CTRL0 72
+#define SRST_USBHOST1 73
+#define SRST_HOST_CTRL1 74
+#define SRST_USBHOST2 75
+#define SRST_HOST_CTRL2 76
+#define SRST_USBPOR0 77
+#define SRST_USBPOR1 78
+#define SRST_DDRMSCH 79
+
+#define SRST_SMART_CARD 80
+#define SRST_SDMMC 81
+#define SRST_SDIO 82
+#define SRST_EMMC 83
+#define SRST_SPI 84
+#define SRST_TSP_H 85
+#define SRST_TSP 86
+#define SRST_TSADC 87
+#define SRST_DDRPHY 88
+#define SRST_DDRPHY_P 89
+#define SRST_DDRCTRL 90
+#define SRST_DDRCTRL_P 91
+#define SRST_HOST0_ECHI 92
+#define SRST_HOST1_ECHI 93
+#define SRST_HOST2_ECHI 94
+#define SRST_VOP_NOC_A 95
+
+#define SRST_HDMI_P 96
+#define SRST_VIO_ARBI_H 97
+#define SRST_IEP_NOC_A 98
+#define SRST_VIO_NOC_H 99
+#define SRST_VOP_A 100
+#define SRST_VOP_H 101
+#define SRST_VOP_D 102
+#define SRST_UTMI0 103
+#define SRST_UTMI1 104
+#define SRST_UTMI2 105
+#define SRST_UTMI3 106
+#define SRST_RGA 107
+#define SRST_RGA_NOC_A 108
+#define SRST_RGA_A 109
+#define SRST_RGA_H 110
+#define SRST_HDCP_A 111
+
+#define SRST_VPU_A 112
+#define SRST_VPU_H 113
+#define SRST_VPU_NOC_A 116
+#define SRST_VPU_NOC_H 117
+#define SRST_RKVDEC_A 118
+#define SRST_RKVDEC_NOC_A 119
+#define SRST_RKVDEC_H 120
+#define SRST_RKVDEC_NOC_H 121
+#define SRST_RKVDEC_CORE 122
+#define SRST_RKVDEC_CABAC 123
+#define SRST_IEP_A 124
+#define SRST_IEP_H 125
+#define SRST_GPU_A 126
+#define SRST_GPU_NOC_A 127
+
+#define SRST_CORE_DBG 128
+#define SRST_DBG_P 129
+#define SRST_TIMER0 130
+#define SRST_TIMER1 131
+#define SRST_TIMER2 132
+#define SRST_TIMER3 133
+#define SRST_TIMER4 134
+#define SRST_TIMER5 135
+#define SRST_VIO_H2P 136
+#define SRST_HDMIPHY 139
+#define SRST_VDAC 140
+#define SRST_TIMER_6CH_P 141
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 5/7] rockchip: rk322x: add basic soc support
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
` (3 preceding siblings ...)
2017-06-09 12:28 ` [U-Boot] [PATCH 4/7] rockchip: rk322x: add dts file Kever Yang
@ 2017-06-09 12:28 ` Kever Yang
2017-06-12 14:19 ` [U-Boot] [U-Boot,5/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 6/7] rockchip: rk322x: add sysreset driver Kever Yang
2017-06-09 12:28 ` [U-Boot] [PATCH 7/7] rockchip: add evb_rk3229 board Kever Yang
6 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
Enable soc support for SPL and U-boot skeleton.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/clock.h | 1 +
arch/arm/mach-rockchip/Kconfig | 13 +++
arch/arm/mach-rockchip/Makefile | 3 +
arch/arm/mach-rockchip/rk322x-board-spl.c | 77 +++++++++++++
arch/arm/mach-rockchip/rk322x-board.c | 159 ++++++++++++++++++++++++++
arch/arm/mach-rockchip/rk322x/Kconfig | 18 +++
arch/arm/mach-rockchip/rk322x/Makefile | 9 ++
arch/arm/mach-rockchip/rk322x/clk_rk322x.c | 33 ++++++
arch/arm/mach-rockchip/rk322x/syscon_rk322x.c | 22 ++++
include/configs/rk322x_common.h | 92 +++++++++++++++
10 files changed, 427 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk322x-board-spl.c
create mode 100644 arch/arm/mach-rockchip/rk322x-board.c
create mode 100644 arch/arm/mach-rockchip/rk322x/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk322x/Makefile
create mode 100644 arch/arm/mach-rockchip/rk322x/clk_rk322x.c
create mode 100644 arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
create mode 100644 include/configs/rk322x_common.h
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index b06bb6c..641df58 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -19,6 +19,7 @@ enum {
ROCKCHIP_SYSCON_PMUGRF,
ROCKCHIP_SYSCON_PMUSGRF,
ROCKCHIP_SYSCON_CIC,
+ ROCKCHIP_SYSCON_MSCH,
};
/* Standard Rockchip clock numbers */
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 9b2ef29..33bd17f 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -28,6 +28,19 @@ config ROCKCHIP_RK3188
Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
UART, SPI, I2C and PWMs.
+config ROCKCHIP_RK322X
+ bool "Support Rockchip RK3228/RK3229"
+ select CPU_V7
+ select SUPPORT_SPL
+ select SPL
+ select ROCKCHIP_BROM_HELPER
+ select DEBUG_UART_BOARD_INIT
+ help
+ The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
+ including NEON and GPU, Mali-400 graphics, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
+
config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 87d2019..71dd66d 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -12,11 +12,13 @@ obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
else ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
+obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
else
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
+obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
endif
@@ -29,6 +31,7 @@ ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
endif
+obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
new file mode 100644
index 0000000..b2d0635
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/cru_rk322x.h>
+#include <asm/arch/grf_rk322x.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/uart.h>
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_MMC1;
+}
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE 0x11000000
+#define SGRF_BASE 0x10140000
+
+#define DEBUG_UART_BASE 0x11030000
+
+void board_debug_uart_init(void)
+{
+static struct rk322x_grf * const grf = (void *)GRF_BASE;
+ /* Enable early UART2 channel 1 on the RK322x */
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK | GPIO1B2_MASK,
+ GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
+ GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
+ /* Set channel C as UART2 input */
+ rk_clrsetreg(&grf->con_iomux,
+ CON_IOMUX_UART2SEL_MASK,
+ CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+}
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+ printascii("SPL Init");
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ rockchip_timer_init();
+ printf("timer init done\n");
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return;
+ }
+
+#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
+ back_to_bootrom();
+#endif
+}
diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
new file mode 100644
index 0000000..1d4fa72
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk322x-board.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <ram.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/grf_rk322x.h>
+#include <asm/arch/boot_mode.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GRF_BASE 0x11000000
+
+static void setup_boot_mode(void)
+{
+ struct rk322x_grf *const grf = (void *)GRF_BASE;
+ int boot_mode = readl(&grf->os_reg[4]);
+
+ debug("boot mode %x.\n", boot_mode);
+
+ /* Clear boot mode */
+ writel(BOOT_NORMAL, &grf->os_reg[4]);
+
+ switch (boot_mode) {
+ case BOOT_FASTBOOT:
+ printf("enter fastboot!\n");
+ setenv("preboot", "setenv preboot; fastboot usb0");
+ break;
+ case BOOT_UMS:
+ printf("enter UMS!\n");
+ setenv("preboot", "setenv preboot; ums mmc 0");
+ break;
+ }
+}
+
+__weak int rk_board_late_init(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ setup_boot_mode();
+
+ return rk_board_late_init();
+}
+
+int board_init(void)
+{
+#include <asm/arch/grf_rk322x.h>
+ /* Enable early UART2 channel 1 on the RK322x */
+#define GRF_BASE 0x11000000
+ struct rk322x_grf * const grf = (void *)GRF_BASE;
+
+ rk_clrsetreg(&grf->gpio1b_iomux,
+ GPIO1B1_MASK | GPIO1B2_MASK,
+ GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
+ GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
+ /* Set channel C as UART2 input */
+ rk_clrsetreg(&grf->con_iomux,
+ CON_IOMUX_UART2SEL_MASK,
+ CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ /* Reserve 0x200000 for OPTEE */
+ gd->bd->bi_dram[0].start = 0x60000000;
+ gd->bd->bi_dram[0].size = 0x8400000;
+ gd->bd->bi_dram[1].start = 0x6a400000;
+ gd->bd->bi_dram[1].size = 0x40000000 - 0xa400000;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct ram_info ram;
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("Cannot get DRAM size: %d\n", ret);
+ return ret;
+ }
+ debug("SDRAM base=%x, size=%x\n",
+ (unsigned int)ram.base, (unsigned int)ram.size);
+ gd->ram_size = ram.size;
+
+ return 0;
+}
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+#endif
+
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk322x_otg_data = {
+ .rx_fifo_sz = 512,
+ .np_tx_fifo_sz = 16,
+ .tx_fifo_sz = 128,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int node;
+ const char *mode;
+ bool matched = false;
+ const void *blob = gd->fdt_blob;
+
+ /* find the usb_otg node */
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3288-usb");
+
+ while (node > 0) {
+ mode = fdt_getprop(blob, node, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ node = fdt_node_offset_by_compatible(blob, node,
+ "rockchip,rk3288-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
+
+ return dwc2_udc_probe(&rk322x_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig
new file mode 100644
index 0000000..dc8071e
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk322x/Kconfig
@@ -0,0 +1,18 @@
+if ROCKCHIP_RK322X
+
+config TARGET_EVB_RK3229
+ bool "EVB_RK3229"
+ select BOARD_LATE_INIT
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+config SPL_SERIAL_SUPPORT
+ default y
+
+source "board/rockchip/evb_rk3229/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile
new file mode 100644
index 0000000..ecb3e8d
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk322x/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2017 Rockchip Electronics Co., Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+
+obj-y += clk_rk322x.o
+obj-y += syscon_rk322x.o
diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c
new file mode 100644
index 0000000..6e8be93
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk322x.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk322x_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk322x_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
new file mode 100644
index 0000000..c5cae32
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk322x_syscon_ids[] = {
+ { .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3228-msch", .data = ROCKCHIP_SYSCON_MSCH },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk322x) = {
+ .name = "rk322x_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk322x_syscon_ids,
+};
diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
new file mode 100644
index 0000000..23b1707
--- /dev/null
+++ b/include/configs/rk322x_common.h
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __CONFIG_RK322X_COMMON_H
+#define __CONFIG_RK322X_COMMON_H
+
+#include <asm/arch/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+
+#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
+#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
+#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_TEXT_BASE 0x60000000
+#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
+#define CONFIG_SYS_LOAD_ADDR 0x60800800
+#define CONFIG_SPL_STACK 0x10088000
+#define CONFIG_SPL_TEXT_BASE 0x10081004
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
+#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SYS_SDRAM_BASE 0x60000000
+#define CONFIG_NR_DRAM_BANKS 2
+#define SDRAM_BANK_SIZE (512UL << 20UL)
+
+#ifndef CONFIG_SPL_BUILD
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+
+/* fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
+#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
+
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_CMD_USB_MASS_STORAGE
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM 0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
+
+/* usb host */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#endif
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x60000000\0" \
+ "pxefile_addr_r=0x60100000\0" \
+ "fdt_addr_r=0x61f00000\0" \
+ "kernel_addr_r=0x62000000\0" \
+ "ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
+ * so limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x7fffffff\0" \
+ "partitions=" PARTS_DEFAULT \
+ ENV_MEM_LAYOUT_SETTINGS \
+ BOOTENV
+#endif
+
+#define CONFIG_PREBOOT
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 6/7] rockchip: rk322x: add sysreset driver
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
` (4 preceding siblings ...)
2017-06-09 12:28 ` [U-Boot] [PATCH 5/7] rockchip: rk322x: add basic soc support Kever Yang
@ 2017-06-09 12:28 ` Kever Yang
2017-06-12 14:19 ` [U-Boot] [U-Boot,6/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 7/7] rockchip: add evb_rk3229 board Kever Yang
6 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
only difference is that the target register address is different.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
drivers/sysreset/sysreset_rk322x.c | 45 ++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 drivers/sysreset/sysreset_rk322x.c
diff --git a/drivers/sysreset/sysreset_rk322x.c b/drivers/sysreset/sysreset_rk322x.c
new file mode 100644
index 0000000..5fce79b
--- /dev/null
+++ b/drivers/sysreset/sysreset_rk322x.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk322x.h>
+#include <asm/arch/hardware.h>
+#include <linux/err.h>
+
+int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+ struct rk322x_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case SYSRESET_WARM:
+ writel(0xeca8, &cru->cru_glb_srst_snd_value);
+ break;
+ case SYSRESET_COLD:
+ writel(0xfdb9, &cru->cru_glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops rk322x_sysreset = {
+ .request = rk322x_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_rk322x) = {
+ .name = "rk322x_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = &rk322x_sysreset,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [PATCH 7/7] rockchip: add evb_rk3229 board
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
` (5 preceding siblings ...)
2017-06-09 12:28 ` [U-Boot] [PATCH 6/7] rockchip: rk322x: add sysreset driver Kever Yang
@ 2017-06-09 12:28 ` Kever Yang
2017-06-12 14:20 ` [U-Boot] [U-Boot,7/7] " Philipp Tomsich
6 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-09 12:28 UTC (permalink / raw)
To: u-boot
evb_rk3229 is a RK3229 based board, with:
- 8GB eMMC;
- 1GB DDR SDRAM;
- 2 USB2.0 HOST port;
- 1 MAC port;
- 1 HDMI port;
- IR;
- WiFi;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/mach-rockchip/Kconfig | 1 +
board/rockchip/evb_rk3229/Kconfig | 15 +++++++++
board/rockchip/evb_rk3229/MAINTAINERS | 6 ++++
board/rockchip/evb_rk3229/Makefile | 7 ++++
board/rockchip/evb_rk3229/evb_rk3229.c | 12 +++++++
configs/evb-rk3229_defconfig | 44 +++++++++++++++++++++++++
include/configs/evb_rk3229.h | 60 ++++++++++++++++++++++++++++++++++
7 files changed, 145 insertions(+)
create mode 100644 board/rockchip/evb_rk3229/Kconfig
create mode 100644 board/rockchip/evb_rk3229/MAINTAINERS
create mode 100644 board/rockchip/evb_rk3229/Makefile
create mode 100644 board/rockchip/evb_rk3229/evb_rk3229.c
create mode 100644 configs/evb-rk3229_defconfig
create mode 100644 include/configs/evb_rk3229.h
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 33bd17f..bb44c61 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -124,6 +124,7 @@ config SPL_MMC_SUPPORT
source "arch/arm/mach-rockchip/rk3036/Kconfig"
source "arch/arm/mach-rockchip/rk3188/Kconfig"
+source "arch/arm/mach-rockchip/rk322x/Kconfig"
source "arch/arm/mach-rockchip/rk3288/Kconfig"
source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
diff --git a/board/rockchip/evb_rk3229/Kconfig b/board/rockchip/evb_rk3229/Kconfig
new file mode 100644
index 0000000..361dcb1
--- /dev/null
+++ b/board/rockchip/evb_rk3229/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3229
+
+config SYS_BOARD
+ default "evb_rk3229"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3229"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS
new file mode 100644
index 0000000..dfa1090
--- /dev/null
+++ b/board/rockchip/evb_rk3229/MAINTAINERS
@@ -0,0 +1,6 @@
+EVB-RK3229
+M: Kever Yang <kever.yang@rock-chips.com>
+S: Maintained
+F: board/rockchip/evb_rk3229
+F: include/configs/evb_rk3229.h
+F: configs/evb-rk3229_defconfig
diff --git a/board/rockchip/evb_rk3229/Makefile b/board/rockchip/evb_rk3229/Makefile
new file mode 100644
index 0000000..65dcd8b
--- /dev/null
+++ b/board/rockchip/evb_rk3229/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evb_rk3229.o
diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c
new file mode 100644
index 0000000..6c4ec2cd
--- /dev/null
+++ b/board/rockchip/evb_rk3229/evb_rk3229.c
@@ -0,0 +1,12 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
new file mode 100644
index 0000000..0c3b6f7
--- /dev/null
+++ b/configs/evb-rk3229_defconfig
@@ -0,0 +1,44 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_ROCKCHIP_RK322X=y
+CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
+CONFIG_TARGET_EVB_RK3229=y
+CONFIG_SPL_STACK_R_ADDR=0x80000
+CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
+CONFIG_FASTBOOT=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ROCKCHIP_RK322X=y
+# CONFIG_SPL_PINCTRL_FULL is not set
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x11030000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_SYSRESET=y
+CONFIG_ERRNO_STR=y
diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h
new file mode 100644
index 0000000..13fc834
--- /dev/null
+++ b/include/configs/evb_rk3229.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2015 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/rk322x_common.h>
+
+
+/* Store env in emmc */
+#undef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE (32 << 10)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 0
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+
+#ifndef CONFIG_SPL_BUILD
+/* Enable gpt partition table */
+#undef PARTS_DEFAULT
+#define PARTS_DEFAULT \
+ "uuid_disk=${uuid_gpt_disk};" \
+ "name=loader_a,start=4M,size=4M,uuid=${uuid_gpt_loader};" \
+ "name=loader_b,size=4M,uuid=${uuid_gpt_reserved};" \
+ "name=trust_a,size=4M,uuid=${uuid_gpt_reserved};" \
+ "name=trust_b,size=4M,uuid=${uuid_gpt_reserved};" \
+ "name=misc,size=4M,uuid=${uuid_gpt_misc};" \
+ "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
+ "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \
+ "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \
+ "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \
+ "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \
+ "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \
+ "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \
+ "name=cache,size=100M,uuid=${uuid_gpt_cache};" \
+ "name=persist,size=4M,uuid=${uuid_gpt_persist};" \
+ "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \
+
+#define CONFIG_PREBOOT
+
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "mmc read 0x61000000 0x8000 0x5000;" \
+ "bootm 0x61000000" \
+
+/* Enable atags */
+#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
+#define CONFIG_INITRD_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+
+#endif
+
+#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot, 1/7] rockchip: mkimage: add support for rk322x soc
2017-06-09 12:28 ` [U-Boot] [PATCH 1/7] rockchip: mkimage: add support for rk322x soc Kever Yang
@ 2017-06-12 10:52 ` Philipp Tomsich
0 siblings, 0 replies; 20+ messages in thread
From: Philipp Tomsich @ 2017-06-12 10:52 UTC (permalink / raw)
To: u-boot
On Fri, 9 Jun 2017, Kever Yang wrote:
> Add support for rk322x package header in mkimage tool.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> tools/rkcommon.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tools/rkcommon.c b/tools/rkcommon.c
> index fd95abc..6e9595f 100644
> --- a/tools/rkcommon.c
> +++ b/tools/rkcommon.c
> @@ -74,6 +74,7 @@ struct spl_info {
> static struct spl_info spl_infos[] = {
> { "rk3036", "RK30", 0x1000, false, false },
> { "rk3188", "RK31", 0x8000 - 0x800, true, false },
> + { "rk322x", "RK32", 0x8000 - 0x1000, false, false },
> { "rk3288", "RK32", 0x8000, false, false },
> { "rk3328", "RK32", 0x8000 - 0x1000, false, false },
> { "rk3399", "RK33", 0x20000, false, true },
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,2/7] rockchip: rk322x: add clock driver
2017-06-09 12:28 ` [U-Boot] [PATCH 2/7] rockchip: rk322x: add clock driver Kever Yang
@ 2017-06-12 11:00 ` Philipp Tomsich
2017-06-23 8:49 ` Kever Yang
0 siblings, 1 reply; 20+ messages in thread
From: Philipp Tomsich @ 2017-06-12 11:00 UTC (permalink / raw)
To: u-boot
On Fri, 9 Jun 2017, Kever Yang wrote:
> Add clock driver init support for:
> - cpu, bus clock init;
> - emmc, sdmmc clock;
> - ddr clock;
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk322x.c | 413 ++++++++++++++++++++++++
> 3 files changed, 629 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h
> create mode 100644 drivers/clk/rockchip/clk_rk322x.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
> new file mode 100644
> index 0000000..0a01f87
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
> @@ -0,0 +1,215 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef _ASM_ARCH_CRU_RK322X_H
> +#define _ASM_ARCH_CRU_RK322X_H
> +
> +#include <common.h>
> +
> +#define MHz 1000000
> +#define OSC_HZ (24 * MHz)
> +
> +#define APLL_HZ (600 * MHz)
> +#define GPLL_HZ (594 * MHz)
> +
> +#define CORE_PERI_HZ 150000000
> +#define CORE_ACLK_HZ 300000000
> +
> +#define BUS_ACLK_HZ 148500000
> +#define BUS_HCLK_HZ 148500000
> +#define BUS_PCLK_HZ 74250000
> +
> +#define PERI_ACLK_HZ 148500000
> +#define PERI_HCLK_HZ 148500000
> +#define PERI_PCLK_HZ 74250000
> +
> +/* Private data for the clock driver - used by rockchip_get_cru() */
> +struct rk322x_clk_priv {
> + struct rk322x_cru *cru;
> + ulong rate;
> +};
> +
> +struct rk322x_cru {
> + struct rk322x_pll {
> + unsigned int con0;
> + unsigned int con1;
> + unsigned int con2;
> + } pll[4];
> + unsigned int reserved0[4];
> + unsigned int cru_mode_con;
> + unsigned int cru_clksel_con[35];
> + unsigned int cru_clkgate_con[16];
> + unsigned int cru_softrst_con[9];
> + unsigned int cru_misc_con;
> + unsigned int reserved1[2];
> + unsigned int cru_glb_cnt_th;
> + unsigned int reserved2[3];
> + unsigned int cru_glb_rst_st;
> + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
It took me a moment to understand why the 'minus one'.
Could you introduce a macro for this along the lines of
U32_ELEMS_START_TO_LAST(0x1c0, 0x14c)
or something similar... I fail to come up with a concise
name that clearly says "from 0x1c0 and covering up to,
but excluding, the address 0x150").
> + unsigned int cru_sdmmc_con[2];
> + unsigned int cru_sdio_con[2];
> + unsigned int reserved4[2];
> + unsigned int cru_emmc_con[2];
> + unsigned int reserved5[4];
> + unsigned int cru_glb_srst_fst_value;
> + unsigned int cru_glb_srst_snd_value;
> + unsigned int cru_pll_mask_con;
> +};
> +check_member(rk322x_cru, cru_pll_mask_con, 0x01f8);
> +
> +struct pll_div {
> + u32 refdiv;
> + u32 fbdiv;
> + u32 postdiv1;
> + u32 postdiv2;
> + u32 frac;
> +};
> +
> +enum {
> + /* PLLCON0*/
> + PLL_BP_SHIFT = 15,
> + PLL_POSTDIV1_SHIFT = 12,
> + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
> + PLL_FBDIV_SHIFT = 0,
> + PLL_FBDIV_MASK = 0xfff,
> +
> + /* PLLCON1 */
> + PLL_RST_SHIFT = 14,
> + PLL_PD_SHIFT = 13,
> + PLL_PD_MASK = 1 << PLL_PD_SHIFT,
> + PLL_DSMPD_SHIFT = 12,
> + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
> + PLL_LOCK_STATUS_SHIFT = 10,
> + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
> + PLL_POSTDIV2_SHIFT = 6,
> + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
> + PLL_REFDIV_SHIFT = 0,
> + PLL_REFDIV_MASK = 0x3f,
> +
> + /* CRU_MODE */
> + GPLL_MODE_SHIFT = 12,
> + GPLL_MODE_MASK = 1 << GPLL_MODE_SHIFT,
> + GPLL_MODE_SLOW = 0,
> + GPLL_MODE_NORM,
> + CPLL_MODE_SHIFT = 8,
> + CPLL_MODE_MASK = 1 << CPLL_MODE_SHIFT,
> + CPLL_MODE_SLOW = 0,
> + CPLL_MODE_NORM,
> + DPLL_MODE_SHIFT = 4,
> + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT,
> + DPLL_MODE_SLOW = 0,
> + DPLL_MODE_NORM,
> + APLL_MODE_SHIFT = 0,
> + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT,
> + APLL_MODE_SLOW = 0,
> + APLL_MODE_NORM,
> +
> + /* CRU_CLK_SEL0_CON */
> + BUS_ACLK_PLL_SEL_SHIFT = 13,
> + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT,
> + BUS_ACLK_PLL_SEL_APLL = 0,
> + BUS_ACLK_PLL_SEL_GPLL,
> + BUS_ACLK_PLL_SEL_HDMIPLL,
> + BUS_ACLK_DIV_SHIFT = 8,
> + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
> + CORE_CLK_PLL_SEL_SHIFT = 6,
> + CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT,
> + CORE_CLK_PLL_SEL_APLL = 0,
> + CORE_CLK_PLL_SEL_GPLL,
> + CORE_CLK_PLL_SEL_DPLL,
> + CORE_DIV_CON_SHIFT = 0,
> + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
> +
> + /* CRU_CLK_SEL1_CON */
> + BUS_PCLK_DIV_SHIFT = 12,
> + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT,
> + BUS_HCLK_DIV_SHIFT = 8,
> + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT,
> + CORE_ACLK_DIV_SHIFT = 4,
> + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
> + CORE_PERI_DIV_SHIFT = 0,
> + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT,
> +
> + /* CRU_CLKSEL5_CON */
> + GMAC_OUT_PLL_SHIFT = 15,
> + GMAC_OUT_PLL_MASK = 1 << GMAC_OUT_PLL_SHIFT,
> + GMAC_OUT_DIV_SHIFT = 8,
> + GMAC_OUT_DIV_MASK = 0x1f << GMAC_OUT_DIV_SHIFT,
> + MAC_PLL_SEL_SHIFT = 7,
> + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,
> + RMII_EXTCLK_SLE_SHIFT = 5,
> + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SLE_SHIFT,
> + RMII_EXTCLK_SEL_INT = 0,
> + RMII_EXTCLK_SEL_EXT,
> + CLK_MAC_DIV_SHIFT = 0,
> + CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT,
> +
> + /* CRU_CLKSEL10_CON */
> + PERI_PCLK_DIV_SHIFT = 12,
> + PERI_PCLK_DIV_MASK = 7 << PERI_PCLK_DIV_SHIFT,
> + PERI_PLL_SEL_SHIFT = 10,
> + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
> + PERI_PLL_CPLL = 0,
> + PERI_PLL_GPLL,
> + PERI_PLL_HDMIPLL,
> + PERI_HCLK_DIV_SHIFT = 8,
> + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
> + PERI_ACLK_DIV_SHIFT = 0,
> + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
> +
> + /* CRU_CLKSEL11_CON */
> + EMMC_PLL_SHIFT = 12,
> + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
> + EMMC_SEL_APLL = 0,
> + EMMC_SEL_DPLL,
> + EMMC_SEL_GPLL,
> + EMMC_SEL_24M,
> + SDIO_PLL_SHIFT = 10,
> + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
> + SDIO_SEL_APLL = 0,
> + SDIO_SEL_DPLL,
> + SDIO_SEL_GPLL,
> + SDIO_SEL_24M,
> + MMC0_PLL_SHIFT = 8,
> + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
> + MMC0_SEL_APLL = 0,
> + MMC0_SEL_DPLL,
> + MMC0_SEL_GPLL,
> + MMC0_SEL_24M,
> + MMC0_DIV_SHIFT = 0,
> + MMC0_DIV_MASK = 0xff << MMC0_DIV_SHIFT,
> +
> + /* CRU_CLKSEL12_CON */
> + EMMC_DIV_SHIFT = 8,
> + EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
> + SDIO_DIV_SHIFT = 0,
> + SDIO_DIV_MASK = 0xff << SDIO_DIV_SHIFT,
> +
> + /* CRU_CLKSEL26_CON */
> + DDR_CLK_PLL_SEL_SHIFT = 8,
> + DDR_CLK_PLL_SEL_MASK = 3 << DDR_CLK_PLL_SEL_SHIFT,
> + DDR_CLK_SEL_DPLL = 0,
> + DDR_CLK_SEL_GPLL,
> + DDR_CLK_SEL_APLL,
> + DDR_DIV_SEL_SHIFT = 0,
> + DDR_DIV_SEL_MASK = 3 << DDR_DIV_SEL_SHIFT,
> +
> + /* CRU_CLKSEL27_CON */
> + VOP_DCLK_DIV_SHIFT = 8,
> + VOP_DCLK_DIV_MASK = 0xff << VOP_DCLK_DIV_SHIFT,
> + VOP_PLL_SEL_SHIFT = 1,
> + VOP_PLL_SEL_MASK = 1 << VOP_PLL_SEL_SHIFT,
> +
> + /* CRU_CLKSEL29_CON */
> + GMAC_CLK_SRC_SHIFT = 12,
> + GMAC_CLK_SRC_MASK = 1 << GMAC_CLK_SRC_SHIFT,
> +
> + /* CRU_SOFTRST5_CON */
> + DDRCTRL_PSRST_SHIFT = 11,
> + DDRCTRL_SRST_SHIFT = 10,
> + DDRPHY_PSRST_SHIFT = 9,
> + DDRPHY_SRST_SHIFT = 8,
> +};
> +#endif
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index e404c0c..c50aff2 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -6,6 +6,7 @@
>
> obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o
> +obj-$(CONFIG_ROCKCHIP_RK322X) += clk_rk322x.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o
> obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
> diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c
> new file mode 100644
> index 0000000..582ef88
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk322x.c
> @@ -0,0 +1,413 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
> +#include <common.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk322x.h>
> +#include <asm/arch/hardware.h>
> +#include <dm/lists.h>
> +#include <dt-bindings/clock/rk3228-cru.h>
> +#include <linux/log2.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +enum {
> + VCO_MAX_HZ = 3200U * 1000000,
> + VCO_MIN_HZ = 800 * 1000000,
> + OUTPUT_MAX_HZ = 3200U * 1000000,
> + OUTPUT_MIN_HZ = 24 * 1000000,
> +};
> +
> +#define RATE_TO_DIV(input_rate, output_rate) \
> + ((input_rate) / (output_rate) - 1);
The RATE_TO_DIV macro remains unused below.
> +
> +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
> +
> +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
> + .refdiv = _refdiv,\
> + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
> + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
> + _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
> + OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
> + #hz "Hz cannot be hit with PLL "\
> + "divisors on line " __stringify(__LINE__));
> +
> +/* use interge mode*/
typo: integer
> +static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
> +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
> +
> +static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
> + const struct pll_div *div)
> +{
> + int pll_id = rk_pll_id(clk_id);
> + struct rk322x_pll *pll = &cru->pll[pll_id];
> +
> + /* All PLLs have same VCO and output frequency range restrictions. */
> + uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
> + uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
> +
> + debug("PLL at %x: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
> + pll, div->fbdiv, div->refdiv, div->postdiv1,
> + div->postdiv2, vco_hz, output_hz);
> + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
> + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
> +
> + /* use interger mode */
> + rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
> + /* Power down */
> + rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
> +
> + rk_clrsetreg(&pll->con0,
> + PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
> + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
> + rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
> + (div->postdiv2 << PLL_POSTDIV2_SHIFT |
> + div->refdiv << PLL_REFDIV_SHIFT));
> +
> + /* Power Up */
> + rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
> +
> + /* waiting for pll lock */
> + while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
> + udelay(1);
> +
> + return 0;
> +}
> +
> +static void rkclk_init(struct rk322x_cru *cru)
> +{
> + u32 aclk_div;
> + u32 hclk_div;
> + u32 pclk_div;
> +
> + /* pll enter slow-mode */
> + rk_clrsetreg(&cru->cru_mode_con,
> + GPLL_MODE_MASK | APLL_MODE_MASK,
> + GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
> + APLL_MODE_SLOW << APLL_MODE_SHIFT);
> +
> + /* init pll */
> + rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
> + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
> +
> + /*
> + * select apll as cpu/core clock pll source and
> + * set up dependent divisors for PERI and ACLK clocks.
> + * core hz : apll = 1:1
> + */
> + aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
> + assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
> +
> + pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
> + assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[0],
> + CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
> + CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
> + 0 << CORE_DIV_CON_SHIFT);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[1],
> + CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
> + aclk_div << CORE_ACLK_DIV_SHIFT |
> + pclk_div << CORE_PERI_DIV_SHIFT);
> +
> + /*
> + * select apll as pd_bus bus clock source and
> + * set up dependent divisors for PCLK/HCLK and ACLK clocks.
> + */
> + aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
> + assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
> +
> + pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
> + assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
> +
> + hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
> + assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[0],
> + BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
> + BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
> + aclk_div << BUS_ACLK_DIV_SHIFT);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[1],
> + BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
> + pclk_div << BUS_PCLK_DIV_SHIFT |
> + hclk_div << BUS_HCLK_DIV_SHIFT);
> +
> + /*
> + * select gpll as pd_peri bus clock source and
> + * set up dependent divisors for PCLK/HCLK and ACLK clocks.
> + */
> + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
> + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
> +
> + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
> + assert((1 << hclk_div) * PERI_HCLK_HZ ==
> + PERI_ACLK_HZ && (hclk_div < 0x4));
> +
> + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
> + assert((1 << pclk_div) * PERI_PCLK_HZ ==
> + PERI_ACLK_HZ && pclk_div < 0x8);
> +
> + rk_clrsetreg(&cru->cru_clksel_con[10],
> + PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
> + PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
> + PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
> + pclk_div << PERI_PCLK_DIV_SHIFT |
> + hclk_div << PERI_HCLK_DIV_SHIFT |
> + aclk_div << PERI_ACLK_DIV_SHIFT);
> +
> + /* PLL enter normal-mode */
> + rk_clrsetreg(&cru->cru_mode_con,
> + GPLL_MODE_MASK | APLL_MODE_MASK,
> + GPLL_MODE_NORM << GPLL_MODE_SHIFT |
> + APLL_MODE_NORM << APLL_MODE_SHIFT);
> +}
> +
> +/* Get pll rate by id */
> +static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
> + enum rk_clk_id clk_id)
> +{
> + uint32_t refdiv, fbdiv, postdiv1, postdiv2;
> + uint32_t con;
> + int pll_id = rk_pll_id(clk_id);
> + struct rk322x_pll *pll = &cru->pll[pll_id];
> + static u8 clk_shift[CLK_COUNT] = {
> + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
> + GPLL_MODE_SHIFT, 0xff
> + };
> + static u32 clk_mask[CLK_COUNT] = {
> + 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
> + GPLL_MODE_MASK, 0xff
> + };
> + uint shift;
> + uint mask;
> +
> + con = readl(&cru->cru_mode_con);
> + shift = clk_shift[clk_id];
> + mask = clk_mask[clk_id];
> +
> + switch ((con & mask) >> shift) {
> + case GPLL_MODE_SLOW:
> + return OSC_HZ;
> + case GPLL_MODE_NORM:
> +
> + /* normal mode */
> + con = readl(&pll->con0);
> + postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
> + fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
> + con = readl(&pll->con1);
> + postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
> + refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
> + return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
> + default:
> + return 32768;
> + }
> +}
> +
> +static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
> + int periph)
> +{
> + uint src_rate;
> + uint div, mux;
> + u32 con;
> +
> + switch (periph) {
> + case HCLK_EMMC:
> + case SCLK_EMMC:
> + con = readl(&cru->cru_clksel_con[11]);
> + mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
> + con = readl(&cru->cru_clksel_con[12]);
> + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
> + break;
> + case HCLK_SDMMC:
> + case SCLK_SDMMC:
> + con = readl(&cru->cru_clksel_con[11]);
> + mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
> + div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
> + return DIV_TO_RATE(src_rate, div);
> +}
> +
> +static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
> + int periph, uint freq)
> +{
> + int src_clk_div;
> + int mux;
> +
> + debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
> +
> + /* mmc clock auto divide 2 in internal */
> + src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
> +
> + if (src_clk_div > 0x7f) {
> + src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
> + mux = EMMC_SEL_24M;
> + } else {
> + mux = EMMC_SEL_GPLL;
> + }
> +
> + switch (periph) {
> + case HCLK_EMMC:
> + case SCLK_EMMC:
> + rk_clrsetreg(&cru->cru_clksel_con[11],
> + EMMC_PLL_MASK,
> + mux << EMMC_PLL_SHIFT);
> + rk_clrsetreg(&cru->cru_clksel_con[12],
> + EMMC_DIV_MASK,
> + (src_clk_div - 1) << EMMC_DIV_SHIFT);
> + break;
> + case HCLK_SDMMC:
> + case SCLK_SDMMC:
> + rk_clrsetreg(&cru->cru_clksel_con[11],
> + MMC0_PLL_MASK | MMC0_DIV_MASK,
> + mux << MMC0_PLL_SHIFT |
> + (src_clk_div - 1) << MMC0_DIV_SHIFT);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
> +}
> +
> +static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
> +{
> + struct pll_div dpll_cfg;
> +
> + /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
> + switch (set_rate) {
> + case 400*MHz:
> + dpll_cfg = (struct pll_div)
> + {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
> + break;
> + case 600*MHz:
> + dpll_cfg = (struct pll_div)
> + {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
> + break;
> + case 800*MHz:
> + dpll_cfg = (struct pll_div)
> + {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
> + break;
> + }
> +
> + /* pll enter slow-mode */
> + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
> + DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
> + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
> + /* PLL enter normal-mode */
> + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
> + DPLL_MODE_NORM << DPLL_MODE_SHIFT);
> +
> + return set_rate;
> +}
> +static ulong rk322x_clk_get_rate(struct clk *clk)
> +{
> + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong rate, gclk_rate;
> +
> + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
> + switch (clk->id) {
> + case 0 ... 63:
> + rate = rkclk_pll_get_rate(priv->cru, clk->id);
> + break;
> + case HCLK_EMMC:
> + case SCLK_EMMC:
> + case HCLK_SDMMC:
> + case SCLK_SDMMC:
> + rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return rate;
> +}
> +
> +static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
> +{
> + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
> + ulong new_rate, gclk_rate;
> +
> + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
> + switch (clk->id) {
> + case HCLK_EMMC:
> + case SCLK_EMMC:
> + case HCLK_SDMMC:
> + case SCLK_SDMMC:
> + new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
> + clk->id, rate);
> + break;
> + case CLK_DDR:
> + new_rate = rk322x_ddr_set_clk(priv->cru, rate);
> + break;
> + default:
> + return -ENOENT;
> + }
> +
> + return new_rate;
> +}
> +
> +static struct clk_ops rk322x_clk_ops = {
> + .get_rate = rk322x_clk_get_rate,
> + .set_rate = rk322x_clk_set_rate,
> +};
> +
> +static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
> +{
> + struct rk322x_clk_priv *priv = dev_get_priv(dev);
> +
> + priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
> +
> + return 0;
> +}
> +
> +static int rk322x_clk_probe(struct udevice *dev)
> +{
> + struct rk322x_clk_priv *priv = dev_get_priv(dev);
> +
> + rkclk_init(priv->cru);
> +
> + return 0;
> +}
> +
> +static int rk322x_clk_bind(struct udevice *dev)
> +{
> + int ret;
> +
> + /* The reset driver does not have a device node, so bind it here */
> + ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
> + if (ret)
> + debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
> +
> + return 0;
> +}
> +
> +static const struct udevice_id rk322x_clk_ids[] = {
> + { .compatible = "rockchip,rk3228-cru" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(rockchip_rk322x_cru) = {
> + .name = "clk_rk322x",
> + .id = UCLASS_CLK,
> + .of_match = rk322x_clk_ids,
> + .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
> + .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
> + .ops = &rk322x_clk_ops,
> + .bind = rk322x_clk_bind,
> + .probe = rk322x_clk_probe,
> +};
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,3/7] rockchip: rk322x: add pinctrl driver
2017-06-09 12:28 ` [U-Boot] [PATCH 3/7] rockchip: rk322x: add pinctrl driver Kever Yang
@ 2017-06-12 14:18 ` Philipp Tomsich
0 siblings, 0 replies; 20+ messages in thread
From: Philipp Tomsich @ 2017-06-12 14:18 UTC (permalink / raw)
To: u-boot
On Fri, 9 Jun 2017, Kever Yang wrote:
> Add init pinctrl driver support for:
> - i2c;
> - spi;
> - uart;
> - pwm;
> - emmc/sdmmc;
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/grf_rk322x.h | 519 ++++++++++++++++++++++++
> drivers/pinctrl/Kconfig | 10 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk322x.c | 295 ++++++++++++++
> 4 files changed, 825 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk322x.h
> create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk322x.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk322x.h b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
> new file mode 100644
> index 0000000..26071c8
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk322x.h
> @@ -0,0 +1,519 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef _ASM_ARCH_GRF_RK322X_H
> +#define _ASM_ARCH_GRF_RK322X_H
> +
> +#include <common.h>
> +
> +struct rk322x_grf {
> + unsigned int gpio0a_iomux;
> + unsigned int gpio0b_iomux;
> + unsigned int gpio0c_iomux;
> + unsigned int gpio0d_iomux;
> +
> + unsigned int gpio1a_iomux;
> + unsigned int gpio1b_iomux;
> + unsigned int gpio1c_iomux;
> + unsigned int gpio1d_iomux;
> +
> + unsigned int gpio2a_iomux;
> + unsigned int gpio2b_iomux;
> + unsigned int gpio2c_iomux;
> + unsigned int gpio2d_iomux;
> +
> + unsigned int gpio3a_iomux;
> + unsigned int gpio3b_iomux;
> + unsigned int gpio3c_iomux;
> + unsigned int gpio3d_iomux;
> +
> + unsigned int reserved1[4];
> + unsigned int con_iomux;
> + unsigned int reserved2[(0x100 - 0x50) / 4 - 1];
Using a macro for this would clarify things.
See my earlier comment to the other patch from this series.
> + unsigned int gpio0_p[4];
> + unsigned int gpio1_p[4];
> + unsigned int gpio2_p[4];
> + unsigned int gpio3_p[4];
> + unsigned int reserved3[(0x200 - 0x13c) / 4 - 1];
> + unsigned int gpio0_e[4];
> + unsigned int gpio1_e[4];
> + unsigned int gpio2_e[4];
> + unsigned int gpio3_e[4];
> + unsigned int reserved4[(0x400 - 0x23c) / 4 - 1];
> + unsigned int soc_con[7];
> + unsigned int reserved5[(0x480 - 0x418) / 4 - 1];
> + unsigned int soc_status[3];
> + unsigned int chip_id;
> + unsigned int reserved6[(0x500 - 0x48c) / 4 - 1];
> + unsigned int cpu_con[4];
> + unsigned int reserved7[4];
> + unsigned int cpu_status[2];
> + unsigned int reserved8[(0x5c8 - 0x524) / 4 - 1];
> + unsigned int os_reg[8];
> + unsigned int reserved9[(0x604 - 0x5e4) / 4 - 1];
> + unsigned int ddrc_stat;
> +};
> +check_member(rk322x_grf, ddrc_stat, 0x604);
> +
> +struct rk322x_sgrf {
> + unsigned int soc_con[11];
> + unsigned int busdmac_con[4];
> +};
> +
> +/* GRF_GPIO0A_IOMUX */
> +enum {
> + GPIO0A7_SHIFT = 14,
> + GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
> + GPIO0A7_GPIO = 0,
> + GPIO0A7_I2C3_SDA,
> + GPIO0A7_HDMI_DDCSDA,
> +
> + GPIO0A6_SHIFT = 12,
> + GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
> + GPIO0A6_GPIO = 0,
> + GPIO0A6_I2C3_SCL,
> + GPIO0A6_HDMI_DDCSCL,
> +
> + GPIO0A3_SHIFT = 6,
> + GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
> + GPIO0A3_GPIO = 0,
> + GPIO0A3_I2C1_SDA,
> + GPIO0A3_SDIO_CMD,
> +
> + GPIO0A2_SHIFT = 4,
> + GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
> + GPIO0A2_GPIO = 0,
> + GPIO0A2_I2C1_SCL,
> +
> + GPIO0A1_SHIFT = 2,
> + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
> + GPIO0A1_GPIO = 0,
> + GPIO0A1_I2C0_SDA,
> +
> + GPIO0A0_SHIFT = 0,
> + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
> + GPIO0A0_GPIO = 0,
> + GPIO0A0_I2C0_SCL,
> +};
> +
> +/* GRF_GPIO0B_IOMUX */
> +enum {
> + GPIO0B7_SHIFT = 14,
> + GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
> + GPIO0B7_GPIO = 0,
> + GPIO0B7_HDMI_HDP,
> +
> + GPIO0B6_SHIFT = 12,
> + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
> + GPIO0B6_GPIO = 0,
> + GPIO0B6_I2S_SDI,
> + GPIO0B6_SPI_CSN0,
> +
> + GPIO0B5_SHIFT = 10,
> + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
> + GPIO0B5_GPIO = 0,
> + GPIO0B5_I2S_SDO,
> + GPIO0B5_SPI_RXD,
> +
> + GPIO0B3_SHIFT = 6,
> + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
> + GPIO0B3_GPIO = 0,
> + GPIO0B3_I2S1_LRCKRX,
> + GPIO0B3_SPI_TXD,
> +
> + GPIO0B1_SHIFT = 2,
> + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
> + GPIO0B1_GPIO = 0,
> + GPIO0B1_I2S_SCLK,
> + GPIO0B1_SPI_CLK,
> +
> + GPIO0B0_SHIFT = 0,
> + GPIO0B0_MASK = 3,
> + GPIO0B0_GPIO = 0,
> + GPIO0B0_I2S_MCLK,
> +};
> +
> +/* GRF_GPIO0C_IOMUX */
> +enum {
> + GPIO0C4_SHIFT = 8,
> + GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
> + GPIO0C4_GPIO = 0,
> + GPIO0C4_HDMI_CECSDA,
> +
> + GPIO0C1_SHIFT = 2,
> + GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
> + GPIO0C1_GPIO = 0,
> + GPIO0C1_UART0_RSTN,
> + GPIO0C1_CLK_OUT1,
> +};
> +
> +/* GRF_GPIO0D_IOMUX */
> +enum {
> + GPIO0D6_SHIFT = 12,
> + GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
> + GPIO0D6_GPIO = 0,
> + GPIO0D6_SDIO_PWREN,
> + GPIO0D6_PWM11,
> +
> +
> + GPIO0D4_SHIFT = 8,
> + GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
> + GPIO0D4_GPIO = 0,
> + GPIO0D4_PWM2,
> +
> + GPIO0D3_SHIFT = 6,
> + GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
> + GPIO0D3_GPIO = 0,
> + GPIO0D3_PWM1,
> +
> + GPIO0D2_SHIFT = 4,
> + GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
> + GPIO0D2_GPIO = 0,
> + GPIO0D2_PWM0,
> +};
> +
> +/* GRF_GPIO1A_IOMUX */
> +enum {
> + GPIO1A7_SHIFT = 14,
> + GPIO1A7_MASK = 1,
> + GPIO1A7_GPIO = 0,
> + GPIO1A7_SDMMC_WRPRT,
> +};
> +
> +/* GRF_GPIO1B_IOMUX */
> +enum {
> + GPIO1B7_SHIFT = 14,
> + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
> + GPIO1B7_GPIO = 0,
> + GPIO1B7_SDMMC_CMD,
> +
> + GPIO1B6_SHIFT = 12,
> + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
> + GPIO1B6_GPIO = 0,
> + GPIO1B6_SDMMC_PWREN,
> +
> + GPIO1B4_SHIFT = 8,
> + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
> + GPIO1B4_GPIO = 0,
> + GPIO1B4_SPI_CSN1,
> + GPIO1B4_PWM12,
> +
> + GPIO1B3_SHIFT = 6,
> + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
> + GPIO1B3_GPIO = 0,
> + GPIO1B3_UART1_RSTN,
> + GPIO1B3_PWM13,
> +
> + GPIO1B2_SHIFT = 4,
> + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
> + GPIO1B2_GPIO = 0,
> + GPIO1B2_UART1_SIN,
> + GPIO1B2_UART21_SIN,
> +
> + GPIO1B1_SHIFT = 2,
> + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
> + GPIO1B1_GPIO = 0,
> + GPIO1B1_UART1_SOUT,
> + GPIO1B1_UART21_SOUT,
> +};
> +
> +/* GRF_GPIO1C_IOMUX */
> +enum {
> + GPIO1C7_SHIFT = 14,
> + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
> + GPIO1C7_GPIO = 0,
> + GPIO1C7_NAND_CS3,
> + GPIO1C7_EMMC_RSTNOUT,
> +
> + GPIO1C6_SHIFT = 12,
> + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
> + GPIO1C6_GPIO = 0,
> + GPIO1C6_NAND_CS2,
> + GPIO1C6_EMMC_CMD,
> +
> +
> + GPIO1C5_SHIFT = 10,
> + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
> + GPIO1C5_GPIO = 0,
> + GPIO1C5_SDMMC_D3,
> + GPIO1C5_JTAG_TMS,
> +
> + GPIO1C4_SHIFT = 8,
> + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
> + GPIO1C4_GPIO = 0,
> + GPIO1C4_SDMMC_D2,
> + GPIO1C4_JTAG_TCK,
> +
> + GPIO1C3_SHIFT = 6,
> + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
> + GPIO1C3_GPIO = 0,
> + GPIO1C3_SDMMC_D1,
> + GPIO1C3_UART2_SIN,
> +
> + GPIO1C2_SHIFT = 4,
> + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
> + GPIO1C2_GPIO = 0,
> + GPIO1C2_SDMMC_D0,
> + GPIO1C2_UART2_SOUT,
> +
> + GPIO1C1_SHIFT = 2,
> + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
> + GPIO1C1_GPIO = 0,
> + GPIO1C1_SDMMC_DETN,
> +
> + GPIO1C0_SHIFT = 0,
> + GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
> + GPIO1C0_GPIO = 0,
> + GPIO1C0_SDMMC_CLKOUT,
> +};
> +
> +/* GRF_GPIO1D_IOMUX */
> +enum {
> + GPIO1D7_SHIFT = 14,
> + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
> + GPIO1D7_GPIO = 0,
> + GPIO1D7_NAND_D7,
> + GPIO1D7_EMMC_D7,
> +
> + GPIO1D6_SHIFT = 12,
> + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
> + GPIO1D6_GPIO = 0,
> + GPIO1D6_NAND_D6,
> + GPIO1D6_EMMC_D6,
> +
> + GPIO1D5_SHIFT = 10,
> + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
> + GPIO1D5_GPIO = 0,
> + GPIO1D5_NAND_D5,
> + GPIO1D5_EMMC_D5,
> +
> + GPIO1D4_SHIFT = 8,
> + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
> + GPIO1D4_GPIO = 0,
> + GPIO1D4_NAND_D4,
> + GPIO1D4_EMMC_D4,
> +
> + GPIO1D3_SHIFT = 6,
> + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
> + GPIO1D3_GPIO = 0,
> + GPIO1D3_NAND_D3,
> + GPIO1D3_EMMC_D3,
> +
> + GPIO1D2_SHIFT = 4,
> + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
> + GPIO1D2_GPIO = 0,
> + GPIO1D2_NAND_D2,
> + GPIO1D2_EMMC_D2,
> +
> + GPIO1D1_SHIFT = 2,
> + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
> + GPIO1D1_GPIO = 0,
> + GPIO1D1_NAND_D1,
> + GPIO1D1_EMMC_D1,
> +
> + GPIO1D0_SHIFT = 0,
> + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
> + GPIO1D0_GPIO = 0,
> + GPIO1D0_NAND_D0,
> + GPIO1D0_EMMC_D0,
> +};
> +
> +/* GRF_GPIO2A_IOMUX */
> +enum {
> + GPIO2A7_SHIFT = 14,
> + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
> + GPIO2A7_GPIO = 0,
> + GPIO2A7_NAND_DQS,
> + GPIO2A7_EMMC_CLKOUT,
> +
> + GPIO2A5_SHIFT = 10,
> + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
> + GPIO2A5_GPIO = 0,
> + GPIO2A5_NAND_WP,
> + GPIO2A5_EMMC_PWREN,
> +
> + GPIO2A4_SHIFT = 8,
> + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
> + GPIO2A4_GPIO = 0,
> + GPIO2A4_NAND_RDY,
> + GPIO2A4_EMMC_CMD,
> +
> + GPIO2A3_SHIFT = 6,
> + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
> + GPIO2A3_GPIO = 0,
> + GPIO2A3_NAND_RDN,
> + GPIO2A4_SPI1_CSN1,
> +
> + GPIO2A2_SHIFT = 4,
> + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
> + GPIO2A2_GPIO = 0,
> + GPIO2A2_NAND_WRN,
> + GPIO2A4_SPI1_CSN0,
> +
> + GPIO2A1_SHIFT = 2,
> + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
> + GPIO2A1_GPIO = 0,
> + GPIO2A1_NAND_CLE,
> + GPIO2A1_SPI1_TXD,
> +
> + GPIO2A0_SHIFT = 0,
> + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
> + GPIO2A0_GPIO = 0,
> + GPIO2A0_NAND_ALE,
> + GPIO2A0_SPI1_RXD,
> +};
> +
> +/* GRF_GPIO2B_IOMUX */
> +enum {
> + GPIO2B7_SHIFT = 14,
> + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
> + GPIO2B7_GPIO = 0,
> + GPIO2B7_GMAC_RXER,
> +
> + GPIO2B6_SHIFT = 12,
> + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
> + GPIO2B6_GPIO = 0,
> + GPIO2B6_GMAC_CLK,
> + GPIO2B6_MAC_LINK,
> +
> + GPIO2B5_SHIFT = 10,
> + GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
> + GPIO2B5_GPIO = 0,
> + GPIO2B5_GMAC_TXEN,
> +
> + GPIO2B4_SHIFT = 8,
> + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
> + GPIO2B4_GPIO = 0,
> + GPIO2B4_GMAC_MDIO,
> +
> + GPIO2B3_SHIFT = 6,
> + GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
> + GPIO2B3_GPIO = 0,
> + GPIO2B3_GMAC_RXCLK,
> +
> + GPIO2B2_SHIFT = 4,
> + GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
> + GPIO2B2_GPIO = 0,
> + GPIO2B2_GMAC_CRS,
> +
> + GPIO2B1_SHIFT = 2,
> + GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
> + GPIO2B1_GPIO = 0,
> + GPIO2B1_GMAC_TXCLK,
> +
> +
> + GPIO2B0_SHIFT = 0,
> + GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
> + GPIO2B0_GPIO = 0,
> + GPIO2B0_GMAC_RXDV,
> + GPIO2B0_MAC_SPEED_IOUT,
> +};
> +
> +/* GRF_GPIO2C_IOMUX */
> +enum {
> + GPIO2C7_SHIFT = 14,
> + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
> + GPIO2C7_GPIO = 0,
> + GPIO2C7_GMAC_TXD3,
> +
> + GPIO2C6_SHIFT = 12,
> + GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
> + GPIO2C6_GPIO = 0,
> + GPIO2C6_GMAC_TXD2,
> +
> + GPIO2C5_SHIFT = 10,
> + GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
> + GPIO2C5_GPIO = 0,
> + GPIO2C5_I2C2_SCL,
> + GPIO2C5_GMAC_RXD2,
> +
> + GPIO2C4_SHIFT = 8,
> + GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
> + GPIO2C4_GPIO = 0,
> + GPIO2C4_I2C2_SDA,
> + GPIO2C4_GMAC_RXD3,
> +
> + GPIO2C3_SHIFT = 6,
> + GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
> + GPIO2C3_GPIO = 0,
> + GPIO2C3_GMAC_TXD0,
> +
> + GPIO2C2_SHIFT = 4,
> + GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
> + GPIO2C2_GPIO = 0,
> + GPIO2C2_GMAC_TXD1,
> +
> + GPIO2C1_SHIFT = 2,
> + GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
> + GPIO2C1_GPIO = 0,
> + GPIO2C1_GMAC_RXD0,
> +
> + GPIO2C0_SHIFT = 0,
> + GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
> + GPIO2C0_GPIO = 0,
> + GPIO2C0_GMAC_RXD1,
> +};
> +
> +/* GRF_GPIO2D_IOMUX */
> +enum {
> + GPIO2D1_SHIFT = 2,
> + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
> + GPIO2D1_GPIO = 0,
> + GPIO2D1_GMAC_MDC,
> +
> + GPIO2D0_SHIFT = 0,
> + GPIO2D0_MASK = 3,
> + GPIO2D0_GPIO = 0,
> + GPIO2D0_GMAC_COL,
> +};
> +
> +/* GRF_GPIO3C_IOMUX */
> +enum {
> + GPIO3C6_SHIFT = 12,
> + GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
> + GPIO3C6_GPIO = 0,
> + GPIO3C6_DRV_VBUS1,
> +
> + GPIO3C5_SHIFT = 10,
> + GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
> + GPIO3C5_GPIO = 0,
> + GPIO3C5_PWM10,
> +
> + GPIO3C1_SHIFT = 2,
> + GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
> + GPIO3C1_GPIO = 0,
> + GPIO3C1_DRV_VBUS,
> +};
> +
> +/* GRF_GPIO3D_IOMUX */
> +enum {
> + GPIO3D2_SHIFT = 4,
> + GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
> + GPIO3D2_GPIO = 0,
> + GPIO3D2_PWM3,
> +};
> +
> +/* GRF_CON_IOMUX */
> +enum {
> + CON_IOMUX_GMAC_SHIFT = 15,
> + CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
> + CON_IOMUX_UART1SEL_SHIFT = 11,
> + CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
> + CON_IOMUX_UART2SEL_SHIFT = 8,
> + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
> + CON_IOMUX_UART2SEL_2 = 0,
> + CON_IOMUX_UART2SEL_21,
> + CON_IOMUX_EMMCSEL_SHIFT = 7,
> + CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
> + CON_IOMUX_PWM3SEL_SHIFT = 3,
> + CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
> + CON_IOMUX_PWM2SEL_SHIFT = 2,
> + CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
> + CON_IOMUX_PWM1SEL_SHIFT = 1,
> + CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
> + CON_IOMUX_PWM0SEL_SHIFT = 0,
> + CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
> +};
> +#endif
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index 150c68d..7c5d269 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -177,6 +177,16 @@ config PINCTRL_ROCKCHIP_RK3188
> the GPIO definitions and pin control functions for each available
> multiplex function.
>
> +config PINCTRL_ROCKCHIP_RK322X
> + bool "Rockchip rk322x pin control driver"
> + depends on DM
> + help
> + Support pin multiplexing control on Rockchip rk322x SoCs.
> +
> + The driver is controlled by a device tree node which contains both
> + the GPIO definitions and pin control functions for each available
> + multiplex function.
> +
> config PINCTRL_ROCKCHIP_RK3288
> bool "Rockchip rk3288 pin control driver"
> depends on DM
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index a1c655d..5251771 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -7,6 +7,7 @@
>
> obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3036) += pinctrl_rk3036.o
> obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3188) += pinctrl_rk3188.o
> +obj-$(CONFIG_PINCTRL_ROCKCHIP_RK322X) += pinctrl_rk322x.o
> obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3288) += pinctrl_rk3288.o
> obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3328) += pinctrl_rk3328.o
> obj-$(CONFIG_PINCTRL_ROCKCHIP_RK3368) += pinctrl_rk3368.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
> new file mode 100644
> index 0000000..5404008
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c
> @@ -0,0 +1,295 @@
> +/*
> + * Pinctrl driver for Rockchip 3036 SoCs
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/grf_rk322x.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/periph.h>
> +#include <dm/pinctrl.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct rk322x_pinctrl_priv {
> + struct rk322x_grf *grf;
> +};
> +
> +static void pinctrl_rk322x_pwm_config(struct rk322x_grf *grf, int pwm_id)
> +{
> + u32 mux_con = readl(&grf->con_iomux);
> +
> + switch (pwm_id) {
> + case PERIPH_ID_PWM0:
> + if (mux_con & CON_IOMUX_PWM0SEL_MASK)
> + rk_clrsetreg(&grf->gpio3c_iomux, GPIO3C5_MASK,
> + GPIO3C5_PWM10 << GPIO3C5_SHIFT);
> + else
> + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D2_MASK,
> + GPIO0D2_PWM0 << GPIO0D2_SHIFT);
> + break;
> + case PERIPH_ID_PWM1:
> + if (mux_con & CON_IOMUX_PWM1SEL_MASK)
> + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D6_MASK,
> + GPIO0D6_PWM11 << GPIO0D6_SHIFT);
> + else
> + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D3_MASK,
> + GPIO0D3_PWM1 << GPIO0D3_SHIFT);
> + break;
> + case PERIPH_ID_PWM2:
> + if (mux_con & CON_IOMUX_PWM2SEL_MASK)
> + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
> + GPIO1B4_PWM12 << GPIO1B4_SHIFT);
> + else
> + rk_clrsetreg(&grf->gpio0d_iomux, GPIO0D4_MASK,
> + GPIO0D4_PWM2 << GPIO0D4_SHIFT);
> + break;
> + case PERIPH_ID_PWM3:
> + if (mux_con & CON_IOMUX_PWM3SEL_MASK)
> + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B3_MASK,
> + GPIO1B3_PWM13 << GPIO1B3_SHIFT);
> + else
> + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D2_MASK,
> + GPIO3D2_PWM3 << GPIO3D2_SHIFT);
> + break;
> + default:
> + debug("pwm id = %d iomux error!\n", pwm_id);
> + break;
> + }
> +}
> +
> +static void pinctrl_rk322x_i2c_config(struct rk322x_grf *grf, int i2c_id)
> +{
> + switch (i2c_id) {
> + case PERIPH_ID_I2C0:
> + rk_clrsetreg(&grf->gpio0a_iomux,
> + GPIO0A1_MASK | GPIO0A0_MASK,
> + GPIO0A1_I2C0_SDA << GPIO0A1_SHIFT |
> + GPIO0A0_I2C0_SCL << GPIO0A0_SHIFT);
> +
> + break;
> + case PERIPH_ID_I2C1:
> + rk_clrsetreg(&grf->gpio0a_iomux,
> + GPIO0A3_MASK | GPIO0A2_MASK,
> + GPIO0A3_I2C1_SDA << GPIO0A3_SHIFT |
> + GPIO0A2_I2C1_SCL << GPIO0A2_SHIFT);
> + break;
> + case PERIPH_ID_I2C2:
> + rk_clrsetreg(&grf->gpio2c_iomux,
> + GPIO2C5_MASK | GPIO2C4_MASK,
> + GPIO2C5_I2C2_SCL << GPIO2C5_SHIFT |
> + GPIO2C4_I2C2_SDA << GPIO2C4_SHIFT);
> + break;
> + case PERIPH_ID_I2C3:
> + rk_clrsetreg(&grf->gpio0a_iomux,
> + GPIO0A7_MASK | GPIO0A6_MASK,
> + GPIO0A7_I2C3_SDA << GPIO0A7_SHIFT |
> + GPIO0A6_I2C3_SCL << GPIO0A6_SHIFT);
> +
> + break;
> + }
> +}
> +
> +static void pinctrl_rk322x_spi_config(struct rk322x_grf *grf, int cs)
> +{
> + switch (cs) {
> + case 0:
> + rk_clrsetreg(&grf->gpio0b_iomux, GPIO0B6_MASK,
> + GPIO0B6_SPI_CSN0 << GPIO0B6_SHIFT);
> + break;
> + case 1:
> + rk_clrsetreg(&grf->gpio1b_iomux, GPIO1B4_MASK,
> + GPIO1B4_SPI_CSN1 << GPIO1B4_SHIFT);
> + break;
> + }
> + rk_clrsetreg(&grf->gpio0b_iomux,
> + GPIO0B1_MASK | GPIO0B3_MASK | GPIO0B5_MASK,
> + GPIO0B5_SPI_RXD << GPIO0B5_SHIFT |
> + GPIO0B3_SPI_TXD << GPIO0B3_SHIFT |
> + GPIO0B1_SPI_CLK << GPIO0B1_SHIFT);
> +}
> +
> +static void pinctrl_rk322x_uart_config(struct rk322x_grf *grf, int uart_id)
> +{
> + u32 mux_con = readl(&grf->con_iomux);
> +
> + switch (uart_id) {
> + case PERIPH_ID_UART1:
> + if (!(mux_con & CON_IOMUX_UART1SEL_MASK))
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B1_MASK | GPIO1B2_MASK,
> + GPIO1B1_UART1_SOUT << GPIO1B1_SHIFT |
> + GPIO1B2_UART1_SIN << GPIO1B2_SHIFT);
> + break;
> + case PERIPH_ID_UART2:
> + if (mux_con & CON_IOMUX_UART2SEL_MASK)
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B1_MASK | GPIO1B2_MASK,
> + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT |
> + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT);
> + else
> + rk_clrsetreg(&grf->gpio1c_iomux,
> + GPIO1C3_MASK | GPIO1C2_MASK,
> + GPIO1C3_UART2_SIN << GPIO1C3_SHIFT |
> + GPIO1C2_UART2_SOUT << GPIO1C2_SHIFT);
> + break;
> + }
> +}
> +
> +static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id)
> +{
> + switch (mmc_id) {
> + case PERIPH_ID_EMMC:
> + rk_clrsetreg(&grf->gpio1d_iomux, 0xffff,
> + GPIO1D7_EMMC_D7 << GPIO1D7_SHIFT |
> + GPIO1D6_EMMC_D6 << GPIO1D6_SHIFT |
> + GPIO1D5_EMMC_D5 << GPIO1D5_SHIFT |
> + GPIO1D4_EMMC_D4 << GPIO1D4_SHIFT |
> + GPIO1D3_EMMC_D3 << GPIO1D3_SHIFT |
> + GPIO1D2_EMMC_D2 << GPIO1D2_SHIFT |
> + GPIO1D1_EMMC_D1 << GPIO1D1_SHIFT |
> + GPIO1D0_EMMC_D0 << GPIO1D0_SHIFT);
> + rk_clrsetreg(&grf->gpio2a_iomux,
> + GPIO2A5_MASK | GPIO2A7_MASK,
> + GPIO2A5_EMMC_PWREN << GPIO2A5_SHIFT |
> + GPIO2A7_EMMC_CLKOUT << GPIO2A7_SHIFT);
> + rk_clrsetreg(&grf->gpio1c_iomux,
> + GPIO1C6_MASK | GPIO1C7_MASK,
> + GPIO1C6_EMMC_CMD << GPIO1C6_SHIFT |
> + GPIO1C7_EMMC_RSTNOUT << GPIO1C6_SHIFT);
> + break;
> + case PERIPH_ID_SDCARD:
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B6_MASK | GPIO1B7_MASK,
> + GPIO1B6_SDMMC_PWREN << GPIO1B6_SHIFT |
> + GPIO1B7_SDMMC_CMD << GPIO1B6_SHIFT);
> + rk_clrsetreg(&grf->gpio1c_iomux, 0xfff,
> + GPIO1C5_SDMMC_D3 << GPIO1C5_SHIFT |
> + GPIO1C4_SDMMC_D2 << GPIO1C4_SHIFT |
> + GPIO1C3_SDMMC_D1 << GPIO1C3_SHIFT |
> + GPIO1C2_SDMMC_D0 << GPIO1C2_SHIFT |
> + GPIO1C1_SDMMC_DETN << GPIO1C1_SHIFT |
> + GPIO1C0_SDMMC_CLKOUT << GPIO1C0_SHIFT);
> + break;
> + }
> +}
> +
> +static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags)
> +{
> + struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
> +
> + debug("%s: func=%x, flags=%x\n", __func__, func, flags);
> + switch (func) {
> + case PERIPH_ID_PWM0:
> + case PERIPH_ID_PWM1:
> + case PERIPH_ID_PWM2:
> + case PERIPH_ID_PWM3:
> + pinctrl_rk322x_pwm_config(priv->grf, func);
> + break;
> + case PERIPH_ID_I2C0:
> + case PERIPH_ID_I2C1:
> + case PERIPH_ID_I2C2:
> + pinctrl_rk322x_i2c_config(priv->grf, func);
> + break;
> + case PERIPH_ID_SPI0:
> + pinctrl_rk322x_spi_config(priv->grf, flags);
> + break;
> + case PERIPH_ID_UART0:
> + case PERIPH_ID_UART1:
> + case PERIPH_ID_UART2:
> + pinctrl_rk322x_uart_config(priv->grf, func);
> + break;
> + case PERIPH_ID_SDMMC0:
> + case PERIPH_ID_SDMMC1:
> + pinctrl_rk322x_sdmmc_config(priv->grf, func);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int rk322x_pinctrl_get_periph_id(struct udevice *dev,
> + struct udevice *periph)
> +{
> + u32 cell[3];
> + int ret;
> +
> + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
> + "interrupts", cell, ARRAY_SIZE(cell));
> + if (ret < 0)
> + return -EINVAL;
> +
> + switch (cell[1]) {
> + case 12:
> + return PERIPH_ID_SDCARD;
> + case 14:
> + return PERIPH_ID_EMMC;
> + case 36:
> + return PERIPH_ID_I2C0;
> + case 37:
> + return PERIPH_ID_I2C1;
> + case 38:
> + return PERIPH_ID_I2C2;
> + case 49:
> + return PERIPH_ID_SPI0;
> + case 50:
> + return PERIPH_ID_PWM0;
> + case 55:
> + return PERIPH_ID_UART0;
> + case 56:
> + return PERIPH_ID_UART1;
> + case 57:
> + return PERIPH_ID_UART2;
> + }
> + return -ENOENT;
> +}
> +
> +static int rk322x_pinctrl_set_state_simple(struct udevice *dev,
> + struct udevice *periph)
> +{
> + int func;
> +
> + func = rk322x_pinctrl_get_periph_id(dev, periph);
> + if (func < 0)
> + return func;
> + return rk322x_pinctrl_request(dev, func, 0);
> +}
> +
> +static struct pinctrl_ops rk322x_pinctrl_ops = {
> + .set_state_simple = rk322x_pinctrl_set_state_simple,
> + .request = rk322x_pinctrl_request,
> + .get_periph_id = rk322x_pinctrl_get_periph_id,
> +};
> +
> +static int rk322x_pinctrl_probe(struct udevice *dev)
> +{
> + struct rk322x_pinctrl_priv *priv = dev_get_priv(dev);
> +
> + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + debug("%s: grf=%p\n", __func__, priv->grf);
> + return 0;
> +}
> +
> +static const struct udevice_id rk322x_pinctrl_ids[] = {
> + { .compatible = "rockchip,rk322x-pinctrl" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pinctrl_rk322x) = {
> + .name = "pinctrl_rk322x",
> + .id = UCLASS_PINCTRL,
> + .of_match = rk322x_pinctrl_ids,
> + .priv_auto_alloc_size = sizeof(struct rk322x_pinctrl_priv),
> + .ops = &rk322x_pinctrl_ops,
> + .bind = dm_scan_fdt_dev,
> + .probe = rk322x_pinctrl_probe,
> +};
>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,4/7] rockchip: rk322x: add dts file
2017-06-09 12:28 ` [U-Boot] [PATCH 4/7] rockchip: rk322x: add dts file Kever Yang
@ 2017-06-12 14:18 ` Philipp Tomsich
0 siblings, 0 replies; 20+ messages in thread
From: Philipp Tomsich @ 2017-06-12 14:18 UTC (permalink / raw)
To: u-boot
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Fri, 9 Jun 2017, Kever Yang wrote:
> The dts files are from kernel and with modify to adapt U-Boot.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/dts/rk3229-evb.dts | 77 ++++
> arch/arm/dts/rk322x.dtsi | 710 +++++++++++++++++++++++++++++++++
> include/dt-bindings/clock/rk3228-cru.h | 247 ++++++++++++
> 3 files changed, 1034 insertions(+)
> create mode 100644 arch/arm/dts/rk3229-evb.dts
> create mode 100644 arch/arm/dts/rk322x.dtsi
> create mode 100644 include/dt-bindings/clock/rk3228-cru.h
>
> diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
> new file mode 100644
> index 0000000..ccdac1c
> --- /dev/null
> +++ b/arch/arm/dts/rk3229-evb.dts
> @@ -0,0 +1,77 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
> + *
> + * SPDX-License-Identifier: GPL-2.0+ X11
> + */
> +
> +/dts-v1/;
> +
> +#include "rk322x.dtsi"
> +
> +/ {
> + model = "Rockchip RK3229 Evaluation board";
> + compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
> +
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + memory at 60000000 {
> + device_type = "memory";
> + reg = <0x60000000 0x40000000>;
> + };
> +
> + ext_gmac: ext_gmac {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + clock-output-names = "ext_gmac";
> + #clock-cells = <0>;
> + };
> +
> + vcc_phy: vcc-phy-regulator {
> + compatible = "regulator-fixed";
> + enable-active-high;
> + regulator-name = "vcc_phy";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +};
> +
> +&dmc {
> + rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>;
> + rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
> + 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
> + 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
> + 0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
> + 0x0 0x924>;
> + rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
> + rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
> + 0 300 3 0 120>;
> +};
> +
> +&gmac {
> + assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
> + assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
> + clock_in_out = "input";
> + phy-supply = <&vcc_phy>;
> + phy-mode = "rgmii";
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmii_pins>;
> + snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
> + snps,reset-active-low;
> + snps,reset-delays-us = <0 10000 1000000>;
> + tx_delay = <0x30>;
> + rx_delay = <0x10>;
> + status = "okay";
> +};
> +
> +&emmc {
> + u-boot,dm-pre-reloc;
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
> new file mode 100644
> index 0000000..7237da4
> --- /dev/null
> +++ b/arch/arm/dts/rk322x.dtsi
> @@ -0,0 +1,710 @@
> +/*
> + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/clock/rk3228-cru.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at f00 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf00>;
> + resets = <&cru SRST_CORE0>;
> + operating-points = <
> + /* KHz uV */
> + 816000 1000000
> + >;
> + #cooling-cells = <2>; /* min followed by max */
> + clock-latency = <40000>;
> + clocks = <&cru ARMCLK>;
> + };
> +
> + cpu1: cpu at f01 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf01>;
> + resets = <&cru SRST_CORE1>;
> + };
> +
> + cpu2: cpu at f02 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf02>;
> + resets = <&cru SRST_CORE2>;
> + };
> +
> + cpu3: cpu at f03 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf03>;
> + resets = <&cru SRST_CORE3>;
> + };
> + };
> +
> + amba {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + pdma: pdma at 110f0000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x110f0000 0x4000>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + clocks = <&cru ACLK_DMAC>;
> + clock-names = "apb_pclk";
> + };
> + };
> +
> + arm-pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + arm,cpu-registers-not-fw-configured;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + clock-frequency = <24000000>;
> + };
> +
> + xin24m: oscillator {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "xin24m";
> + #clock-cells = <0>;
> + };
> +
> + bus_intmem at 10080000 {
> + compatible = "mmio-sram";
> + reg = <0x10080000 0x9000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x10080000 0x9000>;
> + smp-sram at 0 {
> + compatible = "rockchip,rk322x-smp-sram";
> + reg = <0x00 0x10>;
> + };
> + ddr_sram: ddr-sram at 1000 {
> + compatible = "rockchip,rk322x-ddr-sram";
> + reg = <0x1000 0x8000>;
> + };
> + };
> +
> + i2s1: i2s1 at 100b0000 {
> + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
> + reg = <0x100b0000 0x4000>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "i2s_clk", "i2s_hclk";
> + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
> + dmas = <&pdma 14>, <&pdma 15>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s1_bus>;
> + status = "disabled";
> + };
> +
> + i2s0: i2s0 at 100c0000 {
> + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
> + reg = <0x100c0000 0x4000>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "i2s_clk", "i2s_hclk";
> + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
> + dmas = <&pdma 11>, <&pdma 12>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + i2s2: i2s2 at 100e0000 {
> + compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
> + reg = <0x100e0000 0x4000>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "i2s_clk", "i2s_hclk";
> + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
> + dmas = <&pdma 0>, <&pdma 1>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + grf: syscon at 11000000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3228-grf", "syscon";
> + reg = <0x11000000 0x1000>;
> + };
> +
> + uart0: serial at 11010000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x11010000 0x100>;
> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> + clock-names = "baudclk", "apb_pclk";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart1: serial at 11020000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x11020000 0x100>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
> + clock-names = "baudclk", "apb_pclk";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart2: serial at 11030000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x11030000 0x100>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> + clock-names = "baudclk", "apb_pclk";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c at 11050000 {
> + compatible = "rockchip,rk3228-i2c";
> + reg = <0x11050000 0x1000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "i2c";
> + clocks = <&cru PCLK_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_xfer>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c at 11060000 {
> + compatible = "rockchip,rk3228-i2c";
> + reg = <0x11060000 0x1000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "i2c";
> + clocks = <&cru PCLK_I2C1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_xfer>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c at 11070000 {
> + compatible = "rockchip,rk3228-i2c";
> + reg = <0x11070000 0x1000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "i2c";
> + clocks = <&cru PCLK_I2C2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_xfer>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c at 11080000 {
> + compatible = "rockchip,rk3228-i2c";
> + reg = <0x11080000 0x1000>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clock-names = "i2c";
> + clocks = <&cru PCLK_I2C3>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c3_xfer>;
> + status = "disabled";
> + };
> +
> + pwm0: pwm at 110b0000 {
> + compatible = "rockchip,rk3288-pwm";
> + reg = <0x110b0000 0x10>;
> + #pwm-cells = <3>;
> + clocks = <&cru PCLK_PWM>;
> + clock-names = "pwm";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0_pin>;
> + status = "disabled";
> + };
> +
> + pwm1: pwm at 110b0010 {
> + compatible = "rockchip,rk3288-pwm";
> + reg = <0x110b0010 0x10>;
> + #pwm-cells = <3>;
> + clocks = <&cru PCLK_PWM>;
> + clock-names = "pwm";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1_pin>;
> + status = "disabled";
> + };
> +
> + pwm2: pwm at 110b0020 {
> + compatible = "rockchip,rk3288-pwm";
> + reg = <0x110b0020 0x10>;
> + #pwm-cells = <3>;
> + clocks = <&cru PCLK_PWM>;
> + clock-names = "pwm";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2_pin>;
> + status = "disabled";
> + };
> +
> + pwm3: pwm at 110b0030 {
> + compatible = "rockchip,rk3288-pwm";
> + reg = <0x110b0030 0x10>;
> + #pwm-cells = <2>;
> + clocks = <&cru PCLK_PWM>;
> + clock-names = "pwm";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm3_pin>;
> + status = "disabled";
> + };
> +
> + timer: timer at 110c0000 {
> + compatible = "rockchip,rk3288-timer";
> + reg = <0x110c0000 0x20>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&xin24m>, <&cru PCLK_TIMER>;
> + clock-names = "timer", "pclk";
> + };
> +
> + cru: clock-controller at 110e0000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3228-cru";
> + reg = <0x110e0000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + assigned-clocks = <&cru PLL_GPLL>;
> + assigned-clock-rates = <594000000>;
> + };
> +
> + thermal-zones {
> + cpu_thermal: cpu-thermal {
> + polling-delay-passive = <100>; /* milliseconds */
> + polling-delay = <5000>; /* milliseconds */
> +
> + thermal-sensors = <&tsadc 0>;
> +
> + trips {
> + cpu_alert0: cpu_alert0 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "passive";
> + };
> + cpu_alert1: cpu_alert1 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "passive";
> + };
> + cpu_crit: cpu_crit {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <2000>; /* millicelsius */
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert0>;
> + cooling-device =
> + <&cpu0 THERMAL_NO_LIMIT 6>;
> + };
> + map1 {
> + trip = <&cpu_alert1>;
> + cooling-device =
> + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> + };
> +
> + tsadc: tsadc at 11150000 {
> + compatible = "rockchip,rk3228-tsadc";
> + reg = <0x11150000 0x100>;
> + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
> + clock-names = "tsadc", "apb_pclk";
> + resets = <&cru SRST_TSADC>;
> + reset-names = "tsadc-apb";
> + pinctrl-names = "init", "default", "sleep";
> + pinctrl-0 = <&otp_gpio>;
> + pinctrl-1 = <&otp_out>;
> + pinctrl-2 = <&otp_gpio>;
> + #thermal-sensor-cells = <0>;
> + rockchip,hw-tshut-temp = <95000>;
> + status = "disabled";
> + };
> +
> + emmc: dwmmc at 30020000 {
> + compatible = "rockchip,rk3288-dw-mshc";
> + reg = <0x30020000 0x4000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <37500000>;
> + max-frequency = <37500000>;
> + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
> + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
> + bus-width = <8>;
> + default-sample-phase = <158>;
> + num-slots = <1>;
> + fifo-depth = <0x100>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
> + resets = <&cru SRST_EMMC>;
> + reset-names = "reset";
> + status = "disabled";
> + };
> +
> + gmac: ethernet at 30200000 {
> + compatible = "rockchip,rk3228-gmac";
> + reg = <0x30200000 0x10000>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
> + <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
> + <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
> + <&cru PCLK_GMAC>;
> + clock-names = "stmmaceth", "mac_clk_rx",
> + "mac_clk_tx", "clk_mac_ref",
> + "clk_mac_refout", "aclk_mac",
> + "pclk_mac";
> + resets = <&cru SRST_GMAC>;
> + reset-names = "stmmaceth";
> + rockchip,grf = <&grf>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller at 32010000 {
> + compatible = "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> +
> + reg = <0x32011000 0x1000>,
> + <0x32012000 0x2000>,
> + <0x32014000 0x2000>,
> + <0x32016000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + pinctrl: pinctrl {
> + compatible = "rockchip,rk3228-pinctrl";
> + rockchip,grf = <&grf>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + gpio0: gpio0 at 11110000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x11110000 0x100>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO0>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio1: gpio1 at 11120000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x11120000 0x100>;
> + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO1>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio2 at 11130000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x11130000 0x100>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO2>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio3 at 11140000 {
> + compatible = "rockchip,gpio-bank";
> + reg = <0x11140000 0x100>;
> + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO3>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + pcfg_pull_up: pcfg-pull-up {
> + bias-pull-up;
> + };
> +
> + pcfg_pull_down: pcfg-pull-down {
> + bias-pull-down;
> + };
> +
> + pcfg_pull_none: pcfg-pull-none {
> + bias-disable;
> + };
> +
> + pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
> + drive-strength = <12>;
> + };
> +
> + emmc {
> + emmc_clk: emmc-clk {
> + rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
> + };
> +
> + emmc_cmd: emmc-cmd {
> + rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
> + };
> +
> + emmc_bus8: emmc-bus8 {
> + rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> +
> + gmac {
> + rgmii_pins: rgmii-pins {
> + rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
> + <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
> + <2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + rmii_pins: rmii-pins {
> + rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
> + <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + phy_pins: phy-pins {
> + rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
> + <2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c0 {
> + i2c0_xfer: i2c0-xfer {
> + rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c1 {
> + i2c1_xfer: i2c1-xfer {
> + rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c2 {
> + i2c2_xfer: i2c2-xfer {
> + rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c3 {
> + i2c3_xfer: i2c3-xfer {
> + rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + i2s1 {
> + i2s1_bus: i2s1-bus {
> + rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
> + <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
> + <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
> + <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
> + <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + pwm0 {
> + pwm0_pin: pwm0-pin {
> + rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + pwm1 {
> + pwm1_pin: pwm1-pin {
> + rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> +
> + pwm2 {
> + pwm2_pin: pwm2-pin {
> + rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> +
> + pwm3 {
> + pwm3_pin: pwm3-pin {
> + rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> +
> + tsadc {
> + otp_gpio: otp-gpio {
> + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + otp_out: otp-out {
> + rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> +
> + uart0 {
> + uart0_xfer: uart0-xfer {
> + rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
> + <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + uart0_cts: uart0-cts {
> + rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + uart0_rts: uart0-rts {
> + rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + uart1 {
> + uart1_xfer: uart1-xfer {
> + rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
> + <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + uart1_cts: uart1-cts {
> + rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + uart1_rts: uart1-rts {
> + rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> +
> + uart2 {
> + uart2_xfer: uart2-xfer {
> + rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
> + <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
> + };
> +
> + uart2_cts: uart2-cts {
> + rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
> + };
> +
> + uart2_rts: uart2-rts {
> + rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
> + };
> + };
> + };
> +
> + dmc: dmc at 11200000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3228-dmc", "syscon";
> + rockchip,cru = <&cru>;
> + rockchip,grf = <&grf>;
> + rockchip,msch = <&service_msch>;
> + reg = <0x11200000 0x3fc
> + 0x12000000 0x400>;
> + rockchip,sram = <&ddr_sram>;
> + };
> +
> + service_msch: syscon at 31090000 {
> + u-boot,dm-pre-reloc;
> + compatible = "rockchip,rk3228-msch", "syscon";
> + reg = <0x31090000 0x2000>;
> + };
> +};
> diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
> new file mode 100644
> index 0000000..b27e2b1
> --- /dev/null
> +++ b/include/dt-bindings/clock/rk3228-cru.h
> @@ -0,0 +1,247 @@
> +/*
> + * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
> + * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
> +
> +/* core clocks */
> +#define PLL_APLL 1
> +#define PLL_DPLL 2
> +#define PLL_CPLL 3
> +#define PLL_GPLL 4
> +#define ARMCLK 5
> +
> +/* sclk gates (special clocks) */
> +#define SCLK_SPI0 65
> +#define SCLK_NANDC 67
> +#define SCLK_SDMMC 68
> +#define SCLK_SDIO 69
> +#define SCLK_EMMC 71
> +#define SCLK_TSADC 72
> +#define SCLK_UART0 77
> +#define SCLK_UART1 78
> +#define SCLK_UART2 79
> +#define SCLK_I2S0 80
> +#define SCLK_I2S1 81
> +#define SCLK_I2S2 82
> +#define SCLK_SPDIF 83
> +#define SCLK_TIMER0 85
> +#define SCLK_TIMER1 86
> +#define SCLK_TIMER2 87
> +#define SCLK_TIMER3 88
> +#define SCLK_TIMER4 89
> +#define SCLK_TIMER5 90
> +#define SCLK_I2S_OUT 113
> +#define SCLK_SDMMC_DRV 114
> +#define SCLK_SDIO_DRV 115
> +#define SCLK_EMMC_DRV 117
> +#define SCLK_SDMMC_SAMPLE 118
> +#define SCLK_SDIO_SAMPLE 119
> +#define SCLK_EMMC_SAMPLE 121
> +#define SCLK_VOP 122
> +#define SCLK_HDMI_HDCP 123
> +#define SCLK_MAC_SRC 124
> +#define SCLK_MAC_EXTCLK 125
> +#define SCLK_MAC 126
> +#define SCLK_MAC_REFOUT 127
> +#define SCLK_MAC_REF 128
> +#define SCLK_MAC_RX 129
> +#define SCLK_MAC_TX 130
> +#define SCLK_MAC_PHY 131
> +#define SCLK_MAC_OUT 132
> +
> +/* dclk gates */
> +#define DCLK_VOP 190
> +#define DCLK_HDMI_PHY 191
> +
> +/* aclk gates */
> +#define ACLK_DMAC 194
> +#define ACLK_PERI 210
> +#define ACLK_VOP 211
> +#define ACLK_GMAC 212
> +
> +/* pclk gates */
> +#define PCLK_GPIO0 320
> +#define PCLK_GPIO1 321
> +#define PCLK_GPIO2 322
> +#define PCLK_GPIO3 323
> +#define PCLK_GRF 329
> +#define PCLK_I2C0 332
> +#define PCLK_I2C1 333
> +#define PCLK_I2C2 334
> +#define PCLK_I2C3 335
> +#define PCLK_SPI0 338
> +#define PCLK_UART0 341
> +#define PCLK_UART1 342
> +#define PCLK_UART2 343
> +#define PCLK_TSADC 344
> +#define PCLK_PWM 350
> +#define PCLK_TIMER 353
> +#define PCLK_PERI 363
> +#define PCLK_HDMI_CTRL 364
> +#define PCLK_HDMI_PHY 365
> +#define PCLK_GMAC 367
> +
> +/* hclk gates */
> +#define HCLK_I2S0_8CH 442
> +#define HCLK_I2S1_8CH 443
> +#define HCLK_I2S2_2CH 444
> +#define HCLK_SPDIF_8CH 445
> +#define HCLK_VOP 452
> +#define HCLK_NANDC 453
> +#define HCLK_SDMMC 456
> +#define HCLK_SDIO 457
> +#define HCLK_EMMC 459
> +#define HCLK_PERI 478
> +
> +#define CLK_NR_CLKS (HCLK_PERI + 1)
> +
> +/* soft-reset indices */
> +#define SRST_CORE0_PO 0
> +#define SRST_CORE1_PO 1
> +#define SRST_CORE2_PO 2
> +#define SRST_CORE3_PO 3
> +#define SRST_CORE0 4
> +#define SRST_CORE1 5
> +#define SRST_CORE2 6
> +#define SRST_CORE3 7
> +#define SRST_CORE0_DBG 8
> +#define SRST_CORE1_DBG 9
> +#define SRST_CORE2_DBG 10
> +#define SRST_CORE3_DBG 11
> +#define SRST_TOPDBG 12
> +#define SRST_ACLK_CORE 13
> +#define SRST_NOC 14
> +#define SRST_L2C 15
> +
> +#define SRST_CPUSYS_H 18
> +#define SRST_BUSSYS_H 19
> +#define SRST_SPDIF 20
> +#define SRST_INTMEM 21
> +#define SRST_ROM 22
> +#define SRST_OTG_ADP 23
> +#define SRST_I2S0 24
> +#define SRST_I2S1 25
> +#define SRST_I2S2 26
> +#define SRST_ACODEC_P 27
> +#define SRST_DFIMON 28
> +#define SRST_MSCH 29
> +#define SRST_EFUSE1024 30
> +#define SRST_EFUSE256 31
> +
> +#define SRST_GPIO0 32
> +#define SRST_GPIO1 33
> +#define SRST_GPIO2 34
> +#define SRST_GPIO3 35
> +#define SRST_PERIPH_NOC_A 36
> +#define SRST_PERIPH_NOC_BUS_H 37
> +#define SRST_PERIPH_NOC_P 38
> +#define SRST_UART0 39
> +#define SRST_UART1 40
> +#define SRST_UART2 41
> +#define SRST_PHYNOC 42
> +#define SRST_I2C0 43
> +#define SRST_I2C1 44
> +#define SRST_I2C2 45
> +#define SRST_I2C3 46
> +
> +#define SRST_PWM 48
> +#define SRST_A53_GIC 49
> +#define SRST_DAP 51
> +#define SRST_DAP_NOC 52
> +#define SRST_CRYPTO 53
> +#define SRST_SGRF 54
> +#define SRST_GRF 55
> +#define SRST_GMAC 56
> +#define SRST_PERIPH_NOC_H 58
> +#define SRST_MACPHY 63
> +
> +#define SRST_DMA 64
> +#define SRST_NANDC 68
> +#define SRST_USBOTG 69
> +#define SRST_OTGC 70
> +#define SRST_USBHOST0 71
> +#define SRST_HOST_CTRL0 72
> +#define SRST_USBHOST1 73
> +#define SRST_HOST_CTRL1 74
> +#define SRST_USBHOST2 75
> +#define SRST_HOST_CTRL2 76
> +#define SRST_USBPOR0 77
> +#define SRST_USBPOR1 78
> +#define SRST_DDRMSCH 79
> +
> +#define SRST_SMART_CARD 80
> +#define SRST_SDMMC 81
> +#define SRST_SDIO 82
> +#define SRST_EMMC 83
> +#define SRST_SPI 84
> +#define SRST_TSP_H 85
> +#define SRST_TSP 86
> +#define SRST_TSADC 87
> +#define SRST_DDRPHY 88
> +#define SRST_DDRPHY_P 89
> +#define SRST_DDRCTRL 90
> +#define SRST_DDRCTRL_P 91
> +#define SRST_HOST0_ECHI 92
> +#define SRST_HOST1_ECHI 93
> +#define SRST_HOST2_ECHI 94
> +#define SRST_VOP_NOC_A 95
> +
> +#define SRST_HDMI_P 96
> +#define SRST_VIO_ARBI_H 97
> +#define SRST_IEP_NOC_A 98
> +#define SRST_VIO_NOC_H 99
> +#define SRST_VOP_A 100
> +#define SRST_VOP_H 101
> +#define SRST_VOP_D 102
> +#define SRST_UTMI0 103
> +#define SRST_UTMI1 104
> +#define SRST_UTMI2 105
> +#define SRST_UTMI3 106
> +#define SRST_RGA 107
> +#define SRST_RGA_NOC_A 108
> +#define SRST_RGA_A 109
> +#define SRST_RGA_H 110
> +#define SRST_HDCP_A 111
> +
> +#define SRST_VPU_A 112
> +#define SRST_VPU_H 113
> +#define SRST_VPU_NOC_A 116
> +#define SRST_VPU_NOC_H 117
> +#define SRST_RKVDEC_A 118
> +#define SRST_RKVDEC_NOC_A 119
> +#define SRST_RKVDEC_H 120
> +#define SRST_RKVDEC_NOC_H 121
> +#define SRST_RKVDEC_CORE 122
> +#define SRST_RKVDEC_CABAC 123
> +#define SRST_IEP_A 124
> +#define SRST_IEP_H 125
> +#define SRST_GPU_A 126
> +#define SRST_GPU_NOC_A 127
> +
> +#define SRST_CORE_DBG 128
> +#define SRST_DBG_P 129
> +#define SRST_TIMER0 130
> +#define SRST_TIMER1 131
> +#define SRST_TIMER2 132
> +#define SRST_TIMER3 133
> +#define SRST_TIMER4 134
> +#define SRST_TIMER5 135
> +#define SRST_VIO_H2P 136
> +#define SRST_HDMIPHY 139
> +#define SRST_VDAC 140
> +#define SRST_TIMER_6CH_P 141
> +
> +#endif
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,5/7] rockchip: rk322x: add basic soc support
2017-06-09 12:28 ` [U-Boot] [PATCH 5/7] rockchip: rk322x: add basic soc support Kever Yang
@ 2017-06-12 14:19 ` Philipp Tomsich
0 siblings, 0 replies; 20+ messages in thread
From: Philipp Tomsich @ 2017-06-12 14:19 UTC (permalink / raw)
To: u-boot
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Fri, 9 Jun 2017, Kever Yang wrote:
> Enable soc support for SPL and U-boot skeleton.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/include/asm/arch-rockchip/clock.h | 1 +
> arch/arm/mach-rockchip/Kconfig | 13 +++
> arch/arm/mach-rockchip/Makefile | 3 +
> arch/arm/mach-rockchip/rk322x-board-spl.c | 77 +++++++++++++
> arch/arm/mach-rockchip/rk322x-board.c | 159 ++++++++++++++++++++++++++
> arch/arm/mach-rockchip/rk322x/Kconfig | 18 +++
> arch/arm/mach-rockchip/rk322x/Makefile | 9 ++
> arch/arm/mach-rockchip/rk322x/clk_rk322x.c | 33 ++++++
> arch/arm/mach-rockchip/rk322x/syscon_rk322x.c | 22 ++++
> include/configs/rk322x_common.h | 92 +++++++++++++++
> 10 files changed, 427 insertions(+)
> create mode 100644 arch/arm/mach-rockchip/rk322x-board-spl.c
> create mode 100644 arch/arm/mach-rockchip/rk322x-board.c
> create mode 100644 arch/arm/mach-rockchip/rk322x/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk322x/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk322x/clk_rk322x.c
> create mode 100644 arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
> create mode 100644 include/configs/rk322x_common.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index b06bb6c..641df58 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -19,6 +19,7 @@ enum {
> ROCKCHIP_SYSCON_PMUGRF,
> ROCKCHIP_SYSCON_PMUSGRF,
> ROCKCHIP_SYSCON_CIC,
> + ROCKCHIP_SYSCON_MSCH,
> };
>
> /* Standard Rockchip clock numbers */
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 9b2ef29..33bd17f 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -28,6 +28,19 @@ config ROCKCHIP_RK3188
> Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
> UART, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK322X
> + bool "Support Rockchip RK3228/RK3229"
> + select CPU_V7
> + select SUPPORT_SPL
> + select SPL
> + select ROCKCHIP_BROM_HELPER
> + select DEBUG_UART_BOARD_INIT
> + help
> + The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
> + including NEON and GPU, Mali-400 graphics, several DDR3 options
> + and video codec support. Peripherals include Gigabit Ethernet,
> + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
> +
> config ROCKCHIP_RK3288
> bool "Support Rockchip RK3288"
> select CPU_V7
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 87d2019..71dd66d 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -12,11 +12,13 @@ obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else ifdef CONFIG_SPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o
> +obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o
> obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o
> else
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o
> +obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o
> obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o
> endif
> @@ -29,6 +31,7 @@ ifndef CONFIG_TPL_BUILD
> obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
> endif
>
> +obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/
> obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
> obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
> diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c
> new file mode 100644
> index 0000000..b2d0635
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c
> @@ -0,0 +1,77 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <asm/io.h>
> +#include <asm/arch/bootrom.h>
> +#include <asm/arch/cru_rk322x.h>
> +#include <asm/arch/grf_rk322x.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/timer.h>
> +#include <asm/arch/uart.h>
> +
> +u32 spl_boot_device(void)
> +{
> + return BOOT_DEVICE_MMC1;
> +}
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GRF_BASE 0x11000000
> +#define SGRF_BASE 0x10140000
> +
> +#define DEBUG_UART_BASE 0x11030000
> +
> +void board_debug_uart_init(void)
> +{
> +static struct rk322x_grf * const grf = (void *)GRF_BASE;
> + /* Enable early UART2 channel 1 on the RK322x */
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B1_MASK | GPIO1B2_MASK,
> + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
> + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
> + /* Set channel C as UART2 input */
> + rk_clrsetreg(&grf->con_iomux,
> + CON_IOMUX_UART2SEL_MASK,
> + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
> +}
> +void board_init_f(ulong dummy)
> +{
> + struct udevice *dev;
> + int ret;
> +
> + /*
> + * Debug UART can be used from here if required:
> + *
> + * debug_uart_init();
> + * printch('a');
> + * printhex8(0x1234);
> + * printascii("string");
> + */
> + debug_uart_init();
> + printascii("SPL Init");
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +
> + rockchip_timer_init();
> + printf("timer init done\n");
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + printf("DRAM init failed: %d\n", ret);
> + return;
> + }
> +
> +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
> + back_to_bootrom();
> +#endif
> +}
> diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c
> new file mode 100644
> index 0000000..1d4fa72
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk322x-board.c
> @@ -0,0 +1,159 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#include <common.h>
> +#include <clk.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/periph.h>
> +#include <asm/arch/grf_rk322x.h>
> +#include <asm/arch/boot_mode.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GRF_BASE 0x11000000
> +
> +static void setup_boot_mode(void)
> +{
> + struct rk322x_grf *const grf = (void *)GRF_BASE;
> + int boot_mode = readl(&grf->os_reg[4]);
> +
> + debug("boot mode %x.\n", boot_mode);
> +
> + /* Clear boot mode */
> + writel(BOOT_NORMAL, &grf->os_reg[4]);
> +
> + switch (boot_mode) {
> + case BOOT_FASTBOOT:
> + printf("enter fastboot!\n");
> + setenv("preboot", "setenv preboot; fastboot usb0");
> + break;
> + case BOOT_UMS:
> + printf("enter UMS!\n");
> + setenv("preboot", "setenv preboot; ums mmc 0");
> + break;
> + }
> +}
> +
> +__weak int rk_board_late_init(void)
> +{
> + return 0;
> +}
> +
> +int board_late_init(void)
> +{
> + setup_boot_mode();
> +
> + return rk_board_late_init();
> +}
> +
> +int board_init(void)
> +{
> +#include <asm/arch/grf_rk322x.h>
> + /* Enable early UART2 channel 1 on the RK322x */
> +#define GRF_BASE 0x11000000
> + struct rk322x_grf * const grf = (void *)GRF_BASE;
> +
> + rk_clrsetreg(&grf->gpio1b_iomux,
> + GPIO1B1_MASK | GPIO1B2_MASK,
> + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
> + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
> + /* Set channel C as UART2 input */
> + rk_clrsetreg(&grf->con_iomux,
> + CON_IOMUX_UART2SEL_MASK,
> + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
> +
> + return 0;
> +}
> +
> +int dram_init_banksize(void)
> +{
> + /* Reserve 0x200000 for OPTEE */
> + gd->bd->bi_dram[0].start = 0x60000000;
> + gd->bd->bi_dram[0].size = 0x8400000;
> + gd->bd->bi_dram[1].start = 0x6a400000;
> + gd->bd->bi_dram[1].size = 0x40000000 - 0xa400000;
> +
> + return 0;
> +}
> +
> +int dram_init(void)
> +{
> + struct ram_info ram;
> + struct udevice *dev;
> + int ret;
> +
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return ret;
> + }
> + ret = ram_get_info(dev, &ram);
> + if (ret) {
> + debug("Cannot get DRAM size: %d\n", ret);
> + return ret;
> + }
> + debug("SDRAM base=%x, size=%x\n",
> + (unsigned int)ram.base, (unsigned int)ram.size);
> + gd->ram_size = ram.size;
> +
> + return 0;
> +}
> +
> +#ifndef CONFIG_SYS_DCACHE_OFF
> +void enable_caches(void)
> +{
> + /* Enable D-cache. I-cache is already enabled in start.S */
> + dcache_enable();
> +}
> +#endif
> +
> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
> +#include <usb.h>
> +#include <usb/dwc2_udc.h>
> +
> +static struct dwc2_plat_otg_data rk322x_otg_data = {
> + .rx_fifo_sz = 512,
> + .np_tx_fifo_sz = 16,
> + .tx_fifo_sz = 128,
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + int node;
> + const char *mode;
> + bool matched = false;
> + const void *blob = gd->fdt_blob;
> +
> + /* find the usb_otg node */
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "rockchip,rk3288-usb");
> +
> + while (node > 0) {
> + mode = fdt_getprop(blob, node, "dr_mode", NULL);
> + if (mode && strcmp(mode, "otg") == 0) {
> + matched = true;
> + break;
> + }
> +
> + node = fdt_node_offset_by_compatible(blob, node,
> + "rockchip,rk3288-usb");
> + }
> + if (!matched) {
> + debug("Not found usb_otg device\n");
> + return -ENODEV;
> + }
> + rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
> +
> + return dwc2_udc_probe(&rk322x_otg_data);
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + return 0;
> +}
> +#endif
> diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig
> new file mode 100644
> index 0000000..dc8071e
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk322x/Kconfig
> @@ -0,0 +1,18 @@
> +if ROCKCHIP_RK322X
> +
> +config TARGET_EVB_RK3229
> + bool "EVB_RK3229"
> + select BOARD_LATE_INIT
> +
> +config SYS_SOC
> + default "rockchip"
> +
> +config SYS_MALLOC_F_LEN
> + default 0x400
> +
> +config SPL_SERIAL_SUPPORT
> + default y
> +
> +source "board/rockchip/evb_rk3229/Kconfig"
> +
> +endif
> diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile
> new file mode 100644
> index 0000000..ecb3e8d
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk322x/Makefile
> @@ -0,0 +1,9 @@
> +#
> +# (C) Copyright 2017 Rockchip Electronics Co., Ltd.
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +
> +obj-y += clk_rk322x.o
> +obj-y += syscon_rk322x.o
> diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c
> new file mode 100644
> index 0000000..6e8be93
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c
> @@ -0,0 +1,33 @@
> +/*
> + * Copyright (C) 2016 Google, Inc
> + * Written by Simon Glass <sjg@chromium.org>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk322x.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_GET_DRIVER(rockchip_rk322x_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk322x_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
> new file mode 100644
> index 0000000..c5cae32
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c
> @@ -0,0 +1,22 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch/clock.h>
> +
> +static const struct udevice_id rk322x_syscon_ids[] = {
> + { .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF },
> + { .compatible = "rockchip,rk3228-msch", .data = ROCKCHIP_SYSCON_MSCH },
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk322x) = {
> + .name = "rk322x_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk322x_syscon_ids,
> +};
> diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h
> new file mode 100644
> index 0000000..23b1707
> --- /dev/null
> +++ b/include/configs/rk322x_common.h
> @@ -0,0 +1,92 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#ifndef __CONFIG_RK322X_COMMON_H
> +#define __CONFIG_RK322X_COMMON_H
> +
> +#include <asm/arch/hardware.h>
> +#include "rockchip-common.h"
> +
> +#define CONFIG_SKIP_LOWLEVEL_INIT
> +#define CONFIG_ENV_SIZE 0x2000
> +#define CONFIG_SYS_MAXARGS 16
> +#define CONFIG_SYS_MALLOC_LEN (32 << 20)
> +#define CONFIG_SYS_CBSIZE 1024
> +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
> +
> +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
> +#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
> +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
> +
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SYS_NS16550_MEM32
> +#define CONFIG_SYS_TEXT_BASE 0x60000000
> +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
> +#define CONFIG_SYS_LOAD_ADDR 0x60800800
> +#define CONFIG_SPL_STACK 0x10088000
> +#define CONFIG_SPL_TEXT_BASE 0x10081004
> +
> +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10)
> +#define CONFIG_ROCKCHIP_CHIP_TAG "RK32"
> +
> +/* MMC/SD IP block */
> +#define CONFIG_BOUNCE_BUFFER
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x60000000
> +#define CONFIG_NR_DRAM_BANKS 2
> +#define SDRAM_BANK_SIZE (512UL << 20UL)
> +
> +#ifndef CONFIG_SPL_BUILD
> +/* usb otg */
> +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_DWC2_OTG
> +#define CONFIG_USB_GADGET_VBUS_DRAW 0
> +
> +/* fastboot */
> +#define CONFIG_CMD_FASTBOOT
> +#define CONFIG_USB_FUNCTION_FASTBOOT
> +#define CONFIG_FASTBOOT_FLASH
> +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
> +#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
> +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
> +
> +/* usb mass storage */
> +#define CONFIG_USB_FUNCTION_MASS_STORAGE
> +#define CONFIG_CMD_USB_MASS_STORAGE
> +
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
> +#define CONFIG_G_DNL_VENDOR_NUM 0x2207
> +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
> +
> +/* usb host */
> +#ifdef CONFIG_CMD_USB
> +#define CONFIG_USB_DWC2
> +#define CONFIG_USB_HOST_ETHER
> +#define CONFIG_USB_ETHER_SMSC95XX
> +#define CONFIG_USB_ETHER_ASIX
> +#endif
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "scriptaddr=0x60000000\0" \
> + "pxefile_addr_r=0x60100000\0" \
> + "fdt_addr_r=0x61f00000\0" \
> + "kernel_addr_r=0x62000000\0" \
> + "ramdisk_addr_r=0x64000000\0"
> +
> +#include <config_distro_bootcmd.h>
> +
> +/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board,
> + * so limit the fdt reallocation to that */
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + "fdt_high=0x7fffffff\0" \
> + "partitions=" PARTS_DEFAULT \
> + ENV_MEM_LAYOUT_SETTINGS \
> + BOOTENV
> +#endif
> +
> +#define CONFIG_PREBOOT
> +
> +#endif
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,6/7] rockchip: rk322x: add sysreset driver
2017-06-09 12:28 ` [U-Boot] [PATCH 6/7] rockchip: rk322x: add sysreset driver Kever Yang
@ 2017-06-12 14:19 ` Philipp Tomsich
2017-06-23 8:41 ` Kever Yang
0 siblings, 1 reply; 20+ messages in thread
From: Philipp Tomsich @ 2017-06-12 14:19 UTC (permalink / raw)
To: u-boot
On Fri, 9 Jun 2017, Kever Yang wrote:
> Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
> only difference is that the target register address is different.
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> drivers/sysreset/sysreset_rk322x.c | 45 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 drivers/sysreset/sysreset_rk322x.c
>
> diff --git a/drivers/sysreset/sysreset_rk322x.c b/drivers/sysreset/sysreset_rk322x.c
> new file mode 100644
> index 0000000..5fce79b
> --- /dev/null
> +++ b/drivers/sysreset/sysreset_rk322x.c
> @@ -0,0 +1,45 @@
> +/*
> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <sysreset.h>
> +#include <asm/io.h>
> +#include <asm/arch/clock.h>
> +#include <asm/arch/cru_rk322x.h>
> +#include <asm/arch/hardware.h>
> +#include <linux/err.h>
> +
> +int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
> +{
> + struct rk322x_cru *cru = rockchip_get_cru();
> +
> + if (IS_ERR(cru))
> + return PTR_ERR(cru);
> + switch (type) {
> + case SYSRESET_WARM:
> + writel(0xeca8, &cru->cru_glb_srst_snd_value);
Please make this a symbolic constant, thanks.
> + break;
> + case SYSRESET_COLD:
> + writel(0xfdb9, &cru->cru_glb_srst_fst_value);
Same.
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> + break;
> + default:
> + return -EPROTONOSUPPORT;
> + }
> +
> + return -EINPROGRESS;
> +}
> +
> +static struct sysreset_ops rk322x_sysreset = {
> + .request = rk322x_sysreset_request,
> +};
> +
> +U_BOOT_DRIVER(sysreset_rk322x) = {
> + .name = "rk322x_sysreset",
> + .id = UCLASS_SYSRESET,
> + .ops = &rk322x_sysreset,
> +};
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,7/7] rockchip: add evb_rk3229 board
2017-06-09 12:28 ` [U-Boot] [PATCH 7/7] rockchip: add evb_rk3229 board Kever Yang
@ 2017-06-12 14:20 ` Philipp Tomsich
0 siblings, 0 replies; 20+ messages in thread
From: Philipp Tomsich @ 2017-06-12 14:20 UTC (permalink / raw)
To: u-boot
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
On Fri, 9 Jun 2017, Kever Yang wrote:
> evb_rk3229 is a RK3229 based board, with:
> - 8GB eMMC;
> - 1GB DDR SDRAM;
> - 2 USB2.0 HOST port;
> - 1 MAC port;
> - 1 HDMI port;
> - IR;
> - WiFi;
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> arch/arm/mach-rockchip/Kconfig | 1 +
> board/rockchip/evb_rk3229/Kconfig | 15 +++++++++
> board/rockchip/evb_rk3229/MAINTAINERS | 6 ++++
> board/rockchip/evb_rk3229/Makefile | 7 ++++
> board/rockchip/evb_rk3229/evb_rk3229.c | 12 +++++++
> configs/evb-rk3229_defconfig | 44 +++++++++++++++++++++++++
> include/configs/evb_rk3229.h | 60 ++++++++++++++++++++++++++++++++++
> 7 files changed, 145 insertions(+)
> create mode 100644 board/rockchip/evb_rk3229/Kconfig
> create mode 100644 board/rockchip/evb_rk3229/MAINTAINERS
> create mode 100644 board/rockchip/evb_rk3229/Makefile
> create mode 100644 board/rockchip/evb_rk3229/evb_rk3229.c
> create mode 100644 configs/evb-rk3229_defconfig
> create mode 100644 include/configs/evb_rk3229.h
>
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 33bd17f..bb44c61 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -124,6 +124,7 @@ config SPL_MMC_SUPPORT
>
> source "arch/arm/mach-rockchip/rk3036/Kconfig"
> source "arch/arm/mach-rockchip/rk3188/Kconfig"
> +source "arch/arm/mach-rockchip/rk322x/Kconfig"
> source "arch/arm/mach-rockchip/rk3288/Kconfig"
> source "arch/arm/mach-rockchip/rk3328/Kconfig"
> source "arch/arm/mach-rockchip/rk3368/Kconfig"
> diff --git a/board/rockchip/evb_rk3229/Kconfig b/board/rockchip/evb_rk3229/Kconfig
> new file mode 100644
> index 0000000..361dcb1
> --- /dev/null
> +++ b/board/rockchip/evb_rk3229/Kconfig
> @@ -0,0 +1,15 @@
> +if TARGET_EVB_RK3229
> +
> +config SYS_BOARD
> + default "evb_rk3229"
> +
> +config SYS_VENDOR
> + default "rockchip"
> +
> +config SYS_CONFIG_NAME
> + default "evb_rk3229"
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> + def_bool y
> +
> +endif
> diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS
> new file mode 100644
> index 0000000..dfa1090
> --- /dev/null
> +++ b/board/rockchip/evb_rk3229/MAINTAINERS
> @@ -0,0 +1,6 @@
> +EVB-RK3229
> +M: Kever Yang <kever.yang@rock-chips.com>
> +S: Maintained
> +F: board/rockchip/evb_rk3229
> +F: include/configs/evb_rk3229.h
> +F: configs/evb-rk3229_defconfig
> diff --git a/board/rockchip/evb_rk3229/Makefile b/board/rockchip/evb_rk3229/Makefile
> new file mode 100644
> index 0000000..65dcd8b
> --- /dev/null
> +++ b/board/rockchip/evb_rk3229/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# (C) Copyright 2015 Google, Inc
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += evb_rk3229.o
> diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c
> new file mode 100644
> index 0000000..6c4ec2cd
> --- /dev/null
> +++ b/board/rockchip/evb_rk3229/evb_rk3229.c
> @@ -0,0 +1,12 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/io.h>
> +#include <asm/arch/uart.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
> new file mode 100644
> index 0000000..0c3b6f7
> --- /dev/null
> +++ b/configs/evb-rk3229_defconfig
> @@ -0,0 +1,44 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x800
> +CONFIG_ROCKCHIP_RK322X=y
> +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y
> +CONFIG_TARGET_EVB_RK3229=y
> +CONFIG_SPL_STACK_R_ADDR=0x80000
> +CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
> +CONFIG_FASTBOOT=y
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MMC=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_TIME=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_ROCKCHIP_RK322X=y
> +# CONFIG_SPL_PINCTRL_FULL is not set
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART=y
> +CONFIG_DEBUG_UART_BASE=0x11030000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550=y
> +CONFIG_SYSRESET=y
> +CONFIG_ERRNO_STR=y
> diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h
> new file mode 100644
> index 0000000..13fc834
> --- /dev/null
> +++ b/include/configs/evb_rk3229.h
> @@ -0,0 +1,60 @@
> +/*
> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +#include <configs/rk322x_common.h>
> +
> +
> +/* Store env in emmc */
> +#undef CONFIG_ENV_SIZE
> +#define CONFIG_ENV_SIZE (32 << 10)
> +#define CONFIG_ENV_IS_IN_MMC
> +#define CONFIG_SYS_MMC_ENV_DEV 0
> +#define CONFIG_SYS_MMC_ENV_PART 0
> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
> +
> +#ifndef CONFIG_SPL_BUILD
> +/* Enable gpt partition table */
> +#undef PARTS_DEFAULT
> +#define PARTS_DEFAULT \
> + "uuid_disk=${uuid_gpt_disk};" \
> + "name=loader_a,start=4M,size=4M,uuid=${uuid_gpt_loader};" \
> + "name=loader_b,size=4M,uuid=${uuid_gpt_reserved};" \
> + "name=trust_a,size=4M,uuid=${uuid_gpt_reserved};" \
> + "name=trust_b,size=4M,uuid=${uuid_gpt_reserved};" \
> + "name=misc,size=4M,uuid=${uuid_gpt_misc};" \
> + "name=metadata,size=16M,uuid=${uuid_gpt_metadata};" \
> + "name=boot_a,size=32M,uuid=${uuid_gpt_boot_a};" \
> + "name=boot_b,size=32M,uuid=${uuid_gpt_boot_b};" \
> + "name=system_a,size=818M,uuid=${uuid_gpt_system_a};" \
> + "name=system_b,size=818M,uuid=${uuid_gpt_system_b};" \
> + "name=vendor_a,size=50M,uuid=${uuid_gpt_vendor_a};" \
> + "name=vendor_b,size=50M,uuid=${uuid_gpt_vendor_b};" \
> + "name=cache,size=100M,uuid=${uuid_gpt_cache};" \
> + "name=persist,size=4M,uuid=${uuid_gpt_persist};" \
> + "name=userdata,size=-,uuid=${uuid_gpt_userdata};\0" \
> +
> +#define CONFIG_PREBOOT
> +
> +#define CONFIG_ANDROID_BOOT_IMAGE
> +#define CONFIG_SYS_BOOT_RAMDISK_HIGH
> +
> +#undef CONFIG_BOOTCOMMAND
> +#define CONFIG_BOOTCOMMAND \
> + "mmc read 0x61000000 0x8000 0x5000;" \
> + "bootm 0x61000000" \
> +
> +/* Enable atags */
> +#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
> +#define CONFIG_INITRD_TAG
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_CMDLINE_TAG
> +
> +#endif
> +
> +#endif
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,6/7] rockchip: rk322x: add sysreset driver
2017-06-12 14:19 ` [U-Boot] [U-Boot,6/7] " Philipp Tomsich
@ 2017-06-23 8:41 ` Kever Yang
2017-06-23 8:46 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-23 8:41 UTC (permalink / raw)
To: u-boot
Hi Philipp,
On 06/12/2017 10:19 PM, Philipp Tomsich wrote:
>
>
> On Fri, 9 Jun 2017, Kever Yang wrote:
>
>> Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
>> only difference is that the target register address is different.
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> drivers/sysreset/sysreset_rk322x.c | 45
>> ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 45 insertions(+)
>> create mode 100644 drivers/sysreset/sysreset_rk322x.c
>>
>> diff --git a/drivers/sysreset/sysreset_rk322x.c
>> b/drivers/sysreset/sysreset_rk322x.c
>> new file mode 100644
>> index 0000000..5fce79b
>> --- /dev/null
>> +++ b/drivers/sysreset/sysreset_rk322x.c
>> @@ -0,0 +1,45 @@
>> +/*
>> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <dm.h>
>> +#include <errno.h>
>> +#include <sysreset.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/cru_rk322x.h>
>> +#include <asm/arch/hardware.h>
>> +#include <linux/err.h>
>> +
>> +int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
>> +{
>> + struct rk322x_cru *cru = rockchip_get_cru();
>> +
>> + if (IS_ERR(cru))
>> + return PTR_ERR(cru);
>> + switch (type) {
>> + case SYSRESET_WARM:
>> + writel(0xeca8, &cru->cru_glb_srst_snd_value);
>
> Please make this a symbolic constant, thanks.
Do you mean define a MACRO and use it?
Thanks,
- Kever
>
>> + break;
>> + case SYSRESET_COLD:
>> + writel(0xfdb9, &cru->cru_glb_srst_fst_value);
>
> Same.
>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
>> + break;
>> + default:
>> + return -EPROTONOSUPPORT;
>> + }
>> +
>> + return -EINPROGRESS;
>> +}
>> +
>> +static struct sysreset_ops rk322x_sysreset = {
>> + .request = rk322x_sysreset_request,
>> +};
>> +
>> +U_BOOT_DRIVER(sysreset_rk322x) = {
>> + .name = "rk322x_sysreset",
>> + .id = UCLASS_SYSRESET,
>> + .ops = &rk322x_sysreset,
>> +};
>>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,6/7] rockchip: rk322x: add sysreset driver
2017-06-23 8:41 ` Kever Yang
@ 2017-06-23 8:46 ` Dr. Philipp Tomsich
2017-06-23 9:16 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 20+ messages in thread
From: Dr. Philipp Tomsich @ 2017-06-23 8:46 UTC (permalink / raw)
To: u-boot
Kever,
> On 23 Jun 2017, at 10:41, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Philipp,
>
>
> On 06/12/2017 10:19 PM, Philipp Tomsich wrote:
>>
>>
>> On Fri, 9 Jun 2017, Kever Yang wrote:
>>
>>> Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
>>> only difference is that the target register address is different.
>>>
>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>> ---
>>>
>>> drivers/sysreset/sysreset_rk322x.c | 45 ++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 45 insertions(+)
>>> create mode 100644 drivers/sysreset/sysreset_rk322x.c
>>>
>>> diff --git a/drivers/sysreset/sysreset_rk322x.c b/drivers/sysreset/sysreset_rk322x.c
>>> new file mode 100644
>>> index 0000000..5fce79b
>>> --- /dev/null
>>> +++ b/drivers/sysreset/sysreset_rk322x.c
>>> @@ -0,0 +1,45 @@
>>> +/*
>>> + * (C) Copyright 2017 Rockchip Electronics Co., Ltd
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +
>>> +#include <common.h>
>>> +#include <dm.h>
>>> +#include <errno.h>
>>> +#include <sysreset.h>
>>> +#include <asm/io.h>
>>> +#include <asm/arch/clock.h>
>>> +#include <asm/arch/cru_rk322x.h>
>>> +#include <asm/arch/hardware.h>
>>> +#include <linux/err.h>
>>> +
>>> +int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
>>> +{
>>> + struct rk322x_cru *cru = rockchip_get_cru();
>>> +
>>> + if (IS_ERR(cru))
>>> + return PTR_ERR(cru);
>>> + switch (type) {
>>> + case SYSRESET_WARM:
>>> + writel(0xeca8, &cru->cru_glb_srst_snd_value);
>>
>> Please make this a symbolic constant, thanks.
>
> Do you mean define a MACRO and use it?
I think the way this has been done in the past for the Rockchip sub-architecture
was to use an enum…
Personally, I would prefer a ‘static const u32’, but let’s keep consistent and stick
with enums.
> Thanks,
> - Kever
>>
>>> + break;
>>> + case SYSRESET_COLD:
>>> + writel(0xfdb9, &cru->cru_glb_srst_fst_value);
>>
>> Same.
>>
>> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>
>>> + break;
>>> + default:
>>> + return -EPROTONOSUPPORT;
>>> + }
>>> +
>>> + return -EINPROGRESS;
>>> +}
>>> +
>>> +static struct sysreset_ops rk322x_sysreset = {
>>> + .request = rk322x_sysreset_request,
>>> +};
>>> +
>>> +U_BOOT_DRIVER(sysreset_rk322x) = {
>>> + .name = "rk322x_sysreset",
>>> + .id = UCLASS_SYSRESET,
>>> + .ops = &rk322x_sysreset,
>>> +};
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,2/7] rockchip: rk322x: add clock driver
2017-06-12 11:00 ` [U-Boot] [U-Boot,2/7] " Philipp Tomsich
@ 2017-06-23 8:49 ` Kever Yang
2017-06-23 8:54 ` Dr. Philipp Tomsich
0 siblings, 1 reply; 20+ messages in thread
From: Kever Yang @ 2017-06-23 8:49 UTC (permalink / raw)
To: u-boot
Hi Philipp,
On 06/12/2017 07:00 PM, Philipp Tomsich wrote:
>
>
> On Fri, 9 Jun 2017, Kever Yang wrote:
>
>> Add clock driver init support for:
>> - cpu, bus clock init;
>> - emmc, sdmmc clock;
>> - ddr clock;
>>
>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>> ---
>>
>> arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++
>> drivers/clk/rockchip/Makefile | 1 +
>> drivers/clk/rockchip/clk_rk322x.c | 413
>> ++++++++++++++++++++++++
>> 3 files changed, 629 insertions(+)
>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h
>> create mode 100644 drivers/clk/rockchip/clk_rk322x.c
>>
>> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
>> b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
>> new file mode 100644
>> index 0000000..0a01f87
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
>> @@ -0,0 +1,215 @@
>> +/*
>> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +#ifndef _ASM_ARCH_CRU_RK322X_H
>> +#define _ASM_ARCH_CRU_RK322X_H
>> +
>> +#include <common.h>
>> +
>> +#define MHz 1000000
>> +#define OSC_HZ (24 * MHz)
>> +
>> +#define APLL_HZ (600 * MHz)
>> +#define GPLL_HZ (594 * MHz)
>> +
>> +#define CORE_PERI_HZ 150000000
>> +#define CORE_ACLK_HZ 300000000
>> +
>> +#define BUS_ACLK_HZ 148500000
>> +#define BUS_HCLK_HZ 148500000
>> +#define BUS_PCLK_HZ 74250000
>> +
>> +#define PERI_ACLK_HZ 148500000
>> +#define PERI_HCLK_HZ 148500000
>> +#define PERI_PCLK_HZ 74250000
>> +
>> +/* Private data for the clock driver - used by rockchip_get_cru() */
>> +struct rk322x_clk_priv {
>> + struct rk322x_cru *cru;
>> + ulong rate;
>> +};
>> +
>> +struct rk322x_cru {
>> + struct rk322x_pll {
>> + unsigned int con0;
>> + unsigned int con1;
>> + unsigned int con2;
>> + } pll[4];
>> + unsigned int reserved0[4];
>> + unsigned int cru_mode_con;
>> + unsigned int cru_clksel_con[35];
>> + unsigned int cru_clkgate_con[16];
>> + unsigned int cru_softrst_con[9];
>> + unsigned int cru_misc_con;
>> + unsigned int reserved1[2];
>> + unsigned int cru_glb_cnt_th;
>> + unsigned int reserved2[3];
>> + unsigned int cru_glb_rst_st;
>> + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
>
> It took me a moment to understand why the 'minus one'.
>
> Could you introduce a macro for this along the lines of
> U32_ELEMS_START_TO_LAST(0x1c0, 0x14c)
> or something similar... I fail to come up with a concise
> name that clearly says "from 0x1c0 and covering up to,
> but excluding, the address 0x150").
Well, I will keep it as-is for this patch set, because this is widely used
for all other Rockchip SoCs, if we need to do this, we'd better
have a clean for all of them.
Thanks,
- Kever
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,2/7] rockchip: rk322x: add clock driver
2017-06-23 8:49 ` Kever Yang
@ 2017-06-23 8:54 ` Dr. Philipp Tomsich
0 siblings, 0 replies; 20+ messages in thread
From: Dr. Philipp Tomsich @ 2017-06-23 8:54 UTC (permalink / raw)
To: u-boot
> On 23 Jun 2017, at 10:49, Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Philipp,
>
>
> On 06/12/2017 07:00 PM, Philipp Tomsich wrote:
>>
>>
>> On Fri, 9 Jun 2017, Kever Yang wrote:
>>
>>> Add clock driver init support for:
>>> - cpu, bus clock init;
>>> - emmc, sdmmc clock;
>>> - ddr clock;
>>>
>>> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
>>> ---
>>>
>>> arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 215 ++++++++++++
>>> drivers/clk/rockchip/Makefile | 1 +
>>> drivers/clk/rockchip/clk_rk322x.c | 413 ++++++++++++++++++++++++
>>> 3 files changed, 629 insertions(+)
>>> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk322x.h
>>> create mode 100644 drivers/clk/rockchip/clk_rk322x.c
>>>
>>> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
>>> new file mode 100644
>>> index 0000000..0a01f87
>>> --- /dev/null
>>> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h
>>> @@ -0,0 +1,215 @@
>>> +/*
>>> + * (C) Copyright 2015 Rockchip Electronics Co., Ltd
>>> + *
>>> + * SPDX-License-Identifier: GPL-2.0+
>>> + */
>>> +#ifndef _ASM_ARCH_CRU_RK322X_H
>>> +#define _ASM_ARCH_CRU_RK322X_H
>>> +
>>> +#include <common.h>
>>> +
>>> +#define MHz 1000000
>>> +#define OSC_HZ (24 * MHz)
>>> +
>>> +#define APLL_HZ (600 * MHz)
>>> +#define GPLL_HZ (594 * MHz)
>>> +
>>> +#define CORE_PERI_HZ 150000000
>>> +#define CORE_ACLK_HZ 300000000
>>> +
>>> +#define BUS_ACLK_HZ 148500000
>>> +#define BUS_HCLK_HZ 148500000
>>> +#define BUS_PCLK_HZ 74250000
>>> +
>>> +#define PERI_ACLK_HZ 148500000
>>> +#define PERI_HCLK_HZ 148500000
>>> +#define PERI_PCLK_HZ 74250000
>>> +
>>> +/* Private data for the clock driver - used by rockchip_get_cru() */
>>> +struct rk322x_clk_priv {
>>> + struct rk322x_cru *cru;
>>> + ulong rate;
>>> +};
>>> +
>>> +struct rk322x_cru {
>>> + struct rk322x_pll {
>>> + unsigned int con0;
>>> + unsigned int con1;
>>> + unsigned int con2;
>>> + } pll[4];
>>> + unsigned int reserved0[4];
>>> + unsigned int cru_mode_con;
>>> + unsigned int cru_clksel_con[35];
>>> + unsigned int cru_clkgate_con[16];
>>> + unsigned int cru_softrst_con[9];
>>> + unsigned int cru_misc_con;
>>> + unsigned int reserved1[2];
>>> + unsigned int cru_glb_cnt_th;
>>> + unsigned int reserved2[3];
>>> + unsigned int cru_glb_rst_st;
>>> + unsigned int reserved3[(0x1c0 - 0x150) / 4 - 1];
>>
>> It took me a moment to understand why the 'minus one'.
>>
>> Could you introduce a macro for this along the lines of
>> U32_ELEMS_START_TO_LAST(0x1c0, 0x14c)
>> or something similar... I fail to come up with a concise
>> name that clearly says "from 0x1c0 and covering up to,
>> but excluding, the address 0x150").
>
> Well, I will keep it as-is for this patch set, because this is widely used
> for all other Rockchip SoCs, if we need to do this, we'd better
> have a clean for all of them.
Ok. I’ll apply as is.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [U-Boot] [U-Boot,6/7] rockchip: rk322x: add sysreset driver
2017-06-23 8:46 ` Dr. Philipp Tomsich
@ 2017-06-23 9:16 ` Dr. Philipp Tomsich
0 siblings, 0 replies; 20+ messages in thread
From: Dr. Philipp Tomsich @ 2017-06-23 9:16 UTC (permalink / raw)
To: u-boot
Kever,
> On 23 Jun 2017, at 10:46, Dr. Philipp Tomsich <philipp.tomsich@theobroma-systems.com> wrote:
>
>>>> +int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type)
>>>> +{
>>>> + struct rk322x_cru *cru = rockchip_get_cru();
>>>> +
>>>> + if (IS_ERR(cru))
>>>> + return PTR_ERR(cru);
>>>> + switch (type) {
>>>> + case SYSRESET_WARM:
>>>> + writel(0xeca8, &cru->cru_glb_srst_snd_value);
>>>
>>> Please make this a symbolic constant, thanks.
>>
>> Do you mean define a MACRO and use it?
>
> I think the way this has been done in the past for the Rockchip sub-architecture
> was to use an enum…
>
> Personally, I would prefer a ‘static const u32’, but let’s keep consistent and stick
> with enums.
I just took another look and see that the constant isn’t needed anywhere outside the sysrequest driver.
So you could just use a ‘const u32 [put-symbolic-name-here] = 0xeca8’ in the function itself.
The compiler will take care of handling this in an optimal way from there.
Regards,
Philipp.
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2017-06-23 9:16 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-09 12:28 [U-Boot] [PATCH 0/7] Add Rockchip RK3229 SoC Kever Yang
2017-06-09 12:28 ` [U-Boot] [PATCH 1/7] rockchip: mkimage: add support for rk322x soc Kever Yang
2017-06-12 10:52 ` [U-Boot] [U-Boot, " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 2/7] rockchip: rk322x: add clock driver Kever Yang
2017-06-12 11:00 ` [U-Boot] [U-Boot,2/7] " Philipp Tomsich
2017-06-23 8:49 ` Kever Yang
2017-06-23 8:54 ` Dr. Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 3/7] rockchip: rk322x: add pinctrl driver Kever Yang
2017-06-12 14:18 ` [U-Boot] [U-Boot,3/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 4/7] rockchip: rk322x: add dts file Kever Yang
2017-06-12 14:18 ` [U-Boot] [U-Boot,4/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 5/7] rockchip: rk322x: add basic soc support Kever Yang
2017-06-12 14:19 ` [U-Boot] [U-Boot,5/7] " Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 6/7] rockchip: rk322x: add sysreset driver Kever Yang
2017-06-12 14:19 ` [U-Boot] [U-Boot,6/7] " Philipp Tomsich
2017-06-23 8:41 ` Kever Yang
2017-06-23 8:46 ` Dr. Philipp Tomsich
2017-06-23 9:16 ` Dr. Philipp Tomsich
2017-06-09 12:28 ` [U-Boot] [PATCH 7/7] rockchip: add evb_rk3229 board Kever Yang
2017-06-12 14:20 ` [U-Boot] [U-Boot,7/7] " Philipp Tomsich
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