* [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL
@ 2017-06-21 16:39 Anusha Srivatsa
2017-06-21 16:39 ` [PATCH libdrm 2/3] intel: PCI Ids for H " Anusha Srivatsa
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Anusha Srivatsa @ 2017-06-21 16:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Add the PCI IDs for S SKU IN CFL by following the spec.
v2: Update IDs.
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
intel/intel_chipset.h | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 41fc0da..36bbec9 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -221,6 +221,12 @@
#define PCI_CHIP_GLK 0x3184
#define PCI_CHIP_GLK_2X6 0x3185
+#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
+#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
+#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
+#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
+#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
+
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
(devid) == PCI_CHIP_I945_GM || \
@@ -452,10 +458,19 @@
#define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \
(devid) == PCI_CHIP_GLK_2X6)
+#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 )
+
+#define IS_COFFEELAKE(devid) (IS_CFL_S(devid))
+
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
IS_BROXTON(devid) || \
IS_KABYLAKE(devid) || \
- IS_GEMINILAKE(devid))
+ IS_GEMINILAKE(devid) || \
+ IS_COFFEELAKE(devid))
#define IS_9XX(dev) (IS_GEN3(dev) || \
IS_GEN4(dev) || \
--
2.7.4
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH libdrm 2/3] intel: PCI Ids for H SKU in CFL
2017-06-21 16:39 [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL Anusha Srivatsa
@ 2017-06-21 16:39 ` Anusha Srivatsa
2017-06-28 21:08 ` Clint Taylor
2017-06-21 16:39 ` [PATCH libdrm 3/3] intel: PCI Ids for U " Anusha Srivatsa
2017-06-28 21:06 ` [PATCH libdrm 1/3] intel: PCI Ids for S " Clint Taylor
2 siblings, 1 reply; 9+ messages in thread
From: Anusha Srivatsa @ 2017-06-21 16:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Add the PCI IDs for H SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
intel/intel_chipset.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 36bbec9..4da145c 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -226,6 +226,8 @@
#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
+#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
+#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -464,7 +466,11 @@
(devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
(devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 )
-#define IS_COFFEELAKE(devid) (IS_CFL_S(devid))
+#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
+
+#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
+ IS_CFL_H(devid))
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
IS_BROXTON(devid) || \
--
2.7.4
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL
2017-06-21 16:39 [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL Anusha Srivatsa
2017-06-21 16:39 ` [PATCH libdrm 2/3] intel: PCI Ids for H " Anusha Srivatsa
@ 2017-06-21 16:39 ` Anusha Srivatsa
2017-06-21 19:50 ` Clint Taylor
2017-06-28 21:09 ` Clint Taylor
2017-06-28 21:06 ` [PATCH libdrm 1/3] intel: PCI Ids for S " Clint Taylor
2 siblings, 2 replies; 9+ messages in thread
From: Anusha Srivatsa @ 2017-06-21 16:39 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
Add the PCI IDs for U SKU IN CFL by following the spec.
v2: Update IDs
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
intel/intel_chipset.h | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 4da145c..8a0d4ff 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -228,6 +228,10 @@
#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
#define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
(devid) == PCI_CHIP_I915_GM || \
@@ -469,8 +473,14 @@
#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
+ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
+
#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
- IS_CFL_H(devid))
+ IS_CFL_H(devid) || \
+ IS_CFL_U(devid))
#define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
IS_BROXTON(devid) || \
--
2.7.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL
2017-06-21 16:39 ` [PATCH libdrm 3/3] intel: PCI Ids for U " Anusha Srivatsa
@ 2017-06-21 19:50 ` Clint Taylor
2017-06-21 21:16 ` Srivatsa, Anusha
2017-06-28 21:09 ` Clint Taylor
1 sibling, 1 reply; 9+ messages in thread
From: Clint Taylor @ 2017-06-21 19:50 UTC (permalink / raw)
To: intel-gfx
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
> Add the PCI IDs for U SKU IN CFL by following the spec.
>
> v2: Update IDs
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> intel/intel_chipset.h | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 4da145c..8a0d4ff 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -228,6 +228,10 @@
> #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
> #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
> #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
> +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
> +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
> +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
> +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
0x3EA8 is marked not POR in the current documentation.
-Clint
>
> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
> (devid) == PCI_CHIP_I915_GM || \
> @@ -469,8 +473,14 @@
> #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
> (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
>
> +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
> +
> #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
> - IS_CFL_H(devid))
> + IS_CFL_H(devid) || \
> + IS_CFL_U(devid))
>
> #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
> IS_BROXTON(devid) || \
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL
2017-06-21 19:50 ` Clint Taylor
@ 2017-06-21 21:16 ` Srivatsa, Anusha
0 siblings, 0 replies; 9+ messages in thread
From: Srivatsa, Anusha @ 2017-06-21 21:16 UTC (permalink / raw)
To: Taylor, Clinton A, intel-gfx
>-----Original Message-----
>From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>Clint Taylor
>Sent: Wednesday, June 21, 2017 12:51 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL
>
>
>
>On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
>> Add the PCI IDs for U SKU IN CFL by following the spec.
>>
>> v2: Update IDs
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>> intel/intel_chipset.h | 12 +++++++++++-
>> 1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index
>> 4da145c..8a0d4ff 100644
>> --- a/intel/intel_chipset.h
>> +++ b/intel/intel_chipset.h
>> @@ -228,6 +228,10 @@
>> #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
>> #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
>> #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
>0x3EA8 is marked not POR in the current documentation.
Hmm....for now the intention was to match the IDs we currently have in the i915 to libdrm and IGT so that we have same IDs everywhere....
Anusha
>-Clint
>
>>
>> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
>> (devid) == PCI_CHIP_I915_GM || \ @@ -469,8
>+473,14 @@
>> #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
>> (devid) ==
>> PCI_CHIP_COFFEELAKE_H_GT2_2)
>>
>> +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
>> + (devid) ==
>> +PCI_CHIP_COFFEELAKE_U_GT3_4)
>> +
>> #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
>> - IS_CFL_H(devid))
>> + IS_CFL_H(devid) || \
>> + IS_CFL_U(devid))
>>
>> #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
>> IS_BROXTON(devid) || \
>
>_______________________________________________
>Intel-gfx mailing list
>Intel-gfx@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL
2017-06-21 16:39 [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL Anusha Srivatsa
2017-06-21 16:39 ` [PATCH libdrm 2/3] intel: PCI Ids for H " Anusha Srivatsa
2017-06-21 16:39 ` [PATCH libdrm 3/3] intel: PCI Ids for U " Anusha Srivatsa
@ 2017-06-28 21:06 ` Clint Taylor
2 siblings, 0 replies; 9+ messages in thread
From: Clint Taylor @ 2017-06-28 21:06 UTC (permalink / raw)
To: intel-gfx
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
> Add the PCI IDs for S SKU IN CFL by following the spec.
>
> v2: Update IDs.
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> intel/intel_chipset.h | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 41fc0da..36bbec9 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -221,6 +221,12 @@
> #define PCI_CHIP_GLK 0x3184
> #define PCI_CHIP_GLK_2X6 0x3185
>
> +#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90
> +#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93
> +#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
> +#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
> +#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
Matches BSPEC DID2 values.
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> +
> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
> (devid) == PCI_CHIP_I915_GM || \
> (devid) == PCI_CHIP_I945_GM || \
> @@ -452,10 +458,19 @@
> #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \
> (devid) == PCI_CHIP_GLK_2X6)
>
> +#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \
> + (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \
> + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \
> + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
> + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 )
> +
> +#define IS_COFFEELAKE(devid) (IS_CFL_S(devid))
> +
> #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
> IS_BROXTON(devid) || \
> IS_KABYLAKE(devid) || \
> - IS_GEMINILAKE(devid))
> + IS_GEMINILAKE(devid) || \
> + IS_COFFEELAKE(devid))
>
> #define IS_9XX(dev) (IS_GEN3(dev) || \
> IS_GEN4(dev) || \
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH libdrm 2/3] intel: PCI Ids for H SKU in CFL
2017-06-21 16:39 ` [PATCH libdrm 2/3] intel: PCI Ids for H " Anusha Srivatsa
@ 2017-06-28 21:08 ` Clint Taylor
0 siblings, 0 replies; 9+ messages in thread
From: Clint Taylor @ 2017-06-28 21:08 UTC (permalink / raw)
To: intel-gfx
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
> Add the PCI IDs for H SKU IN CFL by following the spec.
>
> v2: Update IDs
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> intel/intel_chipset.h | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 36bbec9..4da145c 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -226,6 +226,8 @@
> #define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91
> #define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92
> #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
> +#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
> +#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
Matches BSPEC DID2 values
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>
> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
> (devid) == PCI_CHIP_I915_GM || \
> @@ -464,7 +466,11 @@
> (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \
> (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 )
>
> -#define IS_COFFEELAKE(devid) (IS_CFL_S(devid))
> +#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
> + (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
> +
> +#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
> + IS_CFL_H(devid))
>
> #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
> IS_BROXTON(devid) || \
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL
2017-06-21 16:39 ` [PATCH libdrm 3/3] intel: PCI Ids for U " Anusha Srivatsa
2017-06-21 19:50 ` Clint Taylor
@ 2017-06-28 21:09 ` Clint Taylor
2017-06-29 17:55 ` Rodrigo Vivi
1 sibling, 1 reply; 9+ messages in thread
From: Clint Taylor @ 2017-06-28 21:09 UTC (permalink / raw)
To: Anusha Srivatsa, intel-gfx; +Cc: Rodrigo Vivi
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
> Add the PCI IDs for U SKU IN CFL by following the spec.
>
> v2: Update IDs
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> intel/intel_chipset.h | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 4da145c..8a0d4ff 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -228,6 +228,10 @@
> #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
> #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
> #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
> +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
> +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
> +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
> +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
Matches values in i915 driver.
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>
> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
> (devid) == PCI_CHIP_I915_GM || \
> @@ -469,8 +473,14 @@
> #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
> (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
>
> +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
> +
> #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
> - IS_CFL_H(devid))
> + IS_CFL_H(devid) || \
> + IS_CFL_U(devid))
>
> #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
> IS_BROXTON(devid) || \
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH libdrm 3/3] intel: PCI Ids for U SKU in CFL
2017-06-28 21:09 ` Clint Taylor
@ 2017-06-29 17:55 ` Rodrigo Vivi
0 siblings, 0 replies; 9+ messages in thread
From: Rodrigo Vivi @ 2017-06-29 17:55 UTC (permalink / raw)
To: Clint Taylor, DRI mailing list, mesa-dev; +Cc: intel-gfx, Rodrigo Vivi
series merged to libdrm. thanks for patches and review.
On Wed, Jun 28, 2017 at 2:09 PM, Clint Taylor
<clinton.a.taylor@intel.com> wrote:
>
>
> On 06/21/2017 09:39 AM, Anusha Srivatsa wrote:
>>
>> Add the PCI IDs for U SKU IN CFL by following the spec.
>>
>> v2: Update IDs
>>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>> intel/intel_chipset.h | 12 +++++++++++-
>> 1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
>> index 4da145c..8a0d4ff 100644
>> --- a/intel/intel_chipset.h
>> +++ b/intel/intel_chipset.h
>> @@ -228,6 +228,10 @@
>> #define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96
>> #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
>> #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
>> +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
>
> Matches values in i915 driver.
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>
>> #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
>> (devid) == PCI_CHIP_I915_GM || \
>> @@ -469,8 +473,14 @@
>> #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1
>> || \
>> (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
>> +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT3_1
>> || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2
>> || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3
>> || \
>> + (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4)
>> +
>> #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
>> - IS_CFL_H(devid))
>> + IS_CFL_H(devid) || \
>> + IS_CFL_U(devid))
>> #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
>> IS_BROXTON(devid) || \
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2017-06-29 17:55 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-06-21 16:39 [PATCH libdrm 1/3] intel: PCI Ids for S SKU in CFL Anusha Srivatsa
2017-06-21 16:39 ` [PATCH libdrm 2/3] intel: PCI Ids for H " Anusha Srivatsa
2017-06-28 21:08 ` Clint Taylor
2017-06-21 16:39 ` [PATCH libdrm 3/3] intel: PCI Ids for U " Anusha Srivatsa
2017-06-21 19:50 ` Clint Taylor
2017-06-21 21:16 ` Srivatsa, Anusha
2017-06-28 21:09 ` Clint Taylor
2017-06-29 17:55 ` Rodrigo Vivi
2017-06-28 21:06 ` [PATCH libdrm 1/3] intel: PCI Ids for S " Clint Taylor
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