* [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured
@ 2022-12-05 6:53 Bin Meng
2022-12-05 23:13 ` Wilfred Mallawa
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Bin Meng @ 2022-12-05 6:53 UTC (permalink / raw)
To: qemu-devel; +Cc: Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
The priv spec v1.12 says:
If no PMP entry matches an M-mode access, the access succeeds. If
no PMP entry matches an S-mode or U-mode access, but at least one
PMP entry is implemented, the access fails. Failed accesses generate
an instruction, load, or store access-fault exception.
At present the exception cause is set to 'illegal instruction' but
should have been 'instruction access fault'.
Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
target/riscv/op_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 09f1f5185d..d7af7f056b 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env)
if (riscv_feature(env, RISCV_FEATURE_PMP) &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
- riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
}
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured
2022-12-05 6:53 [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured Bin Meng
@ 2022-12-05 23:13 ` Wilfred Mallawa
2022-12-06 7:05 ` Alistair Francis
2022-12-07 5:18 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Wilfred Mallawa @ 2022-12-05 23:13 UTC (permalink / raw)
To: bmeng, qemu-devel; +Cc: bin.meng, palmer, Alistair Francis, qemu-riscv
On Mon, 2022-12-05 at 14:53 +0800, Bin Meng wrote:
> The priv spec v1.12 says:
>
> If no PMP entry matches an M-mode access, the access succeeds. If
> no PMP entry matches an S-mode or U-mode access, but at least one
> PMP entry is implemented, the access fails. Failed accesses
> generate
> an instruction, load, or store access-fault exception.
>
> At present the exception cause is set to 'illegal instruction' but
> should have been 'instruction access fault'.
>
> Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP
> entry is configured")
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> ---
>
> target/riscv/op_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 09f1f5185d..d7af7f056b 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env)
>
> if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
> - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST,
> GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT,
> GETPC());
> }
>
> target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured
2022-12-05 6:53 [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured Bin Meng
2022-12-05 23:13 ` Wilfred Mallawa
@ 2022-12-06 7:05 ` Alistair Francis
2022-12-07 5:18 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-12-06 7:05 UTC (permalink / raw)
To: Bin Meng
Cc: qemu-devel, Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
On Mon, Dec 5, 2022 at 4:54 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> The priv spec v1.12 says:
>
> If no PMP entry matches an M-mode access, the access succeeds. If
> no PMP entry matches an S-mode or U-mode access, but at least one
> PMP entry is implemented, the access fails. Failed accesses generate
> an instruction, load, or store access-fault exception.
>
> At present the exception cause is set to 'illegal instruction' but
> should have been 'instruction access fault'.
>
> Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured")
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> target/riscv/op_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 09f1f5185d..d7af7f056b 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env)
>
> if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
> - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
> }
>
> target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured
2022-12-05 6:53 [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured Bin Meng
2022-12-05 23:13 ` Wilfred Mallawa
2022-12-06 7:05 ` Alistair Francis
@ 2022-12-07 5:18 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2022-12-07 5:18 UTC (permalink / raw)
To: Bin Meng
Cc: qemu-devel, Alistair Francis, Bin Meng, Palmer Dabbelt, qemu-riscv
On Mon, Dec 5, 2022 at 4:54 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> The priv spec v1.12 says:
>
> If no PMP entry matches an M-mode access, the access succeeds. If
> no PMP entry matches an S-mode or U-mode access, but at least one
> PMP entry is implemented, the access fails. Failed accesses generate
> an instruction, load, or store access-fault exception.
>
> At present the exception cause is set to 'illegal instruction' but
> should have been 'instruction access fault'.
>
> Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured")
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
>
> target/riscv/op_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 09f1f5185d..d7af7f056b 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env)
>
> if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
> - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
> + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
> }
>
> target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-12-07 5:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-05 6:53 [PATCH] target/riscv: Fix mret exception cause when no pmp rule is configured Bin Meng
2022-12-05 23:13 ` Wilfred Mallawa
2022-12-06 7:05 ` Alistair Francis
2022-12-07 5:18 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.