All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Wang, Zhi A" <zhi.a.wang@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>,
	Zhi Wang <zhi.wang.linux@gmail.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-gvt-dev@lists.freedesktop.org" 
	<intel-gvt-dev@lists.freedesktop.org>
Cc: Zhi Wang <zhi.a.wang@gmail.com>, Christoph Hellwig <hch@lst.de>,
	"Jason Gunthorpe" <jgg@nvidia.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	Zhenyu Wang <zhenyuw@linux.intel.com>
Subject: Re: [PATCH v9 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g
Date: Tue, 12 Apr 2022 05:42:24 +0000	[thread overview]
Message-ID: <b2138ee5-20b0-f296-34df-29ed32edd1b1@intel.com> (raw)
In-Reply-To: <986b8ff0-d0de-437c-8a56-c54aafb6159a@intel.com>

Ping. :)

On 4/8/22 2:07 PM, Zhi Wang wrote:
> Hi Jani:
> 
> Thanks so much for the help. Can you generate a new tag on drm-intel-next? I noticed that there was one patch moving the DMC related registers into display/intel_dmc_regs.h, which is not included in the latest tag on drm-intel-next.
> 
> Guess it would be better that I can change this patch according to it when checking in. This would prevent a conflict in future.
> 
> Thanks,
> Zhi.
> 
> On 4/7/22 3:03 PM, Jani Nikula wrote:
>> On Thu, 07 Apr 2022, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
>>> index d7d3fb6186fd..7665d7cf0bdd 100644
>>> --- a/drivers/gpu/drm/i915/intel_gvt.h
>>> +++ b/drivers/gpu/drm/i915/intel_gvt.h
>>> @@ -26,7 +26,17 @@
>>>  
>>>  struct drm_i915_private;
>>>  
>>> +#include <linux/kernel.h>
>>
>> You only need <linux/types.h>. Please add it before the forward
>> declaration above.
>>
>>> +
>>>  #ifdef CONFIG_DRM_I915_GVT
>>> +
>>> +struct intel_gvt_mmio_table_iter {
>>> +	struct drm_i915_private *i915;
>>> +	void *data;
>>> +	int (*handle_mmio_cb)(struct intel_gvt_mmio_table_iter *iter,
>>> +			      u32 offset, u32 size);
>>> +};
>>> +
>>>  int intel_gvt_init(struct drm_i915_private *dev_priv);
>>>  void intel_gvt_driver_remove(struct drm_i915_private *dev_priv);
>>>  int intel_gvt_init_device(struct drm_i915_private *dev_priv);
>>> @@ -34,6 +44,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
>>>  int intel_gvt_init_host(void);
>>>  void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv);
>>>  void intel_gvt_resume(struct drm_i915_private *dev_priv);
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter);
>>>  #else
>>>  static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
>>>  {
>>> @@ -51,6 +62,16 @@ static inline void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>  static inline void intel_gvt_resume(struct drm_i915_private *dev_priv)
>>>  {
>>>  }
>>> +
>>> +unsigned long intel_gvt_get_device_type(struct drm_i915_private *i915)
>>> +{
>>> +	return 0;
>>> +}
>>
>> The CONFIG_DRM_I915_GVT=y counterpart for this is in mmio.h. Should be
>> both in the same header.
>>
>>> +
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter)
>>> +{
>>> +	return 0;
>>> +}
>>>  #endif
>>>  
>>>  #endif /* _INTEL_GVT_H_ */
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> new file mode 100644
>>> index 000000000000..d29491a6d209
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> @@ -0,0 +1,1290 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2020 Intel Corporation
>>> + */
>>> +
>>> +#include "i915_drv.h"
>>> +#include "i915_reg.h"
>>> +#include "display/vlv_dsi_pll_regs.h"
>>> +#include "gt/intel_gt_regs.h"
>>> +#include "intel_mchbar_regs.h"
>>> +#include "i915_pvinfo.h"
>>> +#include "intel_gvt.h"
>>> +#include "gvt/gvt.h"
>>
>> Generally we have the include lists sorted.
>>
>> Other than the nitpicks above, the series is
>>
>> Acked-by: Jani Nikula <jani.nikula@intel.com>
>>
>>
>> BR,
>> Jani.
>>
>>
> 


WARNING: multiple messages have this Message-ID (diff)
From: "Wang, Zhi A" <zhi.a.wang@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>,
	Zhi Wang <zhi.wang.linux@gmail.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-gvt-dev@lists.freedesktop.org"
	<intel-gvt-dev@lists.freedesktop.org>
Cc: Zhi Wang <zhi.a.wang@gmail.com>, Jason Gunthorpe <jgg@nvidia.com>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH v9 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g
Date: Tue, 12 Apr 2022 05:42:24 +0000	[thread overview]
Message-ID: <b2138ee5-20b0-f296-34df-29ed32edd1b1@intel.com> (raw)
In-Reply-To: <986b8ff0-d0de-437c-8a56-c54aafb6159a@intel.com>

Ping. :)

On 4/8/22 2:07 PM, Zhi Wang wrote:
> Hi Jani:
> 
> Thanks so much for the help. Can you generate a new tag on drm-intel-next? I noticed that there was one patch moving the DMC related registers into display/intel_dmc_regs.h, which is not included in the latest tag on drm-intel-next.
> 
> Guess it would be better that I can change this patch according to it when checking in. This would prevent a conflict in future.
> 
> Thanks,
> Zhi.
> 
> On 4/7/22 3:03 PM, Jani Nikula wrote:
>> On Thu, 07 Apr 2022, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
>>> index d7d3fb6186fd..7665d7cf0bdd 100644
>>> --- a/drivers/gpu/drm/i915/intel_gvt.h
>>> +++ b/drivers/gpu/drm/i915/intel_gvt.h
>>> @@ -26,7 +26,17 @@
>>>  
>>>  struct drm_i915_private;
>>>  
>>> +#include <linux/kernel.h>
>>
>> You only need <linux/types.h>. Please add it before the forward
>> declaration above.
>>
>>> +
>>>  #ifdef CONFIG_DRM_I915_GVT
>>> +
>>> +struct intel_gvt_mmio_table_iter {
>>> +	struct drm_i915_private *i915;
>>> +	void *data;
>>> +	int (*handle_mmio_cb)(struct intel_gvt_mmio_table_iter *iter,
>>> +			      u32 offset, u32 size);
>>> +};
>>> +
>>>  int intel_gvt_init(struct drm_i915_private *dev_priv);
>>>  void intel_gvt_driver_remove(struct drm_i915_private *dev_priv);
>>>  int intel_gvt_init_device(struct drm_i915_private *dev_priv);
>>> @@ -34,6 +44,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
>>>  int intel_gvt_init_host(void);
>>>  void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv);
>>>  void intel_gvt_resume(struct drm_i915_private *dev_priv);
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter);
>>>  #else
>>>  static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
>>>  {
>>> @@ -51,6 +62,16 @@ static inline void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>  static inline void intel_gvt_resume(struct drm_i915_private *dev_priv)
>>>  {
>>>  }
>>> +
>>> +unsigned long intel_gvt_get_device_type(struct drm_i915_private *i915)
>>> +{
>>> +	return 0;
>>> +}
>>
>> The CONFIG_DRM_I915_GVT=y counterpart for this is in mmio.h. Should be
>> both in the same header.
>>
>>> +
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter)
>>> +{
>>> +	return 0;
>>> +}
>>>  #endif
>>>  
>>>  #endif /* _INTEL_GVT_H_ */
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> new file mode 100644
>>> index 000000000000..d29491a6d209
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> @@ -0,0 +1,1290 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2020 Intel Corporation
>>> + */
>>> +
>>> +#include "i915_drv.h"
>>> +#include "i915_reg.h"
>>> +#include "display/vlv_dsi_pll_regs.h"
>>> +#include "gt/intel_gt_regs.h"
>>> +#include "intel_mchbar_regs.h"
>>> +#include "i915_pvinfo.h"
>>> +#include "intel_gvt.h"
>>> +#include "gvt/gvt.h"
>>
>> Generally we have the include lists sorted.
>>
>> Other than the nitpicks above, the series is
>>
>> Acked-by: Jani Nikula <jani.nikula@intel.com>
>>
>>
>> BR,
>> Jani.
>>
>>
> 


WARNING: multiple messages have this Message-ID (diff)
From: "Wang, Zhi A" <zhi.a.wang@intel.com>
To: Jani Nikula <jani.nikula@linux.intel.com>,
	Zhi Wang <zhi.wang.linux@gmail.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-gvt-dev@lists.freedesktop.org"
	<intel-gvt-dev@lists.freedesktop.org>
Cc: Zhi Wang <zhi.a.wang@gmail.com>, Jason Gunthorpe <jgg@nvidia.com>,
	"Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
	Christoph Hellwig <hch@lst.de>
Subject: Re: [Intel-gfx] [PATCH v9 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g
Date: Tue, 12 Apr 2022 05:42:24 +0000	[thread overview]
Message-ID: <b2138ee5-20b0-f296-34df-29ed32edd1b1@intel.com> (raw)
In-Reply-To: <986b8ff0-d0de-437c-8a56-c54aafb6159a@intel.com>

Ping. :)

On 4/8/22 2:07 PM, Zhi Wang wrote:
> Hi Jani:
> 
> Thanks so much for the help. Can you generate a new tag on drm-intel-next? I noticed that there was one patch moving the DMC related registers into display/intel_dmc_regs.h, which is not included in the latest tag on drm-intel-next.
> 
> Guess it would be better that I can change this patch according to it when checking in. This would prevent a conflict in future.
> 
> Thanks,
> Zhi.
> 
> On 4/7/22 3:03 PM, Jani Nikula wrote:
>> On Thu, 07 Apr 2022, Zhi Wang <zhi.wang.linux@gmail.com> wrote:
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt.h b/drivers/gpu/drm/i915/intel_gvt.h
>>> index d7d3fb6186fd..7665d7cf0bdd 100644
>>> --- a/drivers/gpu/drm/i915/intel_gvt.h
>>> +++ b/drivers/gpu/drm/i915/intel_gvt.h
>>> @@ -26,7 +26,17 @@
>>>  
>>>  struct drm_i915_private;
>>>  
>>> +#include <linux/kernel.h>
>>
>> You only need <linux/types.h>. Please add it before the forward
>> declaration above.
>>
>>> +
>>>  #ifdef CONFIG_DRM_I915_GVT
>>> +
>>> +struct intel_gvt_mmio_table_iter {
>>> +	struct drm_i915_private *i915;
>>> +	void *data;
>>> +	int (*handle_mmio_cb)(struct intel_gvt_mmio_table_iter *iter,
>>> +			      u32 offset, u32 size);
>>> +};
>>> +
>>>  int intel_gvt_init(struct drm_i915_private *dev_priv);
>>>  void intel_gvt_driver_remove(struct drm_i915_private *dev_priv);
>>>  int intel_gvt_init_device(struct drm_i915_private *dev_priv);
>>> @@ -34,6 +44,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv);
>>>  int intel_gvt_init_host(void);
>>>  void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv);
>>>  void intel_gvt_resume(struct drm_i915_private *dev_priv);
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter);
>>>  #else
>>>  static inline int intel_gvt_init(struct drm_i915_private *dev_priv)
>>>  {
>>> @@ -51,6 +62,16 @@ static inline void intel_gvt_sanitize_options(struct drm_i915_private *dev_priv)
>>>  static inline void intel_gvt_resume(struct drm_i915_private *dev_priv)
>>>  {
>>>  }
>>> +
>>> +unsigned long intel_gvt_get_device_type(struct drm_i915_private *i915)
>>> +{
>>> +	return 0;
>>> +}
>>
>> The CONFIG_DRM_I915_GVT=y counterpart for this is in mmio.h. Should be
>> both in the same header.
>>
>>> +
>>> +int intel_gvt_iterate_mmio_table(struct intel_gvt_mmio_table_iter *iter)
>>> +{
>>> +	return 0;
>>> +}
>>>  #endif
>>>  
>>>  #endif /* _INTEL_GVT_H_ */
>>> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> new file mode 100644
>>> index 000000000000..d29491a6d209
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
>>> @@ -0,0 +1,1290 @@
>>> +// SPDX-License-Identifier: MIT
>>> +/*
>>> + * Copyright © 2020 Intel Corporation
>>> + */
>>> +
>>> +#include "i915_drv.h"
>>> +#include "i915_reg.h"
>>> +#include "display/vlv_dsi_pll_regs.h"
>>> +#include "gt/intel_gt_regs.h"
>>> +#include "intel_mchbar_regs.h"
>>> +#include "i915_pvinfo.h"
>>> +#include "intel_gvt.h"
>>> +#include "gvt/gvt.h"
>>
>> Generally we have the include lists sorted.
>>
>> Other than the nitpicks above, the series is
>>
>> Acked-by: Jani Nikula <jani.nikula@intel.com>
>>
>>
>> BR,
>> Jani.
>>
>>
> 


  reply	other threads:[~2022-04-12  5:42 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-07  7:19 [PATCH v9 0/3] Refactor GVT-g MMIO tracking table and handlers Zhi Wang
2022-04-07  7:19 ` [Intel-gfx] " Zhi Wang
2022-04-07  7:19 ` [Intel-gfx] [PATCH v9 1/3] i915/gvt: Separate the MMIO tracking table from GVT-g Zhi Wang
2022-04-07  7:19   ` Zhi Wang
2022-04-07  7:19   ` Zhi Wang
2022-04-07  8:06   ` [Intel-gfx] " Christoph Hellwig
2022-04-07  8:06     ` Christoph Hellwig
2022-04-07 10:24     ` Wang, Zhi A
2022-04-07 10:24       ` [Intel-gfx] " Wang, Zhi A
2022-04-07 10:24       ` Wang, Zhi A
2022-04-07 13:20   ` Zhenyu Wang
2022-04-07 13:20     ` Zhenyu Wang
2022-04-07 13:20     ` [Intel-gfx] " Zhenyu Wang
2022-04-07 15:03   ` Jani Nikula
2022-04-07 15:03     ` [Intel-gfx] " Jani Nikula
2022-04-07 15:03     ` Jani Nikula
2022-04-08 14:07     ` Wang, Zhi A
2022-04-08 14:07       ` [Intel-gfx] " Wang, Zhi A
2022-04-08 14:07       ` Wang, Zhi A
2022-04-12  5:42       ` Wang, Zhi A [this message]
2022-04-12  5:42         ` [Intel-gfx] " Wang, Zhi A
2022-04-12  5:42         ` Wang, Zhi A
2022-04-13  9:31       ` Jani Nikula
2022-04-13  9:31         ` Jani Nikula
2022-04-13  9:31         ` [Intel-gfx] " Jani Nikula
2022-04-13  9:53         ` Wang, Zhi A
2022-04-13  9:53           ` [Intel-gfx] " Wang, Zhi A
2022-04-13  9:53           ` Wang, Zhi A
2022-04-13 10:18           ` Jani Nikula
2022-04-13 10:18             ` [Intel-gfx] " Jani Nikula
2022-04-13 10:18             ` Jani Nikula
2022-08-08 20:27   ` Alex Williamson
2022-08-08 20:27     ` [Intel-gfx] " Alex Williamson
2022-08-08 20:27     ` Alex Williamson
2022-04-07  7:19 ` [PATCH v9 2/3] i915/gvt: Save the initial HW state snapshot in i915 Zhi Wang
2022-04-07  7:19   ` Zhi Wang
2022-04-07  7:19   ` [Intel-gfx] " Zhi Wang
2022-04-07  7:19 ` [Intel-gfx] [PATCH v9 3/3] i915/gvt: Use the initial HW state snapshot saved " Zhi Wang
2022-04-07  7:19   ` Zhi Wang
2022-04-07  7:19   ` Zhi Wang
2022-04-07  7:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Refactor GVT-g MMIO tracking table and handlers (rev2) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=b2138ee5-20b0-f296-34df-29ed32edd1b1@intel.com \
    --to=zhi.a.wang@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=hch@lst.de \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=intel-gvt-dev@lists.freedesktop.org \
    --cc=jani.nikula@linux.intel.com \
    --cc=jgg@nvidia.com \
    --cc=joonas.lahtinen@linux.intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=rodrigo.vivi@intel.com \
    --cc=zhenyuw@linux.intel.com \
    --cc=zhi.a.wang@gmail.com \
    --cc=zhi.wang.linux@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.