[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-iio@vger.kernel.org
Cc: linux-rockchip@lists.infradead.org
Tested-by: Guenter Roeck <linux@roeck-us.net>

---

Changes in v3:
- %s/devm_reset_control_get_optional()/devm_reset_control_get()
- add Guente's test tag.

Changes in v2:
- Make the reset as an optional property, since it should work
with old devicetrees as well.

 .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
 drivers/iio/adc/Kconfig                            |  1 +
 drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
 3 files changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
index bf99e2f..205593f 100644
--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
@@ -16,6 +16,11 @@ Required properties:
 - vref-supply: The regulator supply ADC reference voltage.
 - #io-channel-cells: Should be 1, see ../iio-bindings.txt
 
+Optional properties:
+- resets: Must contain an entry for each entry in reset-names if need support
+	  this option. See ../reset/reset.txt for details.
+- reset-names: Must include the name "saradc-apb".
+
 Example:
 	saradc: saradc@2006c000 {
 		compatible = "rockchip,saradc";
@@ -23,6 +28,8 @@ Example:
 		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		#io-channel-cells = <1>;
 		vref-supply = <&vcc18>;
 	};
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 1de31bd..7675772 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
 config ROCKCHIP_SARADC
 	tristate "Rockchip SARADC driver"
 	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
+	depends on RESET_CONTROLLER
 	help
 	  Say yes here to build support for the SARADC found in SoCs from
 	  Rockchip.
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index f9ad6c2..85d7012 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -21,6 +21,8 @@
 #include <linux/of_device.h>
 #include <linux/clk.h>
 #include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
 #include <linux/regulator/consumer.h>
 #include <linux/iio/iio.h>
 
@@ -53,6 +55,7 @@ struct rockchip_saradc {
 	struct clk		*clk;
 	struct completion	completion;
 	struct regulator	*vref;
+	struct reset_control	*reset;
 	const struct rockchip_saradc_data *data;
 	u16			last_val;
 };
@@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
 };
 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
 
+/**
+ * Reset SARADC Controller.
+ */
+static void rockchip_saradc_reset_controller(struct reset_control *reset)
+{
+	reset_control_assert(reset);
+	usleep_range(10, 20);
+	reset_control_deassert(reset);
+}
+
 static int rockchip_saradc_probe(struct platform_device *pdev)
 {
 	struct rockchip_saradc *info = NULL;
@@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
 	if (IS_ERR(info->regs))
 		return PTR_ERR(info->regs);
 
+	/*
+	 * The reset should be an optional property, as it should work
+	 * with old devicetrees as well
+	 */
+	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
+	if (IS_ERR(info->reset)) {
+		ret = PTR_ERR(info->reset);
+		if (ret != -ENOENT)
+			return ret;
+
+		dev_dbg(&pdev->dev, "no reset control found\n");
+		info->reset = NULL;
+	}
+
 	init_completion(&info->completion);
 
 	irq = platform_get_irq(pdev, 0);
@@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
 		return PTR_ERR(info->vref);
 	}
 
+	if (info->reset)
+		rockchip_saradc_reset_controller(info->reset);
+
 	/*
 	 * Use a default value for the converter clock.
 	 * This may become user-configurable in the future.
-- 
1.9.1

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>

---

Changes in v3:
- %s/devm_reset_control_get_optional()/devm_reset_control_get()
- add Guente's test tag.

Changes in v2:
- Make the reset as an optional property, since it should work
with old devicetrees as well.

 .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
 drivers/iio/adc/Kconfig                            |  1 +
 drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
 3 files changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
index bf99e2f..205593f 100644
--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
@@ -16,6 +16,11 @@ Required properties:
 - vref-supply: The regulator supply ADC reference voltage.
 - #io-channel-cells: Should be 1, see ../iio-bindings.txt
 
+Optional properties:
+- resets: Must contain an entry for each entry in reset-names if need support
+	  this option. See ../reset/reset.txt for details.
+- reset-names: Must include the name "saradc-apb".
+
 Example:
 	saradc: saradc@2006c000 {
 		compatible = "rockchip,saradc";
@@ -23,6 +28,8 @@ Example:
 		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		#io-channel-cells = <1>;
 		vref-supply = <&vcc18>;
 	};
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 1de31bd..7675772 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
 config ROCKCHIP_SARADC
 	tristate "Rockchip SARADC driver"
 	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
+	depends on RESET_CONTROLLER
 	help
 	  Say yes here to build support for the SARADC found in SoCs from
 	  Rockchip.
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index f9ad6c2..85d7012 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -21,6 +21,8 @@
 #include <linux/of_device.h>
 #include <linux/clk.h>
 #include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
 #include <linux/regulator/consumer.h>
 #include <linux/iio/iio.h>
 
@@ -53,6 +55,7 @@ struct rockchip_saradc {
 	struct clk		*clk;
 	struct completion	completion;
 	struct regulator	*vref;
+	struct reset_control	*reset;
 	const struct rockchip_saradc_data *data;
 	u16			last_val;
 };
@@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
 };
 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
 
+/**
+ * Reset SARADC Controller.
+ */
+static void rockchip_saradc_reset_controller(struct reset_control *reset)
+{
+	reset_control_assert(reset);
+	usleep_range(10, 20);
+	reset_control_deassert(reset);
+}
+
 static int rockchip_saradc_probe(struct platform_device *pdev)
 {
 	struct rockchip_saradc *info = NULL;
@@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
 	if (IS_ERR(info->regs))
 		return PTR_ERR(info->regs);
 
+	/*
+	 * The reset should be an optional property, as it should work
+	 * with old devicetrees as well
+	 */
+	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
+	if (IS_ERR(info->reset)) {
+		ret = PTR_ERR(info->reset);
+		if (ret != -ENOENT)
+			return ret;
+
+		dev_dbg(&pdev->dev, "no reset control found\n");
+		info->reset = NULL;
+	}
+
 	init_completion(&info->completion);
 
 	irq = platform_get_irq(pdev, 0);
@@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
 		return PTR_ERR(info->vref);
 	}
 
+	if (info->reset)
+		rockchip_saradc_reset_controller(info->reset);
+
 	/*
 	 * Use a default value for the converter clock.
 	 * This may become user-configurable in the future.
-- 
1.9.1

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Cc: Jonathan Cameron <jic23@kernel.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-iio at vger.kernel.org
Cc: linux-rockchip at lists.infradead.org
Tested-by: Guenter Roeck <linux@roeck-us.net>

---

Changes in v3:
- %s/devm_reset_control_get_optional()/devm_reset_control_get()
- add Guente's test tag.

Changes in v2:
- Make the reset as an optional property, since it should work
with old devicetrees as well.

 .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
 drivers/iio/adc/Kconfig                            |  1 +
 drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
 3 files changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
index bf99e2f..205593f 100644
--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
@@ -16,6 +16,11 @@ Required properties:
 - vref-supply: The regulator supply ADC reference voltage.
 - #io-channel-cells: Should be 1, see ../iio-bindings.txt
 
+Optional properties:
+- resets: Must contain an entry for each entry in reset-names if need support
+	  this option. See ../reset/reset.txt for details.
+- reset-names: Must include the name "saradc-apb".
+
 Example:
 	saradc: saradc at 2006c000 {
 		compatible = "rockchip,saradc";
@@ -23,6 +28,8 @@ Example:
 		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		#io-channel-cells = <1>;
 		vref-supply = <&vcc18>;
 	};
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 1de31bd..7675772 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
 config ROCKCHIP_SARADC
 	tristate "Rockchip SARADC driver"
 	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
+	depends on RESET_CONTROLLER
 	help
 	  Say yes here to build support for the SARADC found in SoCs from
 	  Rockchip.
diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index f9ad6c2..85d7012 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -21,6 +21,8 @@
 #include <linux/of_device.h>
 #include <linux/clk.h>
 #include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
 #include <linux/regulator/consumer.h>
 #include <linux/iio/iio.h>
 
@@ -53,6 +55,7 @@ struct rockchip_saradc {
 	struct clk		*clk;
 	struct completion	completion;
 	struct regulator	*vref;
+	struct reset_control	*reset;
 	const struct rockchip_saradc_data *data;
 	u16			last_val;
 };
@@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
 };
 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
 
+/**
+ * Reset SARADC Controller.
+ */
+static void rockchip_saradc_reset_controller(struct reset_control *reset)
+{
+	reset_control_assert(reset);
+	usleep_range(10, 20);
+	reset_control_deassert(reset);
+}
+
 static int rockchip_saradc_probe(struct platform_device *pdev)
 {
 	struct rockchip_saradc *info = NULL;
@@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
 	if (IS_ERR(info->regs))
 		return PTR_ERR(info->regs);
 
+	/*
+	 * The reset should be an optional property, as it should work
+	 * with old devicetrees as well
+	 */
+	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
+	if (IS_ERR(info->reset)) {
+		ret = PTR_ERR(info->reset);
+		if (ret != -ENOENT)
+			return ret;
+
+		dev_dbg(&pdev->dev, "no reset control found\n");
+		info->reset = NULL;
+	}
+
 	init_completion(&info->completion);
 
 	irq = platform_get_irq(pdev, 0);
@@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
 		return PTR_ERR(info->vref);
 	}
 
+	if (info->reset)
+		rockchip_saradc_reset_controller(info->reset);
+
 	/*
 	 * Use a default value for the converter clock.
 	 * This may become user-configurable in the future.
-- 
1.9.1

[PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399

[Caesar Wang]

This patch adds saradc needed information on rk3399 SoCs.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4c84229..b81f84b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -299,6 +299,18 @@
 		};
 	};
 
+	saradc: saradc@ff100000 {
+		compatible = "rockchip,rk3399-saradc";
+		reg = <0x0 0xff100000 0x0 0x100>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_P_SARADC>;
+		reset-names = "saradc-apb";
+		status = "disabled";
+	};
+
 	i2c1: i2c@ff110000 {
 		compatible = "rockchip,rk3399-i2c";
 		reg = <0x0 0xff110000 0x0 0x1000>;
-- 
1.9.1

[PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399

[Caesar Wang]

This patch adds saradc needed information on rk3399 SoCs.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---

Changes in v3: None
Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 4c84229..b81f84b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -299,6 +299,18 @@
 		};
 	};
 
+	saradc: saradc at ff100000 {
+		compatible = "rockchip,rk3399-saradc";
+		reg = <0x0 0xff100000 0x0 0x100>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		#io-channel-cells = <1>;
+		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_P_SARADC>;
+		reset-names = "saradc-apb";
+		status = "disabled";
+	};
+
 	i2c1: i2c at ff110000 {
 		compatible = "rockchip,rk3399-i2c";
 		reg = <0x0 0xff110000 0x0 0x1000>;
-- 
1.9.1

[PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3:
- add Doug's reviewed tag.

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a9003..4f44d11 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -270,6 +270,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1

[PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

Changes in v3:
- add Doug's reviewed tag.

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a9003..4f44d11 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -270,6 +270,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1

[PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3:
- add Doug's reviewed tag.

Changes in v2: None

 arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index d02a9003..4f44d11 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -270,6 +270,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1

[PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/rk3066a.dtsi | 2 ++
 arch/arm/boot/dts/rk3288.dtsi  | 2 ++
 arch/arm/boot/dts/rk3xxx.dtsi  | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index c0ba86c..0d0dae3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -197,6 +197,8 @@
 		clock-names = "saradc", "apb_pclk";
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		#io-channel-cells = <1>;
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cd33f01..91c4b3c 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -279,6 +279,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 99bbcc2..e2cd683 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -399,6 +399,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1

[PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Caesar Wang]

SARADC controller needs to be reset before programming it, otherwise
it will not function properly.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/rk3066a.dtsi | 2 ++
 arch/arm/boot/dts/rk3288.dtsi  | 2 ++
 arch/arm/boot/dts/rk3xxx.dtsi  | 2 ++
 3 files changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index c0ba86c..0d0dae3 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -197,6 +197,8 @@
 		clock-names = "saradc", "apb_pclk";
 		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 		#io-channel-cells = <1>;
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index cd33f01..91c4b3c 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -279,6 +279,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 99bbcc2..e2cd683 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -399,6 +399,8 @@
 		#io-channel-cells = <1>;
 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 		clock-names = "saradc", "apb_pclk";
+		resets = <&cru SRST_SARADC>;
+		reset-names = "saradc-apb";
 		status = "disabled";
 	};
 
-- 
1.9.1

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Peter Meerwald-Stadler]

> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.

nitpicking on wording below
 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio@vger.kernel.org
> Cc: linux-rockchip@lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>
> 
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> index bf99e2f..205593f 100644
> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -16,6 +16,11 @@ Required properties:
>  - vref-supply: The regulator supply ADC reference voltage.
>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>  
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> +	  this option. See ../reset/reset.txt for details.

'... if need support this option.' doesn't sound right, maybe 
simply: '... if needed.' or drop this clause.

> +- reset-names: Must include the name "saradc-apb".
> +
>  Example:
>  	saradc: saradc@2006c000 {
>  		compatible = "rockchip,saradc";
> @@ -23,6 +28,8 @@ Example:
>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>  		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>  		#io-channel-cells = <1>;
>  		vref-supply = <&vcc18>;
>  	};
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 1de31bd..7675772 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>  config ROCKCHIP_SARADC
>  	tristate "Rockchip SARADC driver"
>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
> +	depends on RESET_CONTROLLER
>  	help
>  	  Say yes here to build support for the SARADC found in SoCs from
>  	  Rockchip.
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index f9ad6c2..85d7012 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -21,6 +21,8 @@
>  #include <linux/of_device.h>
>  #include <linux/clk.h>
>  #include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/iio/iio.h>
>  
> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>  	struct clk		*clk;
>  	struct completion	completion;
>  	struct regulator	*vref;
> +	struct reset_control	*reset;
>  	const struct rockchip_saradc_data *data;
>  	u16			last_val;
>  };
> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>  
> +/**
> + * Reset SARADC Controller.
> + */
> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
> +{
> +	reset_control_assert(reset);
> +	usleep_range(10, 20);
> +	reset_control_deassert(reset);
> +}
> +
>  static int rockchip_saradc_probe(struct platform_device *pdev)
>  {
>  	struct rockchip_saradc *info = NULL;
> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  	if (IS_ERR(info->regs))
>  		return PTR_ERR(info->regs);
>  
> +	/*
> +	 * The reset should be an optional property, as it should work
> +	 * with old devicetrees as well
> +	 */
> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
> +	if (IS_ERR(info->reset)) {
> +		ret = PTR_ERR(info->reset);
> +		if (ret != -ENOENT)
> +			return ret;
> +
> +		dev_dbg(&pdev->dev, "no reset control found\n");
> +		info->reset = NULL;
> +	}
> +
>  	init_completion(&info->completion);
>  
>  	irq = platform_get_irq(pdev, 0);
> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  		return PTR_ERR(info->vref);
>  	}
>  
> +	if (info->reset)
> +		rockchip_saradc_reset_controller(info->reset);
> +
>  	/*
>  	 * Use a default value for the converter clock.
>  	 * This may become user-configurable in the future.
> 

-- 

Peter Meerwald-Stadler
+43-664-2444418 (mobile)

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Peter Meerwald-Stadler]

> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.

nitpicking on wording below
 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio at vger.kernel.org
> Cc: linux-rockchip at lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>
> 
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> index bf99e2f..205593f 100644
> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -16,6 +16,11 @@ Required properties:
>  - vref-supply: The regulator supply ADC reference voltage.
>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>  
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> +	  this option. See ../reset/reset.txt for details.

'... if need support this option.' doesn't sound right, maybe 
simply: '... if needed.' or drop this clause.

> +- reset-names: Must include the name "saradc-apb".
> +
>  Example:
>  	saradc: saradc at 2006c000 {
>  		compatible = "rockchip,saradc";
> @@ -23,6 +28,8 @@ Example:
>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>  		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>  		#io-channel-cells = <1>;
>  		vref-supply = <&vcc18>;
>  	};
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 1de31bd..7675772 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>  config ROCKCHIP_SARADC
>  	tristate "Rockchip SARADC driver"
>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
> +	depends on RESET_CONTROLLER
>  	help
>  	  Say yes here to build support for the SARADC found in SoCs from
>  	  Rockchip.
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index f9ad6c2..85d7012 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -21,6 +21,8 @@
>  #include <linux/of_device.h>
>  #include <linux/clk.h>
>  #include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/iio/iio.h>
>  
> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>  	struct clk		*clk;
>  	struct completion	completion;
>  	struct regulator	*vref;
> +	struct reset_control	*reset;
>  	const struct rockchip_saradc_data *data;
>  	u16			last_val;
>  };
> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>  
> +/**
> + * Reset SARADC Controller.
> + */
> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
> +{
> +	reset_control_assert(reset);
> +	usleep_range(10, 20);
> +	reset_control_deassert(reset);
> +}
> +
>  static int rockchip_saradc_probe(struct platform_device *pdev)
>  {
>  	struct rockchip_saradc *info = NULL;
> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  	if (IS_ERR(info->regs))
>  		return PTR_ERR(info->regs);
>  
> +	/*
> +	 * The reset should be an optional property, as it should work
> +	 * with old devicetrees as well
> +	 */
> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
> +	if (IS_ERR(info->reset)) {
> +		ret = PTR_ERR(info->reset);
> +		if (ret != -ENOENT)
> +			return ret;
> +
> +		dev_dbg(&pdev->dev, "no reset control found\n");
> +		info->reset = NULL;
> +	}
> +
>  	init_completion(&info->completion);
>  
>  	irq = platform_get_irq(pdev, 0);
> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  		return PTR_ERR(info->vref);
>  	}
>  
> +	if (info->reset)
> +		rockchip_saradc_reset_controller(info->reset);
> +
>  	/*
>  	 * Use a default value for the converter clock.
>  	 * This may become user-configurable in the future.
> 

-- 

Peter Meerwald-Stadler
+43-664-2444418 (mobile)

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio@vger.kernel.org
> Cc: linux-rockchip@lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

>
> ---
>
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
>
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
>
>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>   drivers/iio/adc/Kconfig                            |  1 +
>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>   3 files changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> index bf99e2f..205593f 100644
> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -16,6 +16,11 @@ Required properties:
>   - vref-supply: The regulator supply ADC reference voltage.
>   - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> +	  this option. See ../reset/reset.txt for details.
> +- reset-names: Must include the name "saradc-apb".
> +
>   Example:
>   	saradc: saradc@2006c000 {
>   		compatible = "rockchip,saradc";
> @@ -23,6 +28,8 @@ Example:
>   		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		#io-channel-cells = <1>;
>   		vref-supply = <&vcc18>;
>   	};
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 1de31bd..7675772 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>   config ROCKCHIP_SARADC
>   	tristate "Rockchip SARADC driver"
>   	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
> +	depends on RESET_CONTROLLER
>   	help
>   	  Say yes here to build support for the SARADC found in SoCs from
>   	  Rockchip.
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index f9ad6c2..85d7012 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -21,6 +21,8 @@
>   #include <linux/of_device.h>
>   #include <linux/clk.h>
>   #include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
>   #include <linux/regulator/consumer.h>
>   #include <linux/iio/iio.h>
>
> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>   	struct clk		*clk;
>   	struct completion	completion;
>   	struct regulator	*vref;
> +	struct reset_control	*reset;
>   	const struct rockchip_saradc_data *data;
>   	u16			last_val;
>   };
> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>   };
>   MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>
> +/**
> + * Reset SARADC Controller.
> + */
> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
> +{
> +	reset_control_assert(reset);
> +	usleep_range(10, 20);
> +	reset_control_deassert(reset);
> +}
> +
>   static int rockchip_saradc_probe(struct platform_device *pdev)
>   {
>   	struct rockchip_saradc *info = NULL;
> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>   	if (IS_ERR(info->regs))
>   		return PTR_ERR(info->regs);
>
> +	/*
> +	 * The reset should be an optional property, as it should work
> +	 * with old devicetrees as well
> +	 */
> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
> +	if (IS_ERR(info->reset)) {
> +		ret = PTR_ERR(info->reset);
> +		if (ret != -ENOENT)
> +			return ret;
> +
> +		dev_dbg(&pdev->dev, "no reset control found\n");
> +		info->reset = NULL;
> +	}
> +
>   	init_completion(&info->completion);
>
>   	irq = platform_get_irq(pdev, 0);
> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>   		return PTR_ERR(info->vref);
>   	}
>
> +	if (info->reset)
> +		rockchip_saradc_reset_controller(info->reset);
> +
>   	/*
>   	 * Use a default value for the converter clock.
>   	 * This may become user-configurable in the future.
>

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio at vger.kernel.org
> Cc: linux-rockchip at lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

>
> ---
>
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
>
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
>
>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>   drivers/iio/adc/Kconfig                            |  1 +
>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>   3 files changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> index bf99e2f..205593f 100644
> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -16,6 +16,11 @@ Required properties:
>   - vref-supply: The regulator supply ADC reference voltage.
>   - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> +	  this option. See ../reset/reset.txt for details.
> +- reset-names: Must include the name "saradc-apb".
> +
>   Example:
>   	saradc: saradc at 2006c000 {
>   		compatible = "rockchip,saradc";
> @@ -23,6 +28,8 @@ Example:
>   		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		#io-channel-cells = <1>;
>   		vref-supply = <&vcc18>;
>   	};
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 1de31bd..7675772 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>   config ROCKCHIP_SARADC
>   	tristate "Rockchip SARADC driver"
>   	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
> +	depends on RESET_CONTROLLER
>   	help
>   	  Say yes here to build support for the SARADC found in SoCs from
>   	  Rockchip.
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index f9ad6c2..85d7012 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -21,6 +21,8 @@
>   #include <linux/of_device.h>
>   #include <linux/clk.h>
>   #include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
>   #include <linux/regulator/consumer.h>
>   #include <linux/iio/iio.h>
>
> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>   	struct clk		*clk;
>   	struct completion	completion;
>   	struct regulator	*vref;
> +	struct reset_control	*reset;
>   	const struct rockchip_saradc_data *data;
>   	u16			last_val;
>   };
> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>   };
>   MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>
> +/**
> + * Reset SARADC Controller.
> + */
> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
> +{
> +	reset_control_assert(reset);
> +	usleep_range(10, 20);
> +	reset_control_deassert(reset);
> +}
> +
>   static int rockchip_saradc_probe(struct platform_device *pdev)
>   {
>   	struct rockchip_saradc *info = NULL;
> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>   	if (IS_ERR(info->regs))
>   		return PTR_ERR(info->regs);
>
> +	/*
> +	 * The reset should be an optional property, as it should work
> +	 * with old devicetrees as well
> +	 */
> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
> +	if (IS_ERR(info->reset)) {
> +		ret = PTR_ERR(info->reset);
> +		if (ret != -ENOENT)
> +			return ret;
> +
> +		dev_dbg(&pdev->dev, "no reset control found\n");
> +		info->reset = NULL;
> +	}
> +
>   	init_completion(&info->completion);
>
>   	irq = platform_get_irq(pdev, 0);
> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>   		return PTR_ERR(info->vref);
>   	}
>
> +	if (info->reset)
> +		rockchip_saradc_reset_controller(info->reset);
> +
>   	/*
>   	 * Use a default value for the converter clock.
>   	 * This may become user-configurable in the future.
>

Re: [PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> This patch adds saradc needed information on rk3399 SoCs.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 4c84229..b81f84b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -299,6 +299,18 @@
>   		};
>   	};
>
> +	saradc: saradc@ff100000 {
> +		compatible = "rockchip,rk3399-saradc";
> +		reg = <0x0 0xff100000 0x0 0x100>;
> +		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +		#io-channel-cells = <1>;
> +		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
> +		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_P_SARADC>;
> +		reset-names = "saradc-apb";
> +		status = "disabled";
> +	};
> +
>   	i2c1: i2c@ff110000 {
>   		compatible = "rockchip,rk3399-i2c";
>   		reg = <0x0 0xff110000 0x0 0x1000>;
>

Re: [PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> This patch adds saradc needed information on rk3399 SoCs.
>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>

Reviewed-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 4c84229..b81f84b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -299,6 +299,18 @@
>   		};
>   	};
>
> +	saradc: saradc@ff100000 {
> +		compatible = "rockchip,rk3399-saradc";
> +		reg = <0x0 0xff100000 0x0 0x100>;
> +		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +		#io-channel-cells = <1>;
> +		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
> +		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_P_SARADC>;
> +		reset-names = "saradc-apb";
> +		status = "disabled";
> +	};
> +
>   	i2c1: i2c@ff110000 {
>   		compatible = "rockchip,rk3399-i2c";
>   		reg = <0x0 0xff110000 0x0 0x1000>;
>

[PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> This patch adds saradc needed information on rk3399 SoCs.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>   arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> index 4c84229..b81f84b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -299,6 +299,18 @@
>   		};
>   	};
>
> +	saradc: saradc at ff100000 {
> +		compatible = "rockchip,rk3399-saradc";
> +		reg = <0x0 0xff100000 0x0 0x100>;
> +		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> +		#io-channel-cells = <1>;
> +		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
> +		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_P_SARADC>;
> +		reset-names = "saradc-apb";
> +		status = "disabled";
> +	};
> +
>   	i2c1: i2c at ff110000 {
>   		compatible = "rockchip,rk3399-i2c";
>   		reg = <0x0 0xff110000 0x0 0x1000>;
>

Re: [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>
> Changes in v3:
> - add Doug's reviewed tag.
>
Not to this patch ?

> Changes in v2: None
>
>   arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index d02a9003..4f44d11 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -270,6 +270,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
>

Re: [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Reviewed-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>

> ---
>
> Changes in v3:
> - add Doug's reviewed tag.
>
Not to this patch ?

> Changes in v2: None
>
>   arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index d02a9003..4f44d11 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -270,6 +270,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
>

[PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>
> Changes in v3:
> - add Doug's reviewed tag.
>
Not to this patch ?

> Changes in v2: None
>
>   arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> index d02a9003..4f44d11 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
> @@ -270,6 +270,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
>

Re: [PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>   arch/arm/boot/dts/rk3066a.dtsi | 2 ++
>   arch/arm/boot/dts/rk3288.dtsi  | 2 ++
>   arch/arm/boot/dts/rk3xxx.dtsi  | 2 ++
>   3 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
> index c0ba86c..0d0dae3 100644
> --- a/arch/arm/boot/dts/rk3066a.dtsi
> +++ b/arch/arm/boot/dts/rk3066a.dtsi
> @@ -197,6 +197,8 @@
>   		clock-names = "saradc", "apb_pclk";
>   		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>   		#io-channel-cells = <1>;
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index cd33f01..91c4b3c 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -279,6 +279,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
> diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
> index 99bbcc2..e2cd683 100644
> --- a/arch/arm/boot/dts/rk3xxx.dtsi
> +++ b/arch/arm/boot/dts/rk3xxx.dtsi
> @@ -399,6 +399,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
>

Re: [PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Reviewed-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>   arch/arm/boot/dts/rk3066a.dtsi | 2 ++
>   arch/arm/boot/dts/rk3288.dtsi  | 2 ++
>   arch/arm/boot/dts/rk3xxx.dtsi  | 2 ++
>   3 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
> index c0ba86c..0d0dae3 100644
> --- a/arch/arm/boot/dts/rk3066a.dtsi
> +++ b/arch/arm/boot/dts/rk3066a.dtsi
> @@ -197,6 +197,8 @@
>   		clock-names = "saradc", "apb_pclk";
>   		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>   		#io-channel-cells = <1>;
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index cd33f01..91c4b3c 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -279,6 +279,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
> diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
> index 99bbcc2..e2cd683 100644
> --- a/arch/arm/boot/dts/rk3xxx.dtsi
> +++ b/arch/arm/boot/dts/rk3xxx.dtsi
> @@ -399,6 +399,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
>

[PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Guenter Roeck]

On 07/27/2016 07:24 AM, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>
> Changes in v3: None
> Changes in v2: None
>
>   arch/arm/boot/dts/rk3066a.dtsi | 2 ++
>   arch/arm/boot/dts/rk3288.dtsi  | 2 ++
>   arch/arm/boot/dts/rk3xxx.dtsi  | 2 ++
>   3 files changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
> index c0ba86c..0d0dae3 100644
> --- a/arch/arm/boot/dts/rk3066a.dtsi
> +++ b/arch/arm/boot/dts/rk3066a.dtsi
> @@ -197,6 +197,8 @@
>   		clock-names = "saradc", "apb_pclk";
>   		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
>   		#io-channel-cells = <1>;
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index cd33f01..91c4b3c 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -279,6 +279,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
> diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
> index 99bbcc2..e2cd683 100644
> --- a/arch/arm/boot/dts/rk3xxx.dtsi
> +++ b/arch/arm/boot/dts/rk3xxx.dtsi
> @@ -399,6 +399,8 @@
>   		#io-channel-cells = <1>;
>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>   		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>   		status = "disabled";
>   	};
>
>

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Rob Herring]

On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio@vger.kernel.org
> Cc: linux-rockchip@lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>
> 
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)

Please add acks when posting new versions.

Rob

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Rob Herring]

On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
> 
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)

Please add acks when posting new versions.

Rob

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Rob Herring]

On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio at vger.kernel.org
> Cc: linux-rockchip at lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>
> 
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)

Please add acks when posting new versions.

Rob

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016年07月30日 05:28, Rob Herring wrote:
> On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio@vger.kernel.org
>> Cc: linux-rockchip@lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
> Please add acks when posting new versions.

I didn't get your ACK when posting the V3. :-P

---
Your ack on 2016-07-27 23:12

  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++

Acked-by: Rob Herring<robh@kernel.org>



>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016年07月30日 05:28, Rob Herring wrote:
> On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio@vger.kernel.org
>> Cc: linux-rockchip@lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
> Please add acks when posting new versions.

I didn't get your ACK when posting the V3. :-P

---
Your ack on 2016-07-27 23:12

  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++

Acked-by: Rob Herring<robh@kernel.org>



>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip



_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016?07?30? 05:28, Rob Herring wrote:
> On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio at vger.kernel.org
>> Cc: linux-rockchip at lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
> Please add acks when posting new versions.

I didn't get your ACK when posting the V3. :-P

---
Your ack on 2016-07-27 23:12

  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++

Acked-by: Rob Herring<robh@kernel.org>



>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016年07月30日 05:28, Rob Herring wrote:
> On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio@vger.kernel.org
>> Cc: linux-rockchip@lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
> Please add acks when posting new versions.

I didn't get your ACK when posting the V3. :-P

---
Your ack on 2016-07-27 23:12

  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++

Acked-by: Rob Herring<robh@kernel.org>



>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
caesar wang | software engineer | wxt@rock-chip.com

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016年07月30日 05:28, Rob Herring wrote:
> On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
> Please add acks when posting new versions.

I didn't get your ACK when posting the V3. :-P

---
Your ack on 2016-07-27 23:12

  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++

Acked-by: Rob Herring<robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>



>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
caesar wang | software engineer | wxt-TNX95d0MmH73oGB3hsPCZA@public.gmane.org

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016?07?30? 05:28, Rob Herring wrote:
> On Wed, Jul 27, 2016 at 10:24:04PM +0800, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio at vger.kernel.org
>> Cc: linux-rockchip at lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
> Please add acks when posting new versions.

I didn't get your ACK when posting the V3. :-P

---
Your ack on 2016-07-27 23:12

  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++

Acked-by: Rob Herring<robh@kernel.org>



>
> Rob
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
caesar wang | software engineer | wxt at rock-chip.com

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016年07月27日 22:47, Peter Meerwald-Stadler wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
> nitpicking on wording below
>   
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio@vger.kernel.org
>> Cc: linux-rockchip@lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> index bf99e2f..205593f 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> @@ -16,6 +16,11 @@ Required properties:
>>   - vref-supply: The regulator supply ADC reference voltage.
>>   - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>   
>> +Optional properties:
>> +- resets: Must contain an entry for each entry in reset-names if need support
>> +	  this option. See ../reset/reset.txt for details.
> '... if need support this option.' doesn't sound right, maybe
> simply: '... if needed.' or drop this clause.

I don't plan to resend this series patches.
I'm assuming that Jonathan will help me fix it when ready to apply it.:-)

Glad to resend this series patches if Jonathan boss ask me to do.

Thanks,

Caesar

>
>> +- reset-names: Must include the name "saradc-apb".
>> +
>>   Example:
>>   	saradc: saradc@2006c000 {
>>   		compatible = "rockchip,saradc";
>> @@ -23,6 +28,8 @@ Example:
>>   		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>   		clock-names = "saradc", "apb_pclk";
>> +		resets = <&cru SRST_SARADC>;
>> +		reset-names = "saradc-apb";
>>   		#io-channel-cells = <1>;
>>   		vref-supply = <&vcc18>;
>>   	};
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 1de31bd..7675772 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>   config ROCKCHIP_SARADC
>>   	tristate "Rockchip SARADC driver"
>>   	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>> +	depends on RESET_CONTROLLER
>>   	help
>>   	  Say yes here to build support for the SARADC found in SoCs from
>>   	  Rockchip.
>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>> index f9ad6c2..85d7012 100644
>> --- a/drivers/iio/adc/rockchip_saradc.c
>> +++ b/drivers/iio/adc/rockchip_saradc.c
>> @@ -21,6 +21,8 @@
>>   #include <linux/of_device.h>
>>   #include <linux/clk.h>
>>   #include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>>   #include <linux/regulator/consumer.h>
>>   #include <linux/iio/iio.h>
>>   
>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>   	struct clk		*clk;
>>   	struct completion	completion;
>>   	struct regulator	*vref;
>> +	struct reset_control	*reset;
>>   	const struct rockchip_saradc_data *data;
>>   	u16			last_val;
>>   };
>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>   };
>>   MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>   
>> +/**
>> + * Reset SARADC Controller.
>> + */
>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>> +{
>> +	reset_control_assert(reset);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(reset);
>> +}
>> +
>>   static int rockchip_saradc_probe(struct platform_device *pdev)
>>   {
>>   	struct rockchip_saradc *info = NULL;
>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   	if (IS_ERR(info->regs))
>>   		return PTR_ERR(info->regs);
>>   
>> +	/*
>> +	 * The reset should be an optional property, as it should work
>> +	 * with old devicetrees as well
>> +	 */
>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>> +	if (IS_ERR(info->reset)) {
>> +		ret = PTR_ERR(info->reset);
>> +		if (ret != -ENOENT)
>> +			return ret;
>> +
>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>> +		info->reset = NULL;
>> +	}
>> +
>>   	init_completion(&info->completion);
>>   
>>   	irq = platform_get_irq(pdev, 0);
>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   		return PTR_ERR(info->vref);
>>   	}
>>   
>> +	if (info->reset)
>> +		rockchip_saradc_reset_controller(info->reset);
>> +
>>   	/*
>>   	 * Use a default value for the converter clock.
>>   	 * This may become user-configurable in the future.
>>


-- 
caesar wang | software engineer | wxt@rock-chip.com

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016年07月27日 22:47, Peter Meerwald-Stadler wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
> nitpicking on wording below
>   
>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> index bf99e2f..205593f 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> @@ -16,6 +16,11 @@ Required properties:
>>   - vref-supply: The regulator supply ADC reference voltage.
>>   - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>   
>> +Optional properties:
>> +- resets: Must contain an entry for each entry in reset-names if need support
>> +	  this option. See ../reset/reset.txt for details.
> '... if need support this option.' doesn't sound right, maybe
> simply: '... if needed.' or drop this clause.

I don't plan to resend this series patches.
I'm assuming that Jonathan will help me fix it when ready to apply it.:-)

Glad to resend this series patches if Jonathan boss ask me to do.

Thanks,

Caesar

>
>> +- reset-names: Must include the name "saradc-apb".
>> +
>>   Example:
>>   	saradc: saradc@2006c000 {
>>   		compatible = "rockchip,saradc";
>> @@ -23,6 +28,8 @@ Example:
>>   		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>   		clock-names = "saradc", "apb_pclk";
>> +		resets = <&cru SRST_SARADC>;
>> +		reset-names = "saradc-apb";
>>   		#io-channel-cells = <1>;
>>   		vref-supply = <&vcc18>;
>>   	};
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 1de31bd..7675772 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>   config ROCKCHIP_SARADC
>>   	tristate "Rockchip SARADC driver"
>>   	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>> +	depends on RESET_CONTROLLER
>>   	help
>>   	  Say yes here to build support for the SARADC found in SoCs from
>>   	  Rockchip.
>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>> index f9ad6c2..85d7012 100644
>> --- a/drivers/iio/adc/rockchip_saradc.c
>> +++ b/drivers/iio/adc/rockchip_saradc.c
>> @@ -21,6 +21,8 @@
>>   #include <linux/of_device.h>
>>   #include <linux/clk.h>
>>   #include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>>   #include <linux/regulator/consumer.h>
>>   #include <linux/iio/iio.h>
>>   
>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>   	struct clk		*clk;
>>   	struct completion	completion;
>>   	struct regulator	*vref;
>> +	struct reset_control	*reset;
>>   	const struct rockchip_saradc_data *data;
>>   	u16			last_val;
>>   };
>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>   };
>>   MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>   
>> +/**
>> + * Reset SARADC Controller.
>> + */
>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>> +{
>> +	reset_control_assert(reset);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(reset);
>> +}
>> +
>>   static int rockchip_saradc_probe(struct platform_device *pdev)
>>   {
>>   	struct rockchip_saradc *info = NULL;
>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   	if (IS_ERR(info->regs))
>>   		return PTR_ERR(info->regs);
>>   
>> +	/*
>> +	 * The reset should be an optional property, as it should work
>> +	 * with old devicetrees as well
>> +	 */
>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>> +	if (IS_ERR(info->reset)) {
>> +		ret = PTR_ERR(info->reset);
>> +		if (ret != -ENOENT)
>> +			return ret;
>> +
>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>> +		info->reset = NULL;
>> +	}
>> +
>>   	init_completion(&info->completion);
>>   
>>   	irq = platform_get_irq(pdev, 0);
>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   		return PTR_ERR(info->vref);
>>   	}
>>   
>> +	if (info->reset)
>> +		rockchip_saradc_reset_controller(info->reset);
>> +
>>   	/*
>>   	 * Use a default value for the converter clock.
>>   	 * This may become user-configurable in the future.
>>


-- 
caesar wang | software engineer | wxt-TNX95d0MmH73oGB3hsPCZA@public.gmane.org

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

On 2016?07?27? 22:47, Peter Meerwald-Stadler wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
> nitpicking on wording below
>   
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio at vger.kernel.org
>> Cc: linux-rockchip at lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> index bf99e2f..205593f 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> @@ -16,6 +16,11 @@ Required properties:
>>   - vref-supply: The regulator supply ADC reference voltage.
>>   - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>   
>> +Optional properties:
>> +- resets: Must contain an entry for each entry in reset-names if need support
>> +	  this option. See ../reset/reset.txt for details.
> '... if need support this option.' doesn't sound right, maybe
> simply: '... if needed.' or drop this clause.

I don't plan to resend this series patches.
I'm assuming that Jonathan will help me fix it when ready to apply it.:-)

Glad to resend this series patches if Jonathan boss ask me to do.

Thanks,

Caesar

>
>> +- reset-names: Must include the name "saradc-apb".
>> +
>>   Example:
>>   	saradc: saradc at 2006c000 {
>>   		compatible = "rockchip,saradc";
>> @@ -23,6 +28,8 @@ Example:
>>   		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>   		clock-names = "saradc", "apb_pclk";
>> +		resets = <&cru SRST_SARADC>;
>> +		reset-names = "saradc-apb";
>>   		#io-channel-cells = <1>;
>>   		vref-supply = <&vcc18>;
>>   	};
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 1de31bd..7675772 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>   config ROCKCHIP_SARADC
>>   	tristate "Rockchip SARADC driver"
>>   	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>> +	depends on RESET_CONTROLLER
>>   	help
>>   	  Say yes here to build support for the SARADC found in SoCs from
>>   	  Rockchip.
>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>> index f9ad6c2..85d7012 100644
>> --- a/drivers/iio/adc/rockchip_saradc.c
>> +++ b/drivers/iio/adc/rockchip_saradc.c
>> @@ -21,6 +21,8 @@
>>   #include <linux/of_device.h>
>>   #include <linux/clk.h>
>>   #include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>>   #include <linux/regulator/consumer.h>
>>   #include <linux/iio/iio.h>
>>   
>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>   	struct clk		*clk;
>>   	struct completion	completion;
>>   	struct regulator	*vref;
>> +	struct reset_control	*reset;
>>   	const struct rockchip_saradc_data *data;
>>   	u16			last_val;
>>   };
>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>   };
>>   MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>   
>> +/**
>> + * Reset SARADC Controller.
>> + */
>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>> +{
>> +	reset_control_assert(reset);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(reset);
>> +}
>> +
>>   static int rockchip_saradc_probe(struct platform_device *pdev)
>>   {
>>   	struct rockchip_saradc *info = NULL;
>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   	if (IS_ERR(info->regs))
>>   		return PTR_ERR(info->regs);
>>   
>> +	/*
>> +	 * The reset should be an optional property, as it should work
>> +	 * with old devicetrees as well
>> +	 */
>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>> +	if (IS_ERR(info->reset)) {
>> +		ret = PTR_ERR(info->reset);
>> +		if (ret != -ENOENT)
>> +			return ret;
>> +
>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>> +		info->reset = NULL;
>> +	}
>> +
>>   	init_completion(&info->completion);
>>   
>>   	irq = platform_get_irq(pdev, 0);
>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   		return PTR_ERR(info->vref);
>>   	}
>>   
>> +	if (info->reset)
>> +		rockchip_saradc_reset_controller(info->reset);
>> +
>>   	/*
>>   	 * Use a default value for the converter clock.
>>   	 * This may become user-configurable in the future.
>>


-- 
caesar wang | software engineer | wxt at rock-chip.com

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 27/07/16 15:24, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio@vger.kernel.org
> Cc: linux-rockchip@lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>
> 
Hi

Patch is fine (I'll fix up the wording issue) however...

I'm not clear on the severity of the issue. Is this something
we should be pushing for stable?

Jonathan
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> index bf99e2f..205593f 100644
> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -16,6 +16,11 @@ Required properties:
>  - vref-supply: The regulator supply ADC reference voltage.
>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>  
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> +	  this option. See ../reset/reset.txt for details.
> +- reset-names: Must include the name "saradc-apb".
> +
>  Example:
>  	saradc: saradc@2006c000 {
>  		compatible = "rockchip,saradc";
> @@ -23,6 +28,8 @@ Example:
>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>  		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>  		#io-channel-cells = <1>;
>  		vref-supply = <&vcc18>;
>  	};
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 1de31bd..7675772 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>  config ROCKCHIP_SARADC
>  	tristate "Rockchip SARADC driver"
>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
> +	depends on RESET_CONTROLLER
>  	help
>  	  Say yes here to build support for the SARADC found in SoCs from
>  	  Rockchip.
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index f9ad6c2..85d7012 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -21,6 +21,8 @@
>  #include <linux/of_device.h>
>  #include <linux/clk.h>
>  #include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/iio/iio.h>
>  
> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>  	struct clk		*clk;
>  	struct completion	completion;
>  	struct regulator	*vref;
> +	struct reset_control	*reset;
>  	const struct rockchip_saradc_data *data;
>  	u16			last_val;
>  };
> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>  
> +/**
> + * Reset SARADC Controller.
> + */
> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
> +{
> +	reset_control_assert(reset);
> +	usleep_range(10, 20);
> +	reset_control_deassert(reset);
> +}
> +
>  static int rockchip_saradc_probe(struct platform_device *pdev)
>  {
>  	struct rockchip_saradc *info = NULL;
> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  	if (IS_ERR(info->regs))
>  		return PTR_ERR(info->regs);
>  
> +	/*
> +	 * The reset should be an optional property, as it should work
> +	 * with old devicetrees as well
> +	 */
> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
> +	if (IS_ERR(info->reset)) {
> +		ret = PTR_ERR(info->reset);
> +		if (ret != -ENOENT)
> +			return ret;
> +
> +		dev_dbg(&pdev->dev, "no reset control found\n");
> +		info->reset = NULL;
> +	}
> +
>  	init_completion(&info->completion);
>  
>  	irq = platform_get_irq(pdev, 0);
> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  		return PTR_ERR(info->vref);
>  	}
>  
> +	if (info->reset)
> +		rockchip_saradc_reset_controller(info->reset);
> +
>  	/*
>  	 * Use a default value for the converter clock.
>  	 * This may become user-configurable in the future.
> 

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 27/07/16 15:24, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
> 
Hi

Patch is fine (I'll fix up the wording issue) however...

I'm not clear on the severity of the issue. Is this something
we should be pushing for stable?

Jonathan
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> index bf99e2f..205593f 100644
> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -16,6 +16,11 @@ Required properties:
>  - vref-supply: The regulator supply ADC reference voltage.
>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>  
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> +	  this option. See ../reset/reset.txt for details.
> +- reset-names: Must include the name "saradc-apb".
> +
>  Example:
>  	saradc: saradc@2006c000 {
>  		compatible = "rockchip,saradc";
> @@ -23,6 +28,8 @@ Example:
>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>  		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>  		#io-channel-cells = <1>;
>  		vref-supply = <&vcc18>;
>  	};
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 1de31bd..7675772 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>  config ROCKCHIP_SARADC
>  	tristate "Rockchip SARADC driver"
>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
> +	depends on RESET_CONTROLLER
>  	help
>  	  Say yes here to build support for the SARADC found in SoCs from
>  	  Rockchip.
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index f9ad6c2..85d7012 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -21,6 +21,8 @@
>  #include <linux/of_device.h>
>  #include <linux/clk.h>
>  #include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/iio/iio.h>
>  
> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>  	struct clk		*clk;
>  	struct completion	completion;
>  	struct regulator	*vref;
> +	struct reset_control	*reset;
>  	const struct rockchip_saradc_data *data;
>  	u16			last_val;
>  };
> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>  
> +/**
> + * Reset SARADC Controller.
> + */
> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
> +{
> +	reset_control_assert(reset);
> +	usleep_range(10, 20);
> +	reset_control_deassert(reset);
> +}
> +
>  static int rockchip_saradc_probe(struct platform_device *pdev)
>  {
>  	struct rockchip_saradc *info = NULL;
> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  	if (IS_ERR(info->regs))
>  		return PTR_ERR(info->regs);
>  
> +	/*
> +	 * The reset should be an optional property, as it should work
> +	 * with old devicetrees as well
> +	 */
> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
> +	if (IS_ERR(info->reset)) {
> +		ret = PTR_ERR(info->reset);
> +		if (ret != -ENOENT)
> +			return ret;
> +
> +		dev_dbg(&pdev->dev, "no reset control found\n");
> +		info->reset = NULL;
> +	}
> +
>  	init_completion(&info->completion);
>  
>  	irq = platform_get_irq(pdev, 0);
> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  		return PTR_ERR(info->vref);
>  	}
>  
> +	if (info->reset)
> +		rockchip_saradc_reset_controller(info->reset);
> +
>  	/*
>  	 * Use a default value for the converter clock.
>  	 * This may become user-configurable in the future.
> 

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 27/07/16 15:24, Caesar Wang wrote:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Cc: Jonathan Cameron <jic23@kernel.org>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-iio at vger.kernel.org
> Cc: linux-rockchip at lists.infradead.org
> Tested-by: Guenter Roeck <linux@roeck-us.net>
> 
Hi

Patch is fine (I'll fix up the wording issue) however...

I'm not clear on the severity of the issue. Is this something
we should be pushing for stable?

Jonathan
> ---
> 
> Changes in v3:
> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
> - add Guente's test tag.
> 
> Changes in v2:
> - Make the reset as an optional property, since it should work
> with old devicetrees as well.
> 
>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>  drivers/iio/adc/Kconfig                            |  1 +
>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>  3 files changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> index bf99e2f..205593f 100644
> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
> @@ -16,6 +16,11 @@ Required properties:
>  - vref-supply: The regulator supply ADC reference voltage.
>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>  
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> +	  this option. See ../reset/reset.txt for details.
> +- reset-names: Must include the name "saradc-apb".
> +
>  Example:
>  	saradc: saradc at 2006c000 {
>  		compatible = "rockchip,saradc";
> @@ -23,6 +28,8 @@ Example:
>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>  		clock-names = "saradc", "apb_pclk";
> +		resets = <&cru SRST_SARADC>;
> +		reset-names = "saradc-apb";
>  		#io-channel-cells = <1>;
>  		vref-supply = <&vcc18>;
>  	};
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 1de31bd..7675772 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>  config ROCKCHIP_SARADC
>  	tristate "Rockchip SARADC driver"
>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
> +	depends on RESET_CONTROLLER
>  	help
>  	  Say yes here to build support for the SARADC found in SoCs from
>  	  Rockchip.
> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
> index f9ad6c2..85d7012 100644
> --- a/drivers/iio/adc/rockchip_saradc.c
> +++ b/drivers/iio/adc/rockchip_saradc.c
> @@ -21,6 +21,8 @@
>  #include <linux/of_device.h>
>  #include <linux/clk.h>
>  #include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/iio/iio.h>
>  
> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>  	struct clk		*clk;
>  	struct completion	completion;
>  	struct regulator	*vref;
> +	struct reset_control	*reset;
>  	const struct rockchip_saradc_data *data;
>  	u16			last_val;
>  };
> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>  };
>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>  
> +/**
> + * Reset SARADC Controller.
> + */
> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
> +{
> +	reset_control_assert(reset);
> +	usleep_range(10, 20);
> +	reset_control_deassert(reset);
> +}
> +
>  static int rockchip_saradc_probe(struct platform_device *pdev)
>  {
>  	struct rockchip_saradc *info = NULL;
> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  	if (IS_ERR(info->regs))
>  		return PTR_ERR(info->regs);
>  
> +	/*
> +	 * The reset should be an optional property, as it should work
> +	 * with old devicetrees as well
> +	 */
> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
> +	if (IS_ERR(info->reset)) {
> +		ret = PTR_ERR(info->reset);
> +		if (ret != -ENOENT)
> +			return ret;
> +
> +		dev_dbg(&pdev->dev, "no reset control found\n");
> +		info->reset = NULL;
> +	}
> +
>  	init_completion(&info->completion);
>  
>  	irq = platform_get_irq(pdev, 0);
> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>  		return PTR_ERR(info->vref);
>  	}
>  
> +	if (info->reset)
> +		rockchip_saradc_reset_controller(info->reset);
> +
>  	/*
>  	 * Use a default value for the converter clock.
>  	 * This may become user-configurable in the future.
> 

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 15/08/16 18:41, Jonathan Cameron wrote:
> On 27/07/16 15:24, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio@vger.kernel.org
>> Cc: linux-rockchip@lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
> Hi
> 
> Patch is fine (I'll fix up the wording issue) however...
> 
> I'm not clear on the severity of the issue. Is this something
> we should be pushing for stable?
To add to this, it's only useful to take this for stable if we
are also fine taking the device tree updates to make it actually
do something!

> 
> Jonathan
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>  drivers/iio/adc/Kconfig                            |  1 +
>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>  3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> index bf99e2f..205593f 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> @@ -16,6 +16,11 @@ Required properties:
>>  - vref-supply: The regulator supply ADC reference voltage.
>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>  
>> +Optional properties:
>> +- resets: Must contain an entry for each entry in reset-names if need support
>> +	  this option. See ../reset/reset.txt for details.
>> +- reset-names: Must include the name "saradc-apb".
>> +
>>  Example:
>>  	saradc: saradc@2006c000 {
>>  		compatible = "rockchip,saradc";
>> @@ -23,6 +28,8 @@ Example:
>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>  		clock-names = "saradc", "apb_pclk";
>> +		resets = <&cru SRST_SARADC>;
>> +		reset-names = "saradc-apb";
>>  		#io-channel-cells = <1>;
>>  		vref-supply = <&vcc18>;
>>  	};
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 1de31bd..7675772 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>  config ROCKCHIP_SARADC
>>  	tristate "Rockchip SARADC driver"
>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>> +	depends on RESET_CONTROLLER
>>  	help
>>  	  Say yes here to build support for the SARADC found in SoCs from
>>  	  Rockchip.
>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>> index f9ad6c2..85d7012 100644
>> --- a/drivers/iio/adc/rockchip_saradc.c
>> +++ b/drivers/iio/adc/rockchip_saradc.c
>> @@ -21,6 +21,8 @@
>>  #include <linux/of_device.h>
>>  #include <linux/clk.h>
>>  #include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>>  #include <linux/regulator/consumer.h>
>>  #include <linux/iio/iio.h>
>>  
>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>  	struct clk		*clk;
>>  	struct completion	completion;
>>  	struct regulator	*vref;
>> +	struct reset_control	*reset;
>>  	const struct rockchip_saradc_data *data;
>>  	u16			last_val;
>>  };
>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>  };
>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>  
>> +/**
>> + * Reset SARADC Controller.
>> + */
>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>> +{
>> +	reset_control_assert(reset);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(reset);
>> +}
>> +
>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>  {
>>  	struct rockchip_saradc *info = NULL;
>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>  	if (IS_ERR(info->regs))
>>  		return PTR_ERR(info->regs);
>>  
>> +	/*
>> +	 * The reset should be an optional property, as it should work
>> +	 * with old devicetrees as well
>> +	 */
>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>> +	if (IS_ERR(info->reset)) {
>> +		ret = PTR_ERR(info->reset);
>> +		if (ret != -ENOENT)
>> +			return ret;
>> +
>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>> +		info->reset = NULL;
>> +	}
>> +
>>  	init_completion(&info->completion);
>>  
>>  	irq = platform_get_irq(pdev, 0);
>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>  		return PTR_ERR(info->vref);
>>  	}
>>  
>> +	if (info->reset)
>> +		rockchip_saradc_reset_controller(info->reset);
>> +
>>  	/*
>>  	 * Use a default value for the converter clock.
>>  	 * This may become user-configurable in the future.
>>
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 15/08/16 18:41, Jonathan Cameron wrote:
> On 27/07/16 15:24, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
>>
> Hi
> 
> Patch is fine (I'll fix up the wording issue) however...
> 
> I'm not clear on the severity of the issue. Is this something
> we should be pushing for stable?
To add to this, it's only useful to take this for stable if we
are also fine taking the device tree updates to make it actually
do something!

> 
> Jonathan
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>  drivers/iio/adc/Kconfig                            |  1 +
>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>  3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> index bf99e2f..205593f 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> @@ -16,6 +16,11 @@ Required properties:
>>  - vref-supply: The regulator supply ADC reference voltage.
>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>  
>> +Optional properties:
>> +- resets: Must contain an entry for each entry in reset-names if need support
>> +	  this option. See ../reset/reset.txt for details.
>> +- reset-names: Must include the name "saradc-apb".
>> +
>>  Example:
>>  	saradc: saradc@2006c000 {
>>  		compatible = "rockchip,saradc";
>> @@ -23,6 +28,8 @@ Example:
>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>  		clock-names = "saradc", "apb_pclk";
>> +		resets = <&cru SRST_SARADC>;
>> +		reset-names = "saradc-apb";
>>  		#io-channel-cells = <1>;
>>  		vref-supply = <&vcc18>;
>>  	};
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 1de31bd..7675772 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>  config ROCKCHIP_SARADC
>>  	tristate "Rockchip SARADC driver"
>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>> +	depends on RESET_CONTROLLER
>>  	help
>>  	  Say yes here to build support for the SARADC found in SoCs from
>>  	  Rockchip.
>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>> index f9ad6c2..85d7012 100644
>> --- a/drivers/iio/adc/rockchip_saradc.c
>> +++ b/drivers/iio/adc/rockchip_saradc.c
>> @@ -21,6 +21,8 @@
>>  #include <linux/of_device.h>
>>  #include <linux/clk.h>
>>  #include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>>  #include <linux/regulator/consumer.h>
>>  #include <linux/iio/iio.h>
>>  
>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>  	struct clk		*clk;
>>  	struct completion	completion;
>>  	struct regulator	*vref;
>> +	struct reset_control	*reset;
>>  	const struct rockchip_saradc_data *data;
>>  	u16			last_val;
>>  };
>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>  };
>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>  
>> +/**
>> + * Reset SARADC Controller.
>> + */
>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>> +{
>> +	reset_control_assert(reset);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(reset);
>> +}
>> +
>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>  {
>>  	struct rockchip_saradc *info = NULL;
>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>  	if (IS_ERR(info->regs))
>>  		return PTR_ERR(info->regs);
>>  
>> +	/*
>> +	 * The reset should be an optional property, as it should work
>> +	 * with old devicetrees as well
>> +	 */
>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>> +	if (IS_ERR(info->reset)) {
>> +		ret = PTR_ERR(info->reset);
>> +		if (ret != -ENOENT)
>> +			return ret;
>> +
>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>> +		info->reset = NULL;
>> +	}
>> +
>>  	init_completion(&info->completion);
>>  
>>  	irq = platform_get_irq(pdev, 0);
>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>  		return PTR_ERR(info->vref);
>>  	}
>>  
>> +	if (info->reset)
>> +		rockchip_saradc_reset_controller(info->reset);
>> +
>>  	/*
>>  	 * Use a default value for the converter clock.
>>  	 * This may become user-configurable in the future.
>>
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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> 

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[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 15/08/16 18:41, Jonathan Cameron wrote:
> On 27/07/16 15:24, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio at vger.kernel.org
>> Cc: linux-rockchip at lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
> Hi
> 
> Patch is fine (I'll fix up the wording issue) however...
> 
> I'm not clear on the severity of the issue. Is this something
> we should be pushing for stable?
To add to this, it's only useful to take this for stable if we
are also fine taking the device tree updates to make it actually
do something!

> 
> Jonathan
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>  drivers/iio/adc/Kconfig                            |  1 +
>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>  3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> index bf99e2f..205593f 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> @@ -16,6 +16,11 @@ Required properties:
>>  - vref-supply: The regulator supply ADC reference voltage.
>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>  
>> +Optional properties:
>> +- resets: Must contain an entry for each entry in reset-names if need support
>> +	  this option. See ../reset/reset.txt for details.
>> +- reset-names: Must include the name "saradc-apb".
>> +
>>  Example:
>>  	saradc: saradc at 2006c000 {
>>  		compatible = "rockchip,saradc";
>> @@ -23,6 +28,8 @@ Example:
>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>  		clock-names = "saradc", "apb_pclk";
>> +		resets = <&cru SRST_SARADC>;
>> +		reset-names = "saradc-apb";
>>  		#io-channel-cells = <1>;
>>  		vref-supply = <&vcc18>;
>>  	};
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 1de31bd..7675772 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>  config ROCKCHIP_SARADC
>>  	tristate "Rockchip SARADC driver"
>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>> +	depends on RESET_CONTROLLER
>>  	help
>>  	  Say yes here to build support for the SARADC found in SoCs from
>>  	  Rockchip.
>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>> index f9ad6c2..85d7012 100644
>> --- a/drivers/iio/adc/rockchip_saradc.c
>> +++ b/drivers/iio/adc/rockchip_saradc.c
>> @@ -21,6 +21,8 @@
>>  #include <linux/of_device.h>
>>  #include <linux/clk.h>
>>  #include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>>  #include <linux/regulator/consumer.h>
>>  #include <linux/iio/iio.h>
>>  
>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>  	struct clk		*clk;
>>  	struct completion	completion;
>>  	struct regulator	*vref;
>> +	struct reset_control	*reset;
>>  	const struct rockchip_saradc_data *data;
>>  	u16			last_val;
>>  };
>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>  };
>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>  
>> +/**
>> + * Reset SARADC Controller.
>> + */
>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>> +{
>> +	reset_control_assert(reset);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(reset);
>> +}
>> +
>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>  {
>>  	struct rockchip_saradc *info = NULL;
>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>  	if (IS_ERR(info->regs))
>>  		return PTR_ERR(info->regs);
>>  
>> +	/*
>> +	 * The reset should be an optional property, as it should work
>> +	 * with old devicetrees as well
>> +	 */
>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>> +	if (IS_ERR(info->reset)) {
>> +		ret = PTR_ERR(info->reset);
>> +		if (ret != -ENOENT)
>> +			return ret;
>> +
>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>> +		info->reset = NULL;
>> +	}
>> +
>>  	init_completion(&info->completion);
>>  
>>  	irq = platform_get_irq(pdev, 0);
>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>  		return PTR_ERR(info->vref);
>>  	}
>>  
>> +	if (info->reset)
>> +		rockchip_saradc_reset_controller(info->reset);
>> +
>>  	/*
>>  	 * Use a default value for the converter clock.
>>  	 * This may become user-configurable in the future.
>>
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
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> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Caesar Wang]

[-- Attachment #1: Type: text/plain, Size: 5663 bytes --]


On 2016?08?16? 01:41, Jonathan Cameron wrote:
> On 27/07/16 15:24, Caesar Wang wrote:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> Cc: Jonathan Cameron <jic23@kernel.org>
>> Cc: Heiko Stuebner <heiko@sntech.de>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: linux-iio@vger.kernel.org
>> Cc: linux-rockchip@lists.infradead.org
>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>
> Hi
>
> Patch is fine (I'll fix up the wording issue) however...
>
> I'm not clear on the severity of the issue. Is this something
> we should be pushing for stable?

I think that should be pushing for stable, since the common isssue for 
the ADC is initially enabled on loader,
and only disabled after the first read.

cat /sys/class/hwmon/hwmon1/device/temp1_input
cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out

The kernel log shows:

[ 32.209451] read channel() error: -110
..

Also, for my experience. Some other reasons caused the adc (controller) 
glitch for the kernel side.

-
Caesar

> Jonathan
>> ---
>>
>> Changes in v3:
>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>> - add Guente's test tag.
>>
>> Changes in v2:
>> - Make the reset as an optional property, since it should work
>> with old devicetrees as well.
>>
>>   .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>   drivers/iio/adc/Kconfig                            |  1 +
>>   drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>   3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> index bf99e2f..205593f 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>> @@ -16,6 +16,11 @@ Required properties:
>>   - vref-supply: The regulator supply ADC reference voltage.
>>   - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>   
>> +Optional properties:
>> +- resets: Must contain an entry for each entry in reset-names if need support
>> +	  this option. See ../reset/reset.txt for details.
>> +- reset-names: Must include the name "saradc-apb".
>> +
>>   Example:
>>   	saradc: saradc@2006c000 {
>>   		compatible = "rockchip,saradc";
>> @@ -23,6 +28,8 @@ Example:
>>   		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>   		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>   		clock-names = "saradc", "apb_pclk";
>> +		resets = <&cru SRST_SARADC>;
>> +		reset-names = "saradc-apb";
>>   		#io-channel-cells = <1>;
>>   		vref-supply = <&vcc18>;
>>   	};
>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>> index 1de31bd..7675772 100644
>> --- a/drivers/iio/adc/Kconfig
>> +++ b/drivers/iio/adc/Kconfig
>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>   config ROCKCHIP_SARADC
>>   	tristate "Rockchip SARADC driver"
>>   	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>> +	depends on RESET_CONTROLLER
>>   	help
>>   	  Say yes here to build support for the SARADC found in SoCs from
>>   	  Rockchip.
>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>> index f9ad6c2..85d7012 100644
>> --- a/drivers/iio/adc/rockchip_saradc.c
>> +++ b/drivers/iio/adc/rockchip_saradc.c
>> @@ -21,6 +21,8 @@
>>   #include <linux/of_device.h>
>>   #include <linux/clk.h>
>>   #include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/reset.h>
>>   #include <linux/regulator/consumer.h>
>>   #include <linux/iio/iio.h>
>>   
>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>   	struct clk		*clk;
>>   	struct completion	completion;
>>   	struct regulator	*vref;
>> +	struct reset_control	*reset;
>>   	const struct rockchip_saradc_data *data;
>>   	u16			last_val;
>>   };
>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>   };
>>   MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>   
>> +/**
>> + * Reset SARADC Controller.
>> + */
>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>> +{
>> +	reset_control_assert(reset);
>> +	usleep_range(10, 20);
>> +	reset_control_deassert(reset);
>> +}
>> +
>>   static int rockchip_saradc_probe(struct platform_device *pdev)
>>   {
>>   	struct rockchip_saradc *info = NULL;
>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   	if (IS_ERR(info->regs))
>>   		return PTR_ERR(info->regs);
>>   
>> +	/*
>> +	 * The reset should be an optional property, as it should work
>> +	 * with old devicetrees as well
>> +	 */
>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>> +	if (IS_ERR(info->reset)) {
>> +		ret = PTR_ERR(info->reset);
>> +		if (ret != -ENOENT)
>> +			return ret;
>> +
>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>> +		info->reset = NULL;
>> +	}
>> +
>>   	init_completion(&info->completion);
>>   
>>   	irq = platform_get_irq(pdev, 0);
>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>   		return PTR_ERR(info->vref);
>>   	}
>>   
>> +	if (info->reset)
>> +		rockchip_saradc_reset_controller(info->reset);
>> +
>>   	/*
>>   	 * Use a default value for the converter clock.
>>   	 * This may become user-configurable in the future.
>>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
caesar wang | software engineer | wxt@rock-chip.com


[-- Attachment #2: Type: text/html, Size: 7175 bytes --]

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 15/08/16 19:10, Caesar Wang wrote:
> 
> On 2016年08月16日 01:41, Jonathan Cameron wrote:
>> On 27/07/16 15:24, Caesar Wang wrote:
>>> SARADC controller needs to be reset before programming it, otherwise
>>> it will not function properly.
>>>
>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>>> Cc: Jonathan Cameron <jic23@kernel.org>
>>> Cc: Heiko Stuebner <heiko@sntech.de>
>>> Cc: Rob Herring <robh+dt@kernel.org>
>>> Cc: linux-iio@vger.kernel.org
>>> Cc: linux-rockchip@lists.infradead.org
>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>>
>> Hi
>>
>> Patch is fine (I'll fix up the wording issue) however...
>>
>> I'm not clear on the severity of the issue. Is this something
>> we should be pushing for stable?
> 
> I think that should be pushing for stable, since the common isssue for the ADC is initially enabled on loader,
> and only disabled after the first read.
> 
> cat /sys/class/hwmon/hwmon1/device/temp1_input
> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
> 
> The kernel log shows:
> 
> [ 32.209451] read channel() error: -110
> ..
> 
> Also, for my experience. Some other reasons caused the adc (controller) glitch for the kernel side.
Fine.  So now the only question is who is handling it. The
fix is useless (I think) without the dts changes to support it.
Normally we'd route the dts and driver changes separately as it
should not matter, but here I think I'd prefer it if the whole
thing went via rockchip -> arm-soc tree so it goes in together.

Hence (with wording fixed)

Acked-by: Jonathan Cameron <jic23@kernel.org>
Cc: <Stable@vger.kernel.org> 
(for the driver patch).

If people want me to take it via IIO then I'll need acks for
the dts changes with explicit agreement that they can be marked
for stable. Would image Heiko, these would come from you.

Thanks,

Jonathan
> 
> -
> Caesar
> 
>> Jonathan
>>> ---
>>>
>>> Changes in v3:
>>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>>> - add Guente's test tag.
>>>
>>> Changes in v2:
>>> - Make the reset as an optional property, since it should work
>>> with old devicetrees as well.
>>>
>>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>>  drivers/iio/adc/Kconfig                            |  1 +
>>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>>  3 files changed, 38 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> index bf99e2f..205593f 100644
>>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> @@ -16,6 +16,11 @@ Required properties:
>>>  - vref-supply: The regulator supply ADC reference voltage.
>>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>>  
>>> +Optional properties:
>>> +- resets: Must contain an entry for each entry in reset-names if need support
>>> +	  this option. See ../reset/reset.txt for details.
>>> +- reset-names: Must include the name "saradc-apb".
>>> +
>>>  Example:
>>>  	saradc: saradc@2006c000 {
>>>  		compatible = "rockchip,saradc";
>>> @@ -23,6 +28,8 @@ Example:
>>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>>  		clock-names = "saradc", "apb_pclk";
>>> +		resets = <&cru SRST_SARADC>;
>>> +		reset-names = "saradc-apb";
>>>  		#io-channel-cells = <1>;
>>>  		vref-supply = <&vcc18>;
>>>  	};
>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>> index 1de31bd..7675772 100644
>>> --- a/drivers/iio/adc/Kconfig
>>> +++ b/drivers/iio/adc/Kconfig
>>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>>  config ROCKCHIP_SARADC
>>>  	tristate "Rockchip SARADC driver"
>>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>>> +	depends on RESET_CONTROLLER
>>>  	help
>>>  	  Say yes here to build support for the SARADC found in SoCs from
>>>  	  Rockchip.
>>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>>> index f9ad6c2..85d7012 100644
>>> --- a/drivers/iio/adc/rockchip_saradc.c
>>> +++ b/drivers/iio/adc/rockchip_saradc.c
>>> @@ -21,6 +21,8 @@
>>>  #include <linux/of_device.h>
>>>  #include <linux/clk.h>
>>>  #include <linux/completion.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/reset.h>
>>>  #include <linux/regulator/consumer.h>
>>>  #include <linux/iio/iio.h>
>>>  
>>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>>  	struct clk		*clk;
>>>  	struct completion	completion;
>>>  	struct regulator	*vref;
>>> +	struct reset_control	*reset;
>>>  	const struct rockchip_saradc_data *data;
>>>  	u16			last_val;
>>>  };
>>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>>  };
>>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>>  
>>> +/**
>>> + * Reset SARADC Controller.
>>> + */
>>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>>> +{
>>> +	reset_control_assert(reset);
>>> +	usleep_range(10, 20);
>>> +	reset_control_deassert(reset);
>>> +}
>>> +
>>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>>  {
>>>  	struct rockchip_saradc *info = NULL;
>>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>  	if (IS_ERR(info->regs))
>>>  		return PTR_ERR(info->regs);
>>>  
>>> +	/*
>>> +	 * The reset should be an optional property, as it should work
>>> +	 * with old devicetrees as well
>>> +	 */
>>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>>> +	if (IS_ERR(info->reset)) {
>>> +		ret = PTR_ERR(info->reset);
>>> +		if (ret != -ENOENT)
>>> +			return ret;
>>> +
>>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>>> +		info->reset = NULL;
>>> +	}
>>> +
>>>  	init_completion(&info->completion);
>>>  
>>>  	irq = platform_get_irq(pdev, 0);
>>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>  		return PTR_ERR(info->vref);
>>>  	}
>>>  
>>> +	if (info->reset)
>>> +		rockchip_saradc_reset_controller(info->reset);
>>> +
>>>  	/*
>>>  	 * Use a default value for the converter clock.
>>>  	 * This may become user-configurable in the future.
>>>
>>
>> _______________________________________________
>> Linux-rockchip mailing list
>> Linux-rockchip@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 
> 
> -- 
> caesar wang | software engineer | wxt@rock-chip.com 
> 


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 15/08/16 19:10, Caesar Wang wrote:
> 
> On 2016?08?16? 01:41, Jonathan Cameron wrote:
>> On 27/07/16 15:24, Caesar Wang wrote:
>>> SARADC controller needs to be reset before programming it, otherwise
>>> it will not function properly.
>>>
>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>>> Cc: Jonathan Cameron <jic23@kernel.org>
>>> Cc: Heiko Stuebner <heiko@sntech.de>
>>> Cc: Rob Herring <robh+dt@kernel.org>
>>> Cc: linux-iio at vger.kernel.org
>>> Cc: linux-rockchip at lists.infradead.org
>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>>
>> Hi
>>
>> Patch is fine (I'll fix up the wording issue) however...
>>
>> I'm not clear on the severity of the issue. Is this something
>> we should be pushing for stable?
> 
> I think that should be pushing for stable, since the common isssue for the ADC is initially enabled on loader,
> and only disabled after the first read.
> 
> cat /sys/class/hwmon/hwmon1/device/temp1_input
> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
> 
> The kernel log shows:
> 
> [ 32.209451] read channel() error: -110
> ..
> 
> Also, for my experience. Some other reasons caused the adc (controller) glitch for the kernel side.
Fine.  So now the only question is who is handling it. The
fix is useless (I think) without the dts changes to support it.
Normally we'd route the dts and driver changes separately as it
should not matter, but here I think I'd prefer it if the whole
thing went via rockchip -> arm-soc tree so it goes in together.

Hence (with wording fixed)

Acked-by: Jonathan Cameron <jic23@kernel.org>
Cc: <Stable@vger.kernel.org> 
(for the driver patch).

If people want me to take it via IIO then I'll need acks for
the dts changes with explicit agreement that they can be marked
for stable. Would image Heiko, these would come from you.

Thanks,

Jonathan
> 
> -
> Caesar
> 
>> Jonathan
>>> ---
>>>
>>> Changes in v3:
>>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>>> - add Guente's test tag.
>>>
>>> Changes in v2:
>>> - Make the reset as an optional property, since it should work
>>> with old devicetrees as well.
>>>
>>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>>  drivers/iio/adc/Kconfig                            |  1 +
>>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>>  3 files changed, 38 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> index bf99e2f..205593f 100644
>>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>> @@ -16,6 +16,11 @@ Required properties:
>>>  - vref-supply: The regulator supply ADC reference voltage.
>>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>>  
>>> +Optional properties:
>>> +- resets: Must contain an entry for each entry in reset-names if need support
>>> +	  this option. See ../reset/reset.txt for details.
>>> +- reset-names: Must include the name "saradc-apb".
>>> +
>>>  Example:
>>>  	saradc: saradc at 2006c000 {
>>>  		compatible = "rockchip,saradc";
>>> @@ -23,6 +28,8 @@ Example:
>>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>>  		clock-names = "saradc", "apb_pclk";
>>> +		resets = <&cru SRST_SARADC>;
>>> +		reset-names = "saradc-apb";
>>>  		#io-channel-cells = <1>;
>>>  		vref-supply = <&vcc18>;
>>>  	};
>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>> index 1de31bd..7675772 100644
>>> --- a/drivers/iio/adc/Kconfig
>>> +++ b/drivers/iio/adc/Kconfig
>>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>>  config ROCKCHIP_SARADC
>>>  	tristate "Rockchip SARADC driver"
>>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>>> +	depends on RESET_CONTROLLER
>>>  	help
>>>  	  Say yes here to build support for the SARADC found in SoCs from
>>>  	  Rockchip.
>>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>>> index f9ad6c2..85d7012 100644
>>> --- a/drivers/iio/adc/rockchip_saradc.c
>>> +++ b/drivers/iio/adc/rockchip_saradc.c
>>> @@ -21,6 +21,8 @@
>>>  #include <linux/of_device.h>
>>>  #include <linux/clk.h>
>>>  #include <linux/completion.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/reset.h>
>>>  #include <linux/regulator/consumer.h>
>>>  #include <linux/iio/iio.h>
>>>  
>>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>>  	struct clk		*clk;
>>>  	struct completion	completion;
>>>  	struct regulator	*vref;
>>> +	struct reset_control	*reset;
>>>  	const struct rockchip_saradc_data *data;
>>>  	u16			last_val;
>>>  };
>>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>>  };
>>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>>  
>>> +/**
>>> + * Reset SARADC Controller.
>>> + */
>>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>>> +{
>>> +	reset_control_assert(reset);
>>> +	usleep_range(10, 20);
>>> +	reset_control_deassert(reset);
>>> +}
>>> +
>>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>>  {
>>>  	struct rockchip_saradc *info = NULL;
>>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>  	if (IS_ERR(info->regs))
>>>  		return PTR_ERR(info->regs);
>>>  
>>> +	/*
>>> +	 * The reset should be an optional property, as it should work
>>> +	 * with old devicetrees as well
>>> +	 */
>>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>>> +	if (IS_ERR(info->reset)) {
>>> +		ret = PTR_ERR(info->reset);
>>> +		if (ret != -ENOENT)
>>> +			return ret;
>>> +
>>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>>> +		info->reset = NULL;
>>> +	}
>>> +
>>>  	init_completion(&info->completion);
>>>  
>>>  	irq = platform_get_irq(pdev, 0);
>>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>  		return PTR_ERR(info->vref);
>>>  	}
>>>  
>>> +	if (info->reset)
>>> +		rockchip_saradc_reset_controller(info->reset);
>>> +
>>>  	/*
>>>  	 * Use a default value for the converter clock.
>>>  	 * This may become user-configurable in the future.
>>>
>>
>> _______________________________________________
>> Linux-rockchip mailing list
>> Linux-rockchip at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
> 
> 
> -- 
> caesar wang | software engineer | wxt at rock-chip.com 
> 

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

Something in here got it blocked by the lists. I'm guessing it
was the characters my email client didn't like so trying again
with them dropped.

Jonathan
On 21/08/16 20:11, Jonathan Cameron wrote:
> On 15/08/16 19:10, Caesar Wang wrote:
>>
>>> On 27/07/16 15:24, Caesar Wang wrote:
>>>> SARADC controller needs to be reset before programming it, otherwise
>>>> it will not function properly.
>>>>
>>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>>>> Cc: Jonathan Cameron <jic23@kernel.org>
>>>> Cc: Heiko Stuebner <heiko@sntech.de>
>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>> Cc: linux-iio@vger.kernel.org
>>>> Cc: linux-rockchip@lists.infradead.org
>>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>>>
>>> Hi
>>>
>>> Patch is fine (I'll fix up the wording issue) however...
>>>
>>> I'm not clear on the severity of the issue. Is this something
>>> we should be pushing for stable?
>>
>> I think that should be pushing for stable, since the common isssue for the ADC is initially enabled on loader,
>> and only disabled after the first read.
>>
>> cat /sys/class/hwmon/hwmon1/device/temp1_input
>> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
>>
>> The kernel log shows:
>>
>> [ 32.209451] read channel() error: -110
>> ..
>>
>> Also, for my experience. Some other reasons caused the adc (controller) glitch for the kernel side.
> Fine.  So now the only question is who is handling it. The
> fix is useless (I think) without the dts changes to support it.
> Normally we'd route the dts and driver changes separately as it
> should not matter, but here I think I'd prefer it if the whole
> thing went via rockchip -> arm-soc tree so it goes in together.
> 
> Hence (with wording fixed)
> 
> Acked-by: Jonathan Cameron <jic23@kernel.org>
> Cc: <Stable@vger.kernel.org> 
> (for the driver patch).
> 
> If people want me to take it via IIO then I'll need acks for
> the dts changes with explicit agreement that they can be marked
> for stable. Would image Heiko, these would come from you.
> 
> Thanks,
> 
> Jonathan
>>
>> -
>> Caesar
>>
>>> Jonathan
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>>>> - add Guente's test tag.
>>>>
>>>> Changes in v2:
>>>> - Make the reset as an optional property, since it should work
>>>> with old devicetrees as well.
>>>>
>>>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>>>  drivers/iio/adc/Kconfig                            |  1 +
>>>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>>>  3 files changed, 38 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> index bf99e2f..205593f 100644
>>>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> @@ -16,6 +16,11 @@ Required properties:
>>>>  - vref-supply: The regulator supply ADC reference voltage.
>>>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>>>  
>>>> +Optional properties:
>>>> +- resets: Must contain an entry for each entry in reset-names if need support
>>>> +	  this option. See ../reset/reset.txt for details.
>>>> +- reset-names: Must include the name "saradc-apb".
>>>> +
>>>>  Example:
>>>>  	saradc: saradc@2006c000 {
>>>>  		compatible = "rockchip,saradc";
>>>> @@ -23,6 +28,8 @@ Example:
>>>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>>>  		clock-names = "saradc", "apb_pclk";
>>>> +		resets = <&cru SRST_SARADC>;
>>>> +		reset-names = "saradc-apb";
>>>>  		#io-channel-cells = <1>;
>>>>  		vref-supply = <&vcc18>;
>>>>  	};
>>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>>> index 1de31bd..7675772 100644
>>>> --- a/drivers/iio/adc/Kconfig
>>>> +++ b/drivers/iio/adc/Kconfig
>>>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>>>  config ROCKCHIP_SARADC
>>>>  	tristate "Rockchip SARADC driver"
>>>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>>>> +	depends on RESET_CONTROLLER
>>>>  	help
>>>>  	  Say yes here to build support for the SARADC found in SoCs from
>>>>  	  Rockchip.
>>>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>>>> index f9ad6c2..85d7012 100644
>>>> --- a/drivers/iio/adc/rockchip_saradc.c
>>>> +++ b/drivers/iio/adc/rockchip_saradc.c
>>>> @@ -21,6 +21,8 @@
>>>>  #include <linux/of_device.h>
>>>>  #include <linux/clk.h>
>>>>  #include <linux/completion.h>
>>>> +#include <linux/delay.h>
>>>> +#include <linux/reset.h>
>>>>  #include <linux/regulator/consumer.h>
>>>>  #include <linux/iio/iio.h>
>>>>  
>>>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>>>  	struct clk		*clk;
>>>>  	struct completion	completion;
>>>>  	struct regulator	*vref;
>>>> +	struct reset_control	*reset;
>>>>  	const struct rockchip_saradc_data *data;
>>>>  	u16			last_val;
>>>>  };
>>>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>>>  };
>>>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>>>  
>>>> +/**
>>>> + * Reset SARADC Controller.
>>>> + */
>>>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>>>> +{
>>>> +	reset_control_assert(reset);
>>>> +	usleep_range(10, 20);
>>>> +	reset_control_deassert(reset);
>>>> +}
>>>> +
>>>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  {
>>>>  	struct rockchip_saradc *info = NULL;
>>>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  	if (IS_ERR(info->regs))
>>>>  		return PTR_ERR(info->regs);
>>>>  
>>>> +	/*
>>>> +	 * The reset should be an optional property, as it should work
>>>> +	 * with old devicetrees as well
>>>> +	 */
>>>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>>>> +	if (IS_ERR(info->reset)) {
>>>> +		ret = PTR_ERR(info->reset);
>>>> +		if (ret != -ENOENT)
>>>> +			return ret;
>>>> +
>>>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>>>> +		info->reset = NULL;
>>>> +	}
>>>> +
>>>>  	init_completion(&info->completion);
>>>>  
>>>>  	irq = platform_get_irq(pdev, 0);
>>>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  		return PTR_ERR(info->vref);
>>>>  	}
>>>>  
>>>> +	if (info->reset)
>>>> +		rockchip_saradc_reset_controller(info->reset);
>>>> +
>>>>  	/*
>>>>  	 * Use a default value for the converter clock.
>>>>  	 * This may become user-configurable in the future.
>>>>
>>>
>>> _______________________________________________
>>> Linux-rockchip mailing list
>>> Linux-rockchip@lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>
>>
>> -- 
>> caesar wang | software engineer | wxt@rock-chip.com 
>>
> 

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

Something in here got it blocked by the lists. I'm guessing it
was the characters my email client didn't like so trying again
with them dropped.

Jonathan
On 21/08/16 20:11, Jonathan Cameron wrote:
> On 15/08/16 19:10, Caesar Wang wrote:
>>
>>> On 27/07/16 15:24, Caesar Wang wrote:
>>>> SARADC controller needs to be reset before programming it, otherwise
>>>> it will not function properly.
>>>>
>>>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>>>> Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>>> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
>>>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>>> Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>>> Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>>>> Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
>>>>
>>> Hi
>>>
>>> Patch is fine (I'll fix up the wording issue) however...
>>>
>>> I'm not clear on the severity of the issue. Is this something
>>> we should be pushing for stable?
>>
>> I think that should be pushing for stable, since the common isssue for the ADC is initially enabled on loader,
>> and only disabled after the first read.
>>
>> cat /sys/class/hwmon/hwmon1/device/temp1_input
>> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
>>
>> The kernel log shows:
>>
>> [ 32.209451] read channel() error: -110
>> ..
>>
>> Also, for my experience. Some other reasons caused the adc (controller) glitch for the kernel side.
> Fine.  So now the only question is who is handling it. The
> fix is useless (I think) without the dts changes to support it.
> Normally we'd route the dts and driver changes separately as it
> should not matter, but here I think I'd prefer it if the whole
> thing went via rockchip -> arm-soc tree so it goes in together.
> 
> Hence (with wording fixed)
> 
> Acked-by: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: <Stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> 
> (for the driver patch).
> 
> If people want me to take it via IIO then I'll need acks for
> the dts changes with explicit agreement that they can be marked
> for stable. Would image Heiko, these would come from you.
> 
> Thanks,
> 
> Jonathan
>>
>> -
>> Caesar
>>
>>> Jonathan
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>>>> - add Guente's test tag.
>>>>
>>>> Changes in v2:
>>>> - Make the reset as an optional property, since it should work
>>>> with old devicetrees as well.
>>>>
>>>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>>>  drivers/iio/adc/Kconfig                            |  1 +
>>>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>>>  3 files changed, 38 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> index bf99e2f..205593f 100644
>>>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> @@ -16,6 +16,11 @@ Required properties:
>>>>  - vref-supply: The regulator supply ADC reference voltage.
>>>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>>>  
>>>> +Optional properties:
>>>> +- resets: Must contain an entry for each entry in reset-names if need support
>>>> +	  this option. See ../reset/reset.txt for details.
>>>> +- reset-names: Must include the name "saradc-apb".
>>>> +
>>>>  Example:
>>>>  	saradc: saradc@2006c000 {
>>>>  		compatible = "rockchip,saradc";
>>>> @@ -23,6 +28,8 @@ Example:
>>>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>>>  		clock-names = "saradc", "apb_pclk";
>>>> +		resets = <&cru SRST_SARADC>;
>>>> +		reset-names = "saradc-apb";
>>>>  		#io-channel-cells = <1>;
>>>>  		vref-supply = <&vcc18>;
>>>>  	};
>>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>>> index 1de31bd..7675772 100644
>>>> --- a/drivers/iio/adc/Kconfig
>>>> +++ b/drivers/iio/adc/Kconfig
>>>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>>>  config ROCKCHIP_SARADC
>>>>  	tristate "Rockchip SARADC driver"
>>>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>>>> +	depends on RESET_CONTROLLER
>>>>  	help
>>>>  	  Say yes here to build support for the SARADC found in SoCs from
>>>>  	  Rockchip.
>>>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>>>> index f9ad6c2..85d7012 100644
>>>> --- a/drivers/iio/adc/rockchip_saradc.c
>>>> +++ b/drivers/iio/adc/rockchip_saradc.c
>>>> @@ -21,6 +21,8 @@
>>>>  #include <linux/of_device.h>
>>>>  #include <linux/clk.h>
>>>>  #include <linux/completion.h>
>>>> +#include <linux/delay.h>
>>>> +#include <linux/reset.h>
>>>>  #include <linux/regulator/consumer.h>
>>>>  #include <linux/iio/iio.h>
>>>>  
>>>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>>>  	struct clk		*clk;
>>>>  	struct completion	completion;
>>>>  	struct regulator	*vref;
>>>> +	struct reset_control	*reset;
>>>>  	const struct rockchip_saradc_data *data;
>>>>  	u16			last_val;
>>>>  };
>>>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>>>  };
>>>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>>>  
>>>> +/**
>>>> + * Reset SARADC Controller.
>>>> + */
>>>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>>>> +{
>>>> +	reset_control_assert(reset);
>>>> +	usleep_range(10, 20);
>>>> +	reset_control_deassert(reset);
>>>> +}
>>>> +
>>>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  {
>>>>  	struct rockchip_saradc *info = NULL;
>>>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  	if (IS_ERR(info->regs))
>>>>  		return PTR_ERR(info->regs);
>>>>  
>>>> +	/*
>>>> +	 * The reset should be an optional property, as it should work
>>>> +	 * with old devicetrees as well
>>>> +	 */
>>>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>>>> +	if (IS_ERR(info->reset)) {
>>>> +		ret = PTR_ERR(info->reset);
>>>> +		if (ret != -ENOENT)
>>>> +			return ret;
>>>> +
>>>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>>>> +		info->reset = NULL;
>>>> +	}
>>>> +
>>>>  	init_completion(&info->completion);
>>>>  
>>>>  	irq = platform_get_irq(pdev, 0);
>>>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  		return PTR_ERR(info->vref);
>>>>  	}
>>>>  
>>>> +	if (info->reset)
>>>> +		rockchip_saradc_reset_controller(info->reset);
>>>> +
>>>>  	/*
>>>>  	 * Use a default value for the converter clock.
>>>>  	 * This may become user-configurable in the future.
>>>>
>>>
>>> _______________________________________________
>>> Linux-rockchip mailing list
>>> Linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>
>>
>> -- 
>> caesar wang | software engineer | wxt-TNX95d0MmH73oGB3hsPCZA@public.gmane.org 
>>
> 

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

Something in here got it blocked by the lists. I'm guessing it
was the characters my email client didn't like so trying again
with them dropped.

Jonathan
On 21/08/16 20:11, Jonathan Cameron wrote:
> On 15/08/16 19:10, Caesar Wang wrote:
>>
>>> On 27/07/16 15:24, Caesar Wang wrote:
>>>> SARADC controller needs to be reset before programming it, otherwise
>>>> it will not function properly.
>>>>
>>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>>>> Cc: Jonathan Cameron <jic23@kernel.org>
>>>> Cc: Heiko Stuebner <heiko@sntech.de>
>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>> Cc: linux-iio at vger.kernel.org
>>>> Cc: linux-rockchip at lists.infradead.org
>>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>>>
>>> Hi
>>>
>>> Patch is fine (I'll fix up the wording issue) however...
>>>
>>> I'm not clear on the severity of the issue. Is this something
>>> we should be pushing for stable?
>>
>> I think that should be pushing for stable, since the common isssue for the ADC is initially enabled on loader,
>> and only disabled after the first read.
>>
>> cat /sys/class/hwmon/hwmon1/device/temp1_input
>> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
>>
>> The kernel log shows:
>>
>> [ 32.209451] read channel() error: -110
>> ..
>>
>> Also, for my experience. Some other reasons caused the adc (controller) glitch for the kernel side.
> Fine.  So now the only question is who is handling it. The
> fix is useless (I think) without the dts changes to support it.
> Normally we'd route the dts and driver changes separately as it
> should not matter, but here I think I'd prefer it if the whole
> thing went via rockchip -> arm-soc tree so it goes in together.
> 
> Hence (with wording fixed)
> 
> Acked-by: Jonathan Cameron <jic23@kernel.org>
> Cc: <Stable@vger.kernel.org> 
> (for the driver patch).
> 
> If people want me to take it via IIO then I'll need acks for
> the dts changes with explicit agreement that they can be marked
> for stable. Would image Heiko, these would come from you.
> 
> Thanks,
> 
> Jonathan
>>
>> -
>> Caesar
>>
>>> Jonathan
>>>> ---
>>>>
>>>> Changes in v3:
>>>> - %s/devm_reset_control_get_optional()/devm_reset_control_get()
>>>> - add Guente's test tag.
>>>>
>>>> Changes in v2:
>>>> - Make the reset as an optional property, since it should work
>>>> with old devicetrees as well.
>>>>
>>>>  .../bindings/iio/adc/rockchip-saradc.txt           |  7 +++++
>>>>  drivers/iio/adc/Kconfig                            |  1 +
>>>>  drivers/iio/adc/rockchip_saradc.c                  | 30 ++++++++++++++++++++++
>>>>  3 files changed, 38 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> index bf99e2f..205593f 100644
>>>> --- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> +++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.txt
>>>> @@ -16,6 +16,11 @@ Required properties:
>>>>  - vref-supply: The regulator supply ADC reference voltage.
>>>>  - #io-channel-cells: Should be 1, see ../iio-bindings.txt
>>>>  
>>>> +Optional properties:
>>>> +- resets: Must contain an entry for each entry in reset-names if need support
>>>> +	  this option. See ../reset/reset.txt for details.
>>>> +- reset-names: Must include the name "saradc-apb".
>>>> +
>>>>  Example:
>>>>  	saradc: saradc at 2006c000 {
>>>>  		compatible = "rockchip,saradc";
>>>> @@ -23,6 +28,8 @@ Example:
>>>>  		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>>>>  		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
>>>>  		clock-names = "saradc", "apb_pclk";
>>>> +		resets = <&cru SRST_SARADC>;
>>>> +		reset-names = "saradc-apb";
>>>>  		#io-channel-cells = <1>;
>>>>  		vref-supply = <&vcc18>;
>>>>  	};
>>>> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>>>> index 1de31bd..7675772 100644
>>>> --- a/drivers/iio/adc/Kconfig
>>>> +++ b/drivers/iio/adc/Kconfig
>>>> @@ -389,6 +389,7 @@ config QCOM_SPMI_VADC
>>>>  config ROCKCHIP_SARADC
>>>>  	tristate "Rockchip SARADC driver"
>>>>  	depends on ARCH_ROCKCHIP || (ARM && COMPILE_TEST)
>>>> +	depends on RESET_CONTROLLER
>>>>  	help
>>>>  	  Say yes here to build support for the SARADC found in SoCs from
>>>>  	  Rockchip.
>>>> diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
>>>> index f9ad6c2..85d7012 100644
>>>> --- a/drivers/iio/adc/rockchip_saradc.c
>>>> +++ b/drivers/iio/adc/rockchip_saradc.c
>>>> @@ -21,6 +21,8 @@
>>>>  #include <linux/of_device.h>
>>>>  #include <linux/clk.h>
>>>>  #include <linux/completion.h>
>>>> +#include <linux/delay.h>
>>>> +#include <linux/reset.h>
>>>>  #include <linux/regulator/consumer.h>
>>>>  #include <linux/iio/iio.h>
>>>>  
>>>> @@ -53,6 +55,7 @@ struct rockchip_saradc {
>>>>  	struct clk		*clk;
>>>>  	struct completion	completion;
>>>>  	struct regulator	*vref;
>>>> +	struct reset_control	*reset;
>>>>  	const struct rockchip_saradc_data *data;
>>>>  	u16			last_val;
>>>>  };
>>>> @@ -190,6 +193,16 @@ static const struct of_device_id rockchip_saradc_match[] = {
>>>>  };
>>>>  MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
>>>>  
>>>> +/**
>>>> + * Reset SARADC Controller.
>>>> + */
>>>> +static void rockchip_saradc_reset_controller(struct reset_control *reset)
>>>> +{
>>>> +	reset_control_assert(reset);
>>>> +	usleep_range(10, 20);
>>>> +	reset_control_deassert(reset);
>>>> +}
>>>> +
>>>>  static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  {
>>>>  	struct rockchip_saradc *info = NULL;
>>>> @@ -218,6 +231,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  	if (IS_ERR(info->regs))
>>>>  		return PTR_ERR(info->regs);
>>>>  
>>>> +	/*
>>>> +	 * The reset should be an optional property, as it should work
>>>> +	 * with old devicetrees as well
>>>> +	 */
>>>> +	info->reset = devm_reset_control_get(&pdev->dev, "saradc-apb");
>>>> +	if (IS_ERR(info->reset)) {
>>>> +		ret = PTR_ERR(info->reset);
>>>> +		if (ret != -ENOENT)
>>>> +			return ret;
>>>> +
>>>> +		dev_dbg(&pdev->dev, "no reset control found\n");
>>>> +		info->reset = NULL;
>>>> +	}
>>>> +
>>>>  	init_completion(&info->completion);
>>>>  
>>>>  	irq = platform_get_irq(pdev, 0);
>>>> @@ -252,6 +279,9 @@ static int rockchip_saradc_probe(struct platform_device *pdev)
>>>>  		return PTR_ERR(info->vref);
>>>>  	}
>>>>  
>>>> +	if (info->reset)
>>>> +		rockchip_saradc_reset_controller(info->reset);
>>>> +
>>>>  	/*
>>>>  	 * Use a default value for the converter clock.
>>>>  	 * This may become user-configurable in the future.
>>>>
>>>
>>> _______________________________________________
>>> Linux-rockchip mailing list
>>> Linux-rockchip at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-rockchip
>>
>>
>> -- 
>> caesar wang | software engineer | wxt at rock-chip.com 
>>
> 

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Heiko Stuebner]

Am Sonntag, 21. August 2016, 21:01:19 CEST schrieb Jonathan Cameron:
> Something in here got it blocked by the lists. I'm guessing it
> was the characters my email client didn't like so trying again
> with them dropped.
> 
> Jonathan
> 
> On 21/08/16 20:11, Jonathan Cameron wrote:
> > On 15/08/16 19:10, Caesar Wang wrote:
> >>> On 27/07/16 15:24, Caesar Wang wrote:
> >>>> SARADC controller needs to be reset before programming it, otherwise
> >>>> it will not function properly.
> >>>> 
> >>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> >>>> Cc: Jonathan Cameron <jic23@kernel.org>
> >>>> Cc: Heiko Stuebner <heiko@sntech.de>
> >>>> Cc: Rob Herring <robh+dt@kernel.org>
> >>>> Cc: linux-iio@vger.kernel.org
> >>>> Cc: linux-rockchip@lists.infradead.org
> >>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
> >>> 
> >>> Hi
> >>> 
> >>> Patch is fine (I'll fix up the wording issue) however...
> >>> 
> >>> I'm not clear on the severity of the issue. Is this something
> >>> we should be pushing for stable?
> >> 
> >> I think that should be pushing for stable, since the common isssue for
> >> the ADC is initially enabled on loader, and only disabled after the
> >> first read.
> >> 
> >> cat /sys/class/hwmon/hwmon1/device/temp1_input
> >> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
> >> 
> >> The kernel log shows:
> >> 
> >> [ 32.209451] read channel() error: -110
> >> ..
> >> 
> >> Also, for my experience. Some other reasons caused the adc (controller)
> >> glitch for the kernel side.> 
> > Fine.  So now the only question is who is handling it. The
> > fix is useless (I think) without the dts changes to support it.
> > Normally we'd route the dts and driver changes separately as it
> > should not matter, but here I think I'd prefer it if the whole
> > thing went via rockchip -> arm-soc tree so it goes in together.
> > 
> > Hence (with wording fixed)
> > 
> > Acked-by: Jonathan Cameron <jic23@kernel.org>
> > Cc: <Stable@vger.kernel.org>
> > (for the driver patch).
> > 
> > If people want me to take it via IIO then I'll need acks for
> > the dts changes with explicit agreement that they can be marked
> > for stable. Would image Heiko, these would come from you.

I don't know how the armsoc people feel about routing other subsystem changes 
through armsoc, but I think small dts changes coming through driver trees is 
the more common case, so personally I'd think patches 1,3 and 4 could go 
through the iio tree.

Patch 2 of course isn't material for stable, as it adds new functionality, so 
I'd pick that up directly, especially as we see numerous rk3399 changes, so 
that would be prone to conflict.


Heiko

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Heiko Stuebner]

Am Sonntag, 21. August 2016, 21:01:19 CEST schrieb Jonathan Cameron:
> Something in here got it blocked by the lists. I'm guessing it
> was the characters my email client didn't like so trying again
> with them dropped.
> 
> Jonathan
> 
> On 21/08/16 20:11, Jonathan Cameron wrote:
> > On 15/08/16 19:10, Caesar Wang wrote:
> >>> On 27/07/16 15:24, Caesar Wang wrote:
> >>>> SARADC controller needs to be reset before programming it, otherwise
> >>>> it will not function properly.
> >>>> 
> >>>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> >>>> Cc: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >>>> Cc: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> >>>> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> >>>> Cc: linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >>>> Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> >>>> Tested-by: Guenter Roeck <linux-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
> >>> 
> >>> Hi
> >>> 
> >>> Patch is fine (I'll fix up the wording issue) however...
> >>> 
> >>> I'm not clear on the severity of the issue. Is this something
> >>> we should be pushing for stable?
> >> 
> >> I think that should be pushing for stable, since the common isssue for
> >> the ADC is initially enabled on loader, and only disabled after the
> >> first read.
> >> 
> >> cat /sys/class/hwmon/hwmon1/device/temp1_input
> >> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
> >> 
> >> The kernel log shows:
> >> 
> >> [ 32.209451] read channel() error: -110
> >> ..
> >> 
> >> Also, for my experience. Some other reasons caused the adc (controller)
> >> glitch for the kernel side.> 
> > Fine.  So now the only question is who is handling it. The
> > fix is useless (I think) without the dts changes to support it.
> > Normally we'd route the dts and driver changes separately as it
> > should not matter, but here I think I'd prefer it if the whole
> > thing went via rockchip -> arm-soc tree so it goes in together.
> > 
> > Hence (with wording fixed)
> > 
> > Acked-by: Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > Cc: <Stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> > (for the driver patch).
> > 
> > If people want me to take it via IIO then I'll need acks for
> > the dts changes with explicit agreement that they can be marked
> > for stable. Would image Heiko, these would come from you.

I don't know how the armsoc people feel about routing other subsystem changes 
through armsoc, but I think small dts changes coming through driver trees is 
the more common case, so personally I'd think patches 1,3 and 4 could go 
through the iio tree.

Patch 2 of course isn't material for stable, as it adds new functionality, so 
I'd pick that up directly, especially as we see numerous rk3399 changes, so 
that would be prone to conflict.


Heiko

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Heiko Stuebner]

Am Sonntag, 21. August 2016, 21:01:19 CEST schrieb Jonathan Cameron:
> Something in here got it blocked by the lists. I'm guessing it
> was the characters my email client didn't like so trying again
> with them dropped.
> 
> Jonathan
> 
> On 21/08/16 20:11, Jonathan Cameron wrote:
> > On 15/08/16 19:10, Caesar Wang wrote:
> >>> On 27/07/16 15:24, Caesar Wang wrote:
> >>>> SARADC controller needs to be reset before programming it, otherwise
> >>>> it will not function properly.
> >>>> 
> >>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> >>>> Cc: Jonathan Cameron <jic23@kernel.org>
> >>>> Cc: Heiko Stuebner <heiko@sntech.de>
> >>>> Cc: Rob Herring <robh+dt@kernel.org>
> >>>> Cc: linux-iio at vger.kernel.org
> >>>> Cc: linux-rockchip at lists.infradead.org
> >>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
> >>> 
> >>> Hi
> >>> 
> >>> Patch is fine (I'll fix up the wording issue) however...
> >>> 
> >>> I'm not clear on the severity of the issue. Is this something
> >>> we should be pushing for stable?
> >> 
> >> I think that should be pushing for stable, since the common isssue for
> >> the ADC is initially enabled on loader, and only disabled after the
> >> first read.
> >> 
> >> cat /sys/class/hwmon/hwmon1/device/temp1_input
> >> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
> >> 
> >> The kernel log shows:
> >> 
> >> [ 32.209451] read channel() error: -110
> >> ..
> >> 
> >> Also, for my experience. Some other reasons caused the adc (controller)
> >> glitch for the kernel side.> 
> > Fine.  So now the only question is who is handling it. The
> > fix is useless (I think) without the dts changes to support it.
> > Normally we'd route the dts and driver changes separately as it
> > should not matter, but here I think I'd prefer it if the whole
> > thing went via rockchip -> arm-soc tree so it goes in together.
> > 
> > Hence (with wording fixed)
> > 
> > Acked-by: Jonathan Cameron <jic23@kernel.org>
> > Cc: <Stable@vger.kernel.org>
> > (for the driver patch).
> > 
> > If people want me to take it via IIO then I'll need acks for
> > the dts changes with explicit agreement that they can be marked
> > for stable. Would image Heiko, these would come from you.

I don't know how the armsoc people feel about routing other subsystem changes 
through armsoc, but I think small dts changes coming through driver trees is 
the more common case, so personally I'd think patches 1,3 and 4 could go 
through the iio tree.

Patch 2 of course isn't material for stable, as it adds new functionality, so 
I'd pick that up directly, especially as we see numerous rk3399 changes, so 
that would be prone to conflict.


Heiko

Re: [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Heiko Stuebner]

Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>

Re: [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Heiko Stuebner]

Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Cc: <Stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>

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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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[PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Heiko Stuebner]

Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>

Re: [PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Heiko Stuebner]

Am Mittwoch, 27. Juli 2016, 22:24:07 CEST schrieb Caesar Wang:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>

Re: [PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Heiko Stuebner]

Am Mittwoch, 27. Juli 2016, 22:24:07 CEST schrieb Caesar Wang:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>

Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Cc: <Stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>

[PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Heiko Stuebner]

Am Mittwoch, 27. Juli 2016, 22:24:07 CEST schrieb Caesar Wang:
> SARADC controller needs to be reset before programming it, otherwise
> it will not function properly.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>

Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>

Re: [PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 22/08/16 18:19, Heiko Stuebner wrote:
> Am Sonntag, 21. August 2016, 21:01:19 CEST schrieb Jonathan Cameron:
>> Something in here got it blocked by the lists. I'm guessing it
>> was the characters my email client didn't like so trying again
>> with them dropped.
>>
>> Jonathan
>>
>> On 21/08/16 20:11, Jonathan Cameron wrote:
>>> On 15/08/16 19:10, Caesar Wang wrote:
>>>>> On 27/07/16 15:24, Caesar Wang wrote:
>>>>>> SARADC controller needs to be reset before programming it, otherwise
>>>>>> it will not function properly.
>>>>>>
>>>>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>>>>>> Cc: Jonathan Cameron <jic23@kernel.org>
>>>>>> Cc: Heiko Stuebner <heiko@sntech.de>
>>>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>>>> Cc: linux-iio@vger.kernel.org
>>>>>> Cc: linux-rockchip@lists.infradead.org
>>>>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>>>>
>>>>> Hi
>>>>>
>>>>> Patch is fine (I'll fix up the wording issue) however...
>>>>>
>>>>> I'm not clear on the severity of the issue. Is this something
>>>>> we should be pushing for stable?
>>>>
>>>> I think that should be pushing for stable, since the common isssue for
>>>> the ADC is initially enabled on loader, and only disabled after the
>>>> first read.
>>>>
>>>> cat /sys/class/hwmon/hwmon1/device/temp1_input
>>>> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
>>>>
>>>> The kernel log shows:
>>>>
>>>> [ 32.209451] read channel() error: -110
>>>> ..
>>>>
>>>> Also, for my experience. Some other reasons caused the adc (controller)
>>>> glitch for the kernel side.> 
>>> Fine.  So now the only question is who is handling it. The
>>> fix is useless (I think) without the dts changes to support it.
>>> Normally we'd route the dts and driver changes separately as it
>>> should not matter, but here I think I'd prefer it if the whole
>>> thing went via rockchip -> arm-soc tree so it goes in together.
>>>
>>> Hence (with wording fixed)
>>>
>>> Acked-by: Jonathan Cameron <jic23@kernel.org>
>>> Cc: <Stable@vger.kernel.org>
>>> (for the driver patch).
>>>
>>> If people want me to take it via IIO then I'll need acks for
>>> the dts changes with explicit agreement that they can be marked
>>> for stable. Would image Heiko, these would come from you.
> 
> I don't know how the armsoc people feel about routing other subsystem changes 
> through armsoc, but I think small dts changes coming through driver trees is 
> the more common case, so personally I'd think patches 1,3 and 4 could go 
> through the iio tree.
> 
> Patch 2 of course isn't material for stable, as it adds new functionality, so 
> I'd pick that up directly, especially as we see numerous rk3399 changes, so 
> that would be prone to conflict.
Absolutely.  This one applied to the fixes-togreg branch of iio.git

Thanks,

Jonathan
> 
> 
> Heiko
> 

[PATCH v3 1/4] iio: adc: rockchip_saradc: reset saradc controller before programming it

[Jonathan Cameron]

On 22/08/16 18:19, Heiko Stuebner wrote:
> Am Sonntag, 21. August 2016, 21:01:19 CEST schrieb Jonathan Cameron:
>> Something in here got it blocked by the lists. I'm guessing it
>> was the characters my email client didn't like so trying again
>> with them dropped.
>>
>> Jonathan
>>
>> On 21/08/16 20:11, Jonathan Cameron wrote:
>>> On 15/08/16 19:10, Caesar Wang wrote:
>>>>> On 27/07/16 15:24, Caesar Wang wrote:
>>>>>> SARADC controller needs to be reset before programming it, otherwise
>>>>>> it will not function properly.
>>>>>>
>>>>>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>>>>>> Cc: Jonathan Cameron <jic23@kernel.org>
>>>>>> Cc: Heiko Stuebner <heiko@sntech.de>
>>>>>> Cc: Rob Herring <robh+dt@kernel.org>
>>>>>> Cc: linux-iio at vger.kernel.org
>>>>>> Cc: linux-rockchip at lists.infradead.org
>>>>>> Tested-by: Guenter Roeck <linux@roeck-us.net>
>>>>>
>>>>> Hi
>>>>>
>>>>> Patch is fine (I'll fix up the wording issue) however...
>>>>>
>>>>> I'm not clear on the severity of the issue. Is this something
>>>>> we should be pushing for stable?
>>>>
>>>> I think that should be pushing for stable, since the common isssue for
>>>> the ADC is initially enabled on loader, and only disabled after the
>>>> first read.
>>>>
>>>> cat /sys/class/hwmon/hwmon1/device/temp1_input
>>>> cat: /sys/class/hwmon/hwmon1/device/temp1_input: Connection timed out
>>>>
>>>> The kernel log shows:
>>>>
>>>> [ 32.209451] read channel() error: -110
>>>> ..
>>>>
>>>> Also, for my experience. Some other reasons caused the adc (controller)
>>>> glitch for the kernel side.> 
>>> Fine.  So now the only question is who is handling it. The
>>> fix is useless (I think) without the dts changes to support it.
>>> Normally we'd route the dts and driver changes separately as it
>>> should not matter, but here I think I'd prefer it if the whole
>>> thing went via rockchip -> arm-soc tree so it goes in together.
>>>
>>> Hence (with wording fixed)
>>>
>>> Acked-by: Jonathan Cameron <jic23@kernel.org>
>>> Cc: <Stable@vger.kernel.org>
>>> (for the driver patch).
>>>
>>> If people want me to take it via IIO then I'll need acks for
>>> the dts changes with explicit agreement that they can be marked
>>> for stable. Would image Heiko, these would come from you.
> 
> I don't know how the armsoc people feel about routing other subsystem changes 
> through armsoc, but I think small dts changes coming through driver trees is 
> the more common case, so personally I'd think patches 1,3 and 4 could go 
> through the iio tree.
> 
> Patch 2 of course isn't material for stable, as it adds new functionality, so 
> I'd pick that up directly, especially as we see numerous rk3399 changes, so 
> that would be prone to conflict.
Absolutely.  This one applied to the fixes-togreg branch of iio.git

Thanks,

Jonathan
> 
> 
> Heiko
> 

Re: [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Jonathan Cameron]

On 22/08/16 18:19, Heiko Stuebner wrote:
> Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> 
> Acked-by: Heiko Stuebner <heiko@sntech.de>
> Cc: <Stable@vger.kernel.org>
Thanks,

Applied to the fixes-togreg branch of iio.git.

Jonathan
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Jonathan Cameron]

On 22/08/16 18:19, Heiko Stuebner wrote:
> Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> 
> Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> Cc: <Stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
Thanks,

Applied to the fixes-togreg branch of iio.git.

Jonathan
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

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[PATCH v3 3/4] arm64: dts: rockchip: add reset saradc node for rk3368 SoCs

[Jonathan Cameron]

On 22/08/16 18:19, Heiko Stuebner wrote:
> Am Mittwoch, 27. Juli 2016, 22:24:06 CEST schrieb Caesar Wang:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> 
> Acked-by: Heiko Stuebner <heiko@sntech.de>
> Cc: <Stable@vger.kernel.org>
Thanks,

Applied to the fixes-togreg branch of iio.git.

Jonathan
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Jonathan Cameron]

On 22/08/16 18:20, Heiko Stuebner wrote:
> Am Mittwoch, 27. Juli 2016, 22:24:07 CEST schrieb Caesar Wang:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> 
> Acked-by: Heiko Stuebner <heiko@sntech.de>
> Cc: <Stable@vger.kernel.org>
> 
Applied to the fixes-togreg branch of iio.git

I'll probably get the pull request done tonight to get this on it's
way.

Jonathan

Re: [PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Jonathan Cameron]

On 22/08/16 18:20, Heiko Stuebner wrote:
> Am Mittwoch, 27. Juli 2016, 22:24:07 CEST schrieb Caesar Wang:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> 
> Acked-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> Cc: <Stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> 
Applied to the fixes-togreg branch of iio.git

I'll probably get the pull request done tonight to get this on it's
way.

Jonathan

[PATCH v3 4/4] arm: dts: rockchip: add reset node for the exist saradc SoCs

[Jonathan Cameron]

On 22/08/16 18:20, Heiko Stuebner wrote:
> Am Mittwoch, 27. Juli 2016, 22:24:07 CEST schrieb Caesar Wang:
>> SARADC controller needs to be reset before programming it, otherwise
>> it will not function properly.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> 
> Acked-by: Heiko Stuebner <heiko@sntech.de>
> Cc: <Stable@vger.kernel.org>
> 
Applied to the fixes-togreg branch of iio.git

I'll probably get the pull request done tonight to get this on it's
way.

Jonathan

Re: [PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399

[Heiko Stübner]

Am Mittwoch, 27. Juli 2016, 22:24:05 schrieb Caesar Wang:
> This patch adds saradc needed information on rk3399 SoCs.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>

applied to my dts64 branch for 4.9

Thanks
Heiko

[PATCH v3 2/4] arm64: dts: rockchip: add the saradc for rk3399

[Heiko Stübner]

Am Mittwoch, 27. Juli 2016, 22:24:05 schrieb Caesar Wang:
> This patch adds saradc needed information on rk3399 SoCs.
> 
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>

applied to my dts64 branch for 4.9

Thanks
Heiko