From: Bryan O'Donoghue <pure.logic@nexus-software.ie>
To: Leonard Crestez <leonard.crestez@nxp.com>, Peng Fan <peng.fan@nxp.com>
Cc: Aisheng Dong <aisheng.dong@nxp.com>,
Abel Vesa <abel.vesa@nxp.com>, Anson Huang <anson.huang@nxp.com>,
"srinivas.kandagatla@linaro.org" <srinivas.kandagatla@linaro.org>,
dl-linux-imx <linux-imx@nxp.com>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
Fabio Estevam <fabio.estevam@nxp.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"l.stach@pengutronix.de" <l.stach@pengutronix.de>
Subject: Re: [PATCH 3/6] nvmem: imx-ocotp: Add i.MX8MM support
Date: Fri, 19 Apr 2019 12:48:55 +0100 [thread overview]
Message-ID: <b2c9b225-d998-8db9-222b-03e2d23ce9cc@nexus-software.ie> (raw)
In-Reply-To: <VI1PR04MB5533CEAA4A84DC46985C231EEE270@VI1PR04MB5533.eurprd04.prod.outlook.com>
On 19/04/2019 11:32, Leonard Crestez wrote:
> On 19.04.2019 13:03, Bryan O'Donoghue wrote:
>> This patch adds support to burn the fuses on the i.MX8MM.
>>
>> +#if defined(CONFIG_ARCH_MXC)
>> +#define IMX_OCOTP_BM_CTRL_ADDR 0x000000FF
>> +#else
>> #define IMX_OCOTP_BM_CTRL_ADDR 0x0000007F
>> +#endif /* ARCH_MXC */
>
> You're on an older tree; in upstream ARCH_MXC is defined on all imx6/7/8
> so can't be used to distinguish. Maybe move to ocotp_params instead?
> The number of valid ADDR bits in OCOTP_CTRL also seems to vary between
> some imx6 variants.
>
> As far as I can tell high ADDR bits are RSVD0 based on total number of
> fuses in the chip. Reading that zero from hardware and writing it back
> should be harmless.
>
> Maybe enlarge to 0xFF, maximum of all current parts?
putative yes..
>
>> +static const struct ocotp_params imx8mm_params = {
>> + .nregs = 64,
>
> Why nregs=64? fusemap in RM documents fuses from 0x400 and 0x13f0 so 256
> in total. But most of those are reserved anyway.
Hrmm.
I did print out all of the address offsets all the way up to what is
documented @ 3035_07B0h but, now that you ask the question I will check
that again.
I'll rebase this against linux-next/master.
---
bod
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next prev parent reply other threads:[~2019-04-19 11:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-19 10:03 [PATCH 0/6] Add i.MX8MM support Bryan O'Donoghue
2019-04-19 10:03 ` [PATCH 1/6] nvmem: imx-ocotp: Allow selection of OCOTP for imx8 processors Bryan O'Donoghue
2019-04-19 10:03 ` [PATCH 2/6] nvmem: imx-ocotp: Fix i.MX OC-OTP naming prompt Bryan O'Donoghue
2019-04-19 10:03 ` [PATCH 3/6] nvmem: imx-ocotp: Add i.MX8MM support Bryan O'Donoghue
2019-04-19 10:32 ` Leonard Crestez
2019-04-19 11:48 ` Bryan O'Donoghue [this message]
2019-04-19 16:45 ` Bryan O'Donoghue
2019-04-19 10:03 ` [PATCH 4/6] nvmem: imx-ocotp: Ensure WAIT bits are preserved when setting timing Bryan O'Donoghue
2019-04-19 10:03 ` [PATCH 5/6] nvmem: imx-ocotp: Ensure the RELAX field is non-zero Bryan O'Donoghue
2019-04-19 10:03 ` [PATCH 6/6] dt-bindings: imx-ocotp: Add i.MX8MM support Bryan O'Donoghue
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