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From: "Durrant, Paul" <xadimgnik@gmail.com>
To: Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Paul Durrant <paul@xen.org>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: Re: Ping: [PATCH v2 3/3] AMD/IOMMU: consider hidden devices when flushing device I/O TLBs
Date: Mon, 11 Oct 2021 10:45:53 +0100	[thread overview]
Message-ID: <b2d4ec6f-3cfb-0dd7-e499-112437e132ae@gmail.com> (raw)
In-Reply-To: <2b6cdf04-ab6b-bbbd-6df1-d90fc22752f8@suse.com>

On 11/10/2021 09:04, Jan Beulich wrote:
> On 17.09.2021 13:00, Jan Beulich wrote:
>> Hidden devices are associated with DomXEN but usable by the
>> hardware domain. Hence they need flushing as well when all devices are
>> to have flushes invoked.
>>
>> While there drop a redundant ATS-enabled check and constify the first
>> parameter of the involved function.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> 
> The VT-d side equivalent having gone in a while ago, I think it would
> be good to have the AMD side on par.
> 

Agreed.

Reviewed-by: Paul Durrant <paul@xen.org>


      reply	other threads:[~2021-10-11  9:46 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-17 10:58 [PATCH v2 0/3] IOMMU/PCI: respect device specifics Jan Beulich
2021-09-17 11:00 ` [PATCH v2 1/3] VT-d: consider hidden devices when unmapping Jan Beulich
2021-09-18  0:48   ` Tian, Kevin
2021-09-17 11:00 ` [PATCH v2 2/3] VT-d: PCI segments are up to 16 bits wide Jan Beulich
2021-09-18  0:49   ` Tian, Kevin
2021-09-17 11:00 ` [PATCH v2 3/3] AMD/IOMMU: consider hidden devices when flushing device I/O TLBs Jan Beulich
2021-10-11  8:04   ` Ping: " Jan Beulich
2021-10-11  9:45     ` Durrant, Paul [this message]

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