* [PATCH] arm64: dts: mediatek: Initial mt8365-evk support
@ 2022-11-07 21:10 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-07 21:10 UTC (permalink / raw)
To: linux-mediatek, linux-arm-kernel, linux-kernel, devicetree,
robh+dt, krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
This adds minimal support for the MediaTek 8365 SOC and the EVK reference
board, allowing the board to boot to initramfs with serial port I/O.
GPIO keys are supported, MMC is partially supported (needs the clocks
driver for full support).
Signed-off-by: Fabien Parent <fparent@baylibre.com>
[bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Compared to the previous version of the patch submitted by Fabien
Parent, this removes dependencies on drivers/patches that are not yet in
mainline (obviously this comes with some reduced functionality for now;
this will be added back as drivers are accepted), and addresses some
feedback from reviewers.
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 602 ++++++++++++++++++++
3 files changed, 947 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 0ec90cb3ef289..e668fd50a3326 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
new file mode 100644
index 0000000000000..a24e478fff51f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2022 BayLibre, SAS.
+ * Authors:
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
+#include "mt8365.dtsi"
+
+/ {
+ model = "MediaTek MT8365 Open Platform EVK";
+ compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys>;
+
+ key-volume-up {
+ gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xc0000000>;
+ };
+
+ usb_otg_vbus: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&pio {
+ dpi_func_pins: dpi-func-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
+ <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
+ <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
+ <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
+ <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
+ <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
+ <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
+ <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
+ <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
+ <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
+ <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
+ <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
+ <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
+ <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
+ <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
+ <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ dpi_idle_pins: dpi-idle-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
+ <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
+ <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
+ <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
+ <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
+ <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
+ <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
+ <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
+ <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
+ <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
+ <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
+ <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
+ <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
+ <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
+ <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
+ <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
+ };
+ };
+
+ gpio_keys: gpio-keys-pins {
+ pins {
+ pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
+ <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ bias-pull-up;
+ };
+ };
+
+ ite_pins: ite-pins {
+ pins-rst-ite {
+ pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
+ output-high;
+ };
+
+ pins-irq-ite {
+ pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-pwr {
+ pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
+ <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
+ output-high;
+ };
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_pins_default: mmc1-default-pins {
+ pins-cd {
+ pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
+ bias-pull-up;
+ };
+
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
+ <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
+ <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
+ <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
+ };
+ };
+
+ usb_pins: usb-pins {
+ pins-id {
+ pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-usb0-vbus {
+ pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
+ output-high;
+ };
+
+ pin-usb1-vbus {
+ pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
+ output-high;
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ pins {
+ pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
+ <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
+ };
+ };
+};
+
+&pwm {
+ pinctrl-0 = <&pwm_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
new file mode 100644
index 0000000000000..8b20e3e5f807d
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) 2018 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+#include <dt-bindings/clock/mediatek,mt8365-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "mediatek,mt8365";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@43000000 {
+ no-map;
+ reg = <0 0x43000000 0 0x20000>;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x80000>,
+ <0 0x0c080000 0 0x80000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8365-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8365-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ syscfg_pctl: syscfg-pctl@10005000 {
+ compatible = "mediatek,mt8365-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8365-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
+ };
+
+ gpt: apxgpt@10008000 {
+ compatible = "mediatek,mt8365-timer",
+ "mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYS_26M_D2>;
+ clock-names = "clk13m";
+ };
+
+ pio: pinctrl@1000b000 {
+ compatible = "mediatek,mt8365-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8365-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8365-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
+ <&infracfg CLK_IFR_PMIC_AP>,
+ <&infracfg CLK_IFR_PWRAP_SYS>,
+ <&infracfg CLK_IFR_PWRAP_TMR>;
+ clock-names = "spi", "wrap", "sys", "tmr";
+ };
+
+ keypad: keypad@10010000 {
+ compatible = "mediatek,mt6779-keypad";
+ reg = <0 0x10010000 0 0x1000>;
+ wakeup-source;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&clk26m>;
+ clock-names = "kpd";
+ status = "disabled";
+ };
+
+ mcucfg: syscon@10200000 {
+ compatible = "mediatek,mt8365-mcucfg", "syscon";
+ reg = <0 0x10200000 0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt8365-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x20>;
+ };
+
+ infracfg_nao: infracfg-nao@1020e000 {
+ compatible = "syscon";
+ reg = <0 0x1020e000 0 0x1000>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt8365-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x100>;
+ clocks = <&infracfg CLK_IFR_TRNG>;
+ clock-names = "rng";
+ };
+
+ apdma: dma-controller@11000280 {
+ compatible = "mediatek,mt8365-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000280 0 0x80>,
+ <0 0x11000300 0 0x80>,
+ <0 0x11000380 0 0x80>,
+ <0 0x11000400 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <6>;
+ clocks = <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt8365-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt8365-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_PWM_HCLK>,
+ <&infracfg CLK_IFR_PWM>,
+ <&infracfg CLK_IFR_PWM1>,
+ <&infracfg CLK_IFR_PWM2>,
+ <&infracfg CLK_IFR_PWM3>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11007000 0 0xa0>,
+ <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C0_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11008000 0 0xa0>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C1_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11009000 0 0xa0>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C2_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt8365-spi",
+ "mediatek,mt7622-spi";
+ reg = <0 0x1100a000 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_IFR_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ thermal: thermal@1100b000 {
+ compatible = "mediatek,mt8365-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_THERM>,
+ <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "therm", "auxadc";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ };
+
+ i2c3: i2c@1100f000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x1100f000 0 0xa0>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C3_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssusb: usb@11201000 {
+ compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: usb@11200000 {
+ compatible = "mediatek,mt8365-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>,
+ <&infracfg CLK_IFR_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck", "xhci_ck";
+ status = "disabled";
+ };
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_IFR_MSDC0_HCLK>,
+ <&infracfg CLK_IFR_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&infracfg CLK_IFR_MSDC1_HCLK>,
+ <&infracfg CLK_IFR_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ ethernet: ethernet@112a0000 {
+ compatible = "mediatek,mt8365-eth";
+ reg = <0 0x112a0000 0 0x1000>;
+ mediatek,pericfg = <&infracfg>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <&infracfg CLK_IFR_NIC_AXI>,
+ <&infracfg CLK_IFR_NIC_SLV_AXI>;
+ clock-names = "core", "reg", "trans";
+ status = "disabled";
+ };
+
+ mipi_tx0: dsi-phy@11c00000 {
+ compatible = "mediatek,mt8365-mipi-tx",
+ "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c00000 0 0x800>;
+ clocks = <&clk26m>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ };
+
+ efuse: efuse@11c50000 {
+ compatible = "mediatek,mt8365-efuse", "mediatek,efuse";
+ reg = <0 0x11c50000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
+ };
+
+ u3phy: t-phy@11cc0000 {
+ compatible = "mediatek,mt8365-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #phy-cells = <1>;
+ ranges;
+
+ u2port0: usb-phy@11cc0000 {
+ reg = <0 0x11cc0000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@11cc1000 {
+ reg = <0 0x11cc1000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt8365-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8365-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@15000000 {
+ compatible = "mediatek,mt8365-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8365-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8365-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apu: syscon@19020000 {
+ compatible = "mediatek,mt8365-apu", "syscon";
+ reg = <0 0x19020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point1 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit0 {
+ temperature = <117000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device =
+ <&cpu0
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu1
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu2
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu3
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ contribution = <100>;
+ };
+ };
+ };
+ };
+
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH] arm64: dts: mediatek: Initial mt8365-evk support
@ 2022-11-07 21:10 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-07 21:10 UTC (permalink / raw)
To: linux-mediatek, linux-arm-kernel, linux-kernel, devicetree,
robh+dt, krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
This adds minimal support for the MediaTek 8365 SOC and the EVK reference
board, allowing the board to boot to initramfs with serial port I/O.
GPIO keys are supported, MMC is partially supported (needs the clocks
driver for full support).
Signed-off-by: Fabien Parent <fparent@baylibre.com>
[bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Compared to the previous version of the patch submitted by Fabien
Parent, this removes dependencies on drivers/patches that are not yet in
mainline (obviously this comes with some reduced functionality for now;
this will be added back as drivers are accepted), and addresses some
feedback from reviewers.
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 602 ++++++++++++++++++++
3 files changed, 947 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 0ec90cb3ef289..e668fd50a3326 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
new file mode 100644
index 0000000000000..a24e478fff51f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2022 BayLibre, SAS.
+ * Authors:
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
+#include "mt8365.dtsi"
+
+/ {
+ model = "MediaTek MT8365 Open Platform EVK";
+ compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys>;
+
+ key-volume-up {
+ gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xc0000000>;
+ };
+
+ usb_otg_vbus: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&pio {
+ dpi_func_pins: dpi-func-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
+ <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
+ <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
+ <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
+ <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
+ <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
+ <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
+ <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
+ <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
+ <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
+ <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
+ <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
+ <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
+ <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
+ <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
+ <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ dpi_idle_pins: dpi-idle-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
+ <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
+ <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
+ <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
+ <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
+ <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
+ <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
+ <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
+ <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
+ <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
+ <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
+ <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
+ <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
+ <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
+ <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
+ <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
+ };
+ };
+
+ gpio_keys: gpio-keys-pins {
+ pins {
+ pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
+ <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ bias-pull-up;
+ };
+ };
+
+ ite_pins: ite-pins {
+ pins-rst-ite {
+ pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
+ output-high;
+ };
+
+ pins-irq-ite {
+ pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-pwr {
+ pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
+ <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
+ output-high;
+ };
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_pins_default: mmc1-default-pins {
+ pins-cd {
+ pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
+ bias-pull-up;
+ };
+
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
+ <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
+ <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
+ <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
+ };
+ };
+
+ usb_pins: usb-pins {
+ pins-id {
+ pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-usb0-vbus {
+ pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
+ output-high;
+ };
+
+ pin-usb1-vbus {
+ pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
+ output-high;
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ pins {
+ pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
+ <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
+ };
+ };
+};
+
+&pwm {
+ pinctrl-0 = <&pwm_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
new file mode 100644
index 0000000000000..8b20e3e5f807d
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) 2018 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+#include <dt-bindings/clock/mediatek,mt8365-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "mediatek,mt8365";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@43000000 {
+ no-map;
+ reg = <0 0x43000000 0 0x20000>;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x80000>,
+ <0 0x0c080000 0 0x80000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8365-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8365-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ syscfg_pctl: syscfg-pctl@10005000 {
+ compatible = "mediatek,mt8365-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8365-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
+ };
+
+ gpt: apxgpt@10008000 {
+ compatible = "mediatek,mt8365-timer",
+ "mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYS_26M_D2>;
+ clock-names = "clk13m";
+ };
+
+ pio: pinctrl@1000b000 {
+ compatible = "mediatek,mt8365-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8365-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8365-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
+ <&infracfg CLK_IFR_PMIC_AP>,
+ <&infracfg CLK_IFR_PWRAP_SYS>,
+ <&infracfg CLK_IFR_PWRAP_TMR>;
+ clock-names = "spi", "wrap", "sys", "tmr";
+ };
+
+ keypad: keypad@10010000 {
+ compatible = "mediatek,mt6779-keypad";
+ reg = <0 0x10010000 0 0x1000>;
+ wakeup-source;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&clk26m>;
+ clock-names = "kpd";
+ status = "disabled";
+ };
+
+ mcucfg: syscon@10200000 {
+ compatible = "mediatek,mt8365-mcucfg", "syscon";
+ reg = <0 0x10200000 0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt8365-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x20>;
+ };
+
+ infracfg_nao: infracfg-nao@1020e000 {
+ compatible = "syscon";
+ reg = <0 0x1020e000 0 0x1000>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt8365-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x100>;
+ clocks = <&infracfg CLK_IFR_TRNG>;
+ clock-names = "rng";
+ };
+
+ apdma: dma-controller@11000280 {
+ compatible = "mediatek,mt8365-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000280 0 0x80>,
+ <0 0x11000300 0 0x80>,
+ <0 0x11000380 0 0x80>,
+ <0 0x11000400 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <6>;
+ clocks = <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt8365-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt8365-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_PWM_HCLK>,
+ <&infracfg CLK_IFR_PWM>,
+ <&infracfg CLK_IFR_PWM1>,
+ <&infracfg CLK_IFR_PWM2>,
+ <&infracfg CLK_IFR_PWM3>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11007000 0 0xa0>,
+ <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C0_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11008000 0 0xa0>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C1_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11009000 0 0xa0>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C2_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt8365-spi",
+ "mediatek,mt7622-spi";
+ reg = <0 0x1100a000 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_IFR_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ thermal: thermal@1100b000 {
+ compatible = "mediatek,mt8365-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_THERM>,
+ <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "therm", "auxadc";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ };
+
+ i2c3: i2c@1100f000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x1100f000 0 0xa0>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C3_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssusb: usb@11201000 {
+ compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: usb@11200000 {
+ compatible = "mediatek,mt8365-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>,
+ <&infracfg CLK_IFR_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck", "xhci_ck";
+ status = "disabled";
+ };
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_IFR_MSDC0_HCLK>,
+ <&infracfg CLK_IFR_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&infracfg CLK_IFR_MSDC1_HCLK>,
+ <&infracfg CLK_IFR_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ ethernet: ethernet@112a0000 {
+ compatible = "mediatek,mt8365-eth";
+ reg = <0 0x112a0000 0 0x1000>;
+ mediatek,pericfg = <&infracfg>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <&infracfg CLK_IFR_NIC_AXI>,
+ <&infracfg CLK_IFR_NIC_SLV_AXI>;
+ clock-names = "core", "reg", "trans";
+ status = "disabled";
+ };
+
+ mipi_tx0: dsi-phy@11c00000 {
+ compatible = "mediatek,mt8365-mipi-tx",
+ "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c00000 0 0x800>;
+ clocks = <&clk26m>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ };
+
+ efuse: efuse@11c50000 {
+ compatible = "mediatek,mt8365-efuse", "mediatek,efuse";
+ reg = <0 0x11c50000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
+ };
+
+ u3phy: t-phy@11cc0000 {
+ compatible = "mediatek,mt8365-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #phy-cells = <1>;
+ ranges;
+
+ u2port0: usb-phy@11cc0000 {
+ reg = <0 0x11cc0000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@11cc1000 {
+ reg = <0 0x11cc1000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt8365-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8365-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@15000000 {
+ compatible = "mediatek,mt8365-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8365-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8365-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apu: syscon@19020000 {
+ compatible = "mediatek,mt8365-apu", "syscon";
+ reg = <0 0x19020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point1 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit0 {
+ temperature = <117000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device =
+ <&cpu0
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu1
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu2
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu3
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ contribution = <100>;
+ };
+ };
+ };
+ };
+
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
--
2.38.1
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^ permalink raw reply related [flat|nested] 70+ messages in thread
* Re: [PATCH] arm64: dts: mediatek: Initial mt8365-evk support
2022-11-07 21:10 ` Bernhard Rosenkränzer
@ 2022-11-08 10:02 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-08 10:02 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek, linux-arm-kernel,
linux-kernel, devicetree, robh+dt, krzysztof.kozlowski+dt,
matthias.bgg
On 07/11/2022 22:10, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> This adds minimal support for the MediaTek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
>
> Compared to the previous version of the patch submitted by Fabien
> Parent, this removes dependencies on drivers/patches that are not yet in
> mainline (obviously this comes with some reduced functionality for now;
> this will be added back as drivers are accepted), and addresses some
> feedback from reviewers.
>
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 602 ++++++++++++++++++++
> 3 files changed, 947 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 0ec90cb3ef289..e668fd50a3326 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> new file mode 100644
> index 0000000000000..a24e478fff51f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021-2022 BayLibre, SAS.
> + * Authors:
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
> +#include "mt8365.dtsi"
> +
> +/ {
> + model = "MediaTek MT8365 Open Platform EVK";
> + compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
Missing documentation.
Run checkpatch on your patches. It will print several warnings, which
must be fixed.
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + input-name = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio_keys>;
> +
> + key-volume-up {
> + gpios = <&pio 24 GPIO_ACTIVE_LOW>;
> + label = "volume_up";
> + linux,code = <KEY_VOLUMEUP>;
> + wakeup-source;
> + debounce-interval = <15>;
> + };
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0xc0000000>;
> + };
> +
> + usb_otg_vbus: regulator-2 {
Where are regulators 0 and 1 (or just 1)?
> + compatible = "regulator-fixed";
> + regulator-name = "otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
(...)
> +
> + mcucfg: syscon@10200000 {
> + compatible = "mediatek,mt8365-mcucfg", "syscon";
> + reg = <0 0x10200000 0 0x2000>;
> + #clock-cells = <1>;
> + };
> +
> + sysirq: interrupt-controller@10200a80 {
> + compatible = "mediatek,mt8365-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10200a80 0 0x20>;
> + };
> +
> + infracfg_nao: infracfg-nao@1020e000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "syscon";
Not allowed on its own.
> + reg = <0 0x1020e000 0 0x1000>;
> + };
> +
> + rng: rng@1020f000 {
> + compatible = "mediatek,mt8365-rng",
> + "mediatek,mt7623-rng";
> + reg = <0 0x1020f000 0 0x100>;
> + clocks = <&infracfg CLK_IFR_TRNG>;
> + clock-names = "rng";
> + };
> +
> + apdma: dma-controller@11000280 {
> + compatible = "mediatek,mt8365-uart-dma",
> + "mediatek,mt6577-uart-dma";
> + reg = <0 0x11000280 0 0x80>,
> + <0 0x11000300 0 0x80>,
> + <0 0x11000380 0 0x80>,
> + <0 0x11000400 0 0x80>,
> + <0 0x11000580 0 0x80>,
> + <0 0x11000600 0 0x80>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
> + dma-requests = <6>;
> + clocks = <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "apdma";
> + #dma-cells = <1>;
> + };
> +
> + auxadc: adc@11001000 {
> + compatible = "mediatek,mt8365-auxadc",
> + "mediatek,mt8173-auxadc";
> + reg = <0 0x11001000 0 0x1000>;
> + clocks = <&infracfg CLK_IFR_AUXADC>;
> + clock-names = "main";
> + #io-channel-cells = <1>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 0>, <&apdma 1>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 2>, <&apdma 3>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + uart2: serial@11004000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11004000 0 0x1000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 4>, <&apdma 5>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + pwm: pwm@11006000 {
> + compatible = "mediatek,mt8365-pwm";
> + reg = <0 0x11006000 0 0x1000>;
> + #pwm-cells = <2>;
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_IFR_PWM_HCLK>,
> + <&infracfg CLK_IFR_PWM>,
> + <&infracfg CLK_IFR_PWM1>,
> + <&infracfg CLK_IFR_PWM2>,
> + <&infracfg CLK_IFR_PWM3>;
> + clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
> + };
> +
> + i2c0: i2c@11007000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11007000 0 0xa0>,
> + <0 0x11000080 0 0x80>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C0_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@11008000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11008000 0 0xa0>,
> + <0 0x11000100 0 0x80>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C1_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@11009000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11009000 0 0xa0>,
> + <0 0x11000180 0 0x80>;
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C2_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi: spi@1100a000 {
> + compatible = "mediatek,mt8365-spi",
> + "mediatek,mt7622-spi";
> + reg = <0 0x1100a000 0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_IFR_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + status = "disabled";
> + };
> +
> + thermal: thermal@1100b000 {
> + compatible = "mediatek,mt8365-thermal";
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_IFR_THERM>,
> + <&infracfg CLK_IFR_AUXADC>;
> + clock-names = "therm", "auxadc";
> + mediatek,auxadc = <&auxadc>;
> + mediatek,apmixedsys = <&apmixedsys>;
> + nvmem-cells = <&thermal_calibration>;
> + nvmem-cell-names = "calibration-data";
> + #thermal-sensor-cells = <1>;
> + };
> +
> + i2c3: i2c@1100f000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x1100f000 0 0xa0>,
> + <0 0x11000200 0 0x80>;
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C3_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + ssusb: usb@11201000 {
> + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
> + reg = <0 0x11201000 0 0x2e00>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u2port1 PHY_TYPE_USB2>;
> + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
> + <&infracfg CLK_IFR_SSUSB_REF>,
> + <&infracfg CLK_IFR_SSUSB_SYS>,
> + <&infracfg CLK_IFR_ICUSB>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck",
> + "dma_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usb_host: usb@11200000 {
> + compatible = "mediatek,mt8365-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
> + <&infracfg CLK_IFR_SSUSB_REF>,
> + <&infracfg CLK_IFR_SSUSB_SYS>,
> + <&infracfg CLK_IFR_ICUSB>,
> + <&infracfg CLK_IFR_SSUSB_XHCI>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck",
> + "dma_ck", "xhci_ck";
> + status = "disabled";
> + };
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&infracfg CLK_IFR_MSDC0_HCLK>,
> + <&infracfg CLK_IFR_MSDC0_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> + <&infracfg CLK_IFR_MSDC1_HCLK>,
> + <&infracfg CLK_IFR_MSDC1_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + ethernet: ethernet@112a0000 {
> + compatible = "mediatek,mt8365-eth";
> + reg = <0 0x112a0000 0 0x1000>;
> + mediatek,pericfg = <&infracfg>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&topckgen CLK_TOP_ETH_SEL>,
> + <&infracfg CLK_IFR_NIC_AXI>,
> + <&infracfg CLK_IFR_NIC_SLV_AXI>;
> + clock-names = "core", "reg", "trans";
> + status = "disabled";
> + };
> +
> + mipi_tx0: dsi-phy@11c00000 {
> + compatible = "mediatek,mt8365-mipi-tx",
> + "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11c00000 0 0x800>;
> + clocks = <&clk26m>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
> + };
> +
> + efuse: efuse@11c50000 {
> + compatible = "mediatek,mt8365-efuse", "mediatek,efuse";
> + reg = <0 0x11c50000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + thermal_calibration: calib@180 {
> + reg = <0x180 0xc>;
> + };
> + };
> +
> + u3phy: t-phy@11cc0000 {
Node names should be generic, so just phy
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "mediatek,mt8365-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #phy-cells = <1>;
> + ranges;
> +
> + u2port0: usb-phy@11cc0000 {
> + reg = <0 0x11cc0000 0 0x400>;
> + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + };
> +
> + u2port1: usb-phy@11cc1000 {
> + reg = <0 0x11cc1000 0 0x400>;
> + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + mfgcfg: syscon@13000000 {
> + compatible = "mediatek,mt8365-mfgcfg", "syscon";
> + reg = <0 0x13000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt8365-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys: syscon@15000000 {
> + compatible = "mediatek,mt8365-imgsys", "syscon";
> + reg = <0 0x15000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys: syscon@16000000 {
> + compatible = "mediatek,mt8365-vdecsys", "syscon";
> + reg = <0 0x16000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vencsys: syscon@17000000 {
> + compatible = "mediatek,mt8365-vencsys", "syscon";
> + reg = <0 0x17000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apu: syscon@19020000 {
> + compatible = "mediatek,mt8365-apu", "syscon";
> + reg = <0 0x19020000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> + };
> +
> + thermal-zones {
> + cpu_thermal: cpu-thermal {
> + polling-delay-passive = <1000>; /* milliseconds */
> + polling-delay = <1000>; /* milliseconds */
> + thermal-sensors = <&thermal 0>;
> +
> + trips {
> + threshold: trip-point0 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + target: trip-point1 {
> + temperature = <105000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit: cpu_crit0 {
> + temperature = <117000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&target>;
> + cooling-device =
> + <&cpu0
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu1
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu2
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu3
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <100>;
> + };
> + };
> + };
> + };
> +
> +
Only one blank line.
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
> + };
> +};
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH] arm64: dts: mediatek: Initial mt8365-evk support
@ 2022-11-08 10:02 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-08 10:02 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek, linux-arm-kernel,
linux-kernel, devicetree, robh+dt, krzysztof.kozlowski+dt,
matthias.bgg
On 07/11/2022 22:10, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> This adds minimal support for the MediaTek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
>
> Compared to the previous version of the patch submitted by Fabien
> Parent, this removes dependencies on drivers/patches that are not yet in
> mainline (obviously this comes with some reduced functionality for now;
> this will be added back as drivers are accepted), and addresses some
> feedback from reviewers.
>
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 602 ++++++++++++++++++++
> 3 files changed, 947 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 0ec90cb3ef289..e668fd50a3326 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> new file mode 100644
> index 0000000000000..a24e478fff51f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021-2022 BayLibre, SAS.
> + * Authors:
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
> +#include "mt8365.dtsi"
> +
> +/ {
> + model = "MediaTek MT8365 Open Platform EVK";
> + compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
Missing documentation.
Run checkpatch on your patches. It will print several warnings, which
must be fixed.
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + input-name = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio_keys>;
> +
> + key-volume-up {
> + gpios = <&pio 24 GPIO_ACTIVE_LOW>;
> + label = "volume_up";
> + linux,code = <KEY_VOLUMEUP>;
> + wakeup-source;
> + debounce-interval = <15>;
> + };
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0xc0000000>;
> + };
> +
> + usb_otg_vbus: regulator-2 {
Where are regulators 0 and 1 (or just 1)?
> + compatible = "regulator-fixed";
> + regulator-name = "otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
(...)
> +
> + mcucfg: syscon@10200000 {
> + compatible = "mediatek,mt8365-mcucfg", "syscon";
> + reg = <0 0x10200000 0 0x2000>;
> + #clock-cells = <1>;
> + };
> +
> + sysirq: interrupt-controller@10200a80 {
> + compatible = "mediatek,mt8365-sysirq",
> + "mediatek,mt6577-sysirq";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupt-parent = <&gic>;
> + reg = <0 0x10200a80 0 0x20>;
> + };
> +
> + infracfg_nao: infracfg-nao@1020e000 {
Node names should be generic.
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "syscon";
Not allowed on its own.
> + reg = <0 0x1020e000 0 0x1000>;
> + };
> +
> + rng: rng@1020f000 {
> + compatible = "mediatek,mt8365-rng",
> + "mediatek,mt7623-rng";
> + reg = <0 0x1020f000 0 0x100>;
> + clocks = <&infracfg CLK_IFR_TRNG>;
> + clock-names = "rng";
> + };
> +
> + apdma: dma-controller@11000280 {
> + compatible = "mediatek,mt8365-uart-dma",
> + "mediatek,mt6577-uart-dma";
> + reg = <0 0x11000280 0 0x80>,
> + <0 0x11000300 0 0x80>,
> + <0 0x11000380 0 0x80>,
> + <0 0x11000400 0 0x80>,
> + <0 0x11000580 0 0x80>,
> + <0 0x11000600 0 0x80>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
> + dma-requests = <6>;
> + clocks = <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "apdma";
> + #dma-cells = <1>;
> + };
> +
> + auxadc: adc@11001000 {
> + compatible = "mediatek,mt8365-auxadc",
> + "mediatek,mt8173-auxadc";
> + reg = <0 0x11001000 0 0x1000>;
> + clocks = <&infracfg CLK_IFR_AUXADC>;
> + clock-names = "main";
> + #io-channel-cells = <1>;
> + };
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 0>, <&apdma 1>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + uart1: serial@11003000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11003000 0 0x1000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 2>, <&apdma 3>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + uart2: serial@11004000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
> + reg = <0 0x11004000 0 0x1000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 4>, <&apdma 5>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
> + pwm: pwm@11006000 {
> + compatible = "mediatek,mt8365-pwm";
> + reg = <0 0x11006000 0 0x1000>;
> + #pwm-cells = <2>;
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_IFR_PWM_HCLK>,
> + <&infracfg CLK_IFR_PWM>,
> + <&infracfg CLK_IFR_PWM1>,
> + <&infracfg CLK_IFR_PWM2>,
> + <&infracfg CLK_IFR_PWM3>;
> + clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
> + };
> +
> + i2c0: i2c@11007000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11007000 0 0xa0>,
> + <0 0x11000080 0 0x80>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C0_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@11008000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11008000 0 0xa0>,
> + <0 0x11000100 0 0x80>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C1_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@11009000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11009000 0 0xa0>,
> + <0 0x11000180 0 0x80>;
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C2_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi: spi@1100a000 {
> + compatible = "mediatek,mt8365-spi",
> + "mediatek,mt7622-spi";
> + reg = <0 0x1100a000 0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_IFR_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + status = "disabled";
> + };
> +
> + thermal: thermal@1100b000 {
> + compatible = "mediatek,mt8365-thermal";
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_IFR_THERM>,
> + <&infracfg CLK_IFR_AUXADC>;
> + clock-names = "therm", "auxadc";
> + mediatek,auxadc = <&auxadc>;
> + mediatek,apmixedsys = <&apmixedsys>;
> + nvmem-cells = <&thermal_calibration>;
> + nvmem-cell-names = "calibration-data";
> + #thermal-sensor-cells = <1>;
> + };
> +
> + i2c3: i2c@1100f000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x1100f000 0 0xa0>,
> + <0 0x11000200 0 0x80>;
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C3_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + ssusb: usb@11201000 {
> + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
> + reg = <0 0x11201000 0 0x2e00>,
> + <0 0x11203e00 0 0x0100>;
> + reg-names = "mac", "ippc";
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
> + phys = <&u2port0 PHY_TYPE_USB2>,
> + <&u2port1 PHY_TYPE_USB2>;
> + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
> + <&infracfg CLK_IFR_SSUSB_REF>,
> + <&infracfg CLK_IFR_SSUSB_SYS>,
> + <&infracfg CLK_IFR_ICUSB>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck",
> + "dma_ck";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + usb_host: usb@11200000 {
> + compatible = "mediatek,mt8365-xhci",
> + "mediatek,mtk-xhci";
> + reg = <0 0x11200000 0 0x1000>;
> + reg-names = "mac";
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
> + <&infracfg CLK_IFR_SSUSB_REF>,
> + <&infracfg CLK_IFR_SSUSB_SYS>,
> + <&infracfg CLK_IFR_ICUSB>,
> + <&infracfg CLK_IFR_SSUSB_XHCI>;
> + clock-names = "sys_ck", "ref_ck", "mcu_ck",
> + "dma_ck", "xhci_ck";
> + status = "disabled";
> + };
> + };
> +
> + mmc0: mmc@11230000 {
> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11230000 0 0x1000>,
> + <0 0x11cd0000 0 0x1000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> + <&infracfg CLK_IFR_MSDC0_HCLK>,
> + <&infracfg CLK_IFR_MSDC0_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@11240000 {
> + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
> + reg = <0 0x11240000 0 0x1000>,
> + <0 0x11c90000 0 0x1000>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> + <&infracfg CLK_IFR_MSDC1_HCLK>,
> + <&infracfg CLK_IFR_MSDC1_SRC>;
> + clock-names = "source", "hclk", "source_cg";
> + status = "disabled";
> + };
> +
> + ethernet: ethernet@112a0000 {
> + compatible = "mediatek,mt8365-eth";
> + reg = <0 0x112a0000 0 0x1000>;
> + mediatek,pericfg = <&infracfg>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&topckgen CLK_TOP_ETH_SEL>,
> + <&infracfg CLK_IFR_NIC_AXI>,
> + <&infracfg CLK_IFR_NIC_SLV_AXI>;
> + clock-names = "core", "reg", "trans";
> + status = "disabled";
> + };
> +
> + mipi_tx0: dsi-phy@11c00000 {
> + compatible = "mediatek,mt8365-mipi-tx",
> + "mediatek,mt8183-mipi-tx";
> + reg = <0 0x11c00000 0 0x800>;
> + clocks = <&clk26m>;
> + clock-names = "ref_clk";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clock-output-names = "mipi_tx0_pll";
> + };
> +
> + efuse: efuse@11c50000 {
> + compatible = "mediatek,mt8365-efuse", "mediatek,efuse";
> + reg = <0 0x11c50000 0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + thermal_calibration: calib@180 {
> + reg = <0x180 0xc>;
> + };
> + };
> +
> + u3phy: t-phy@11cc0000 {
Node names should be generic, so just phy
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
> + compatible = "mediatek,mt8365-tphy",
> + "mediatek,generic-tphy-v2";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + #phy-cells = <1>;
> + ranges;
> +
> + u2port0: usb-phy@11cc0000 {
> + reg = <0 0x11cc0000 0 0x400>;
> + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + };
> +
> + u2port1: usb-phy@11cc1000 {
> + reg = <0 0x11cc1000 0 0x400>;
> + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
> + <&topckgen CLK_TOP_USB20_48M_EN>;
> + clock-names = "ref", "da_ref";
> + #phy-cells = <1>;
> + };
> + };
> +
> + mfgcfg: syscon@13000000 {
> + compatible = "mediatek,mt8365-mfgcfg", "syscon";
> + reg = <0 0x13000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt8365-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + camsys: syscon@15000000 {
> + compatible = "mediatek,mt8365-imgsys", "syscon";
> + reg = <0 0x15000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys: syscon@16000000 {
> + compatible = "mediatek,mt8365-vdecsys", "syscon";
> + reg = <0 0x16000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vencsys: syscon@17000000 {
> + compatible = "mediatek,mt8365-vencsys", "syscon";
> + reg = <0 0x17000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + apu: syscon@19020000 {
> + compatible = "mediatek,mt8365-apu", "syscon";
> + reg = <0 0x19020000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> + };
> +
> + thermal-zones {
> + cpu_thermal: cpu-thermal {
> + polling-delay-passive = <1000>; /* milliseconds */
> + polling-delay = <1000>; /* milliseconds */
> + thermal-sensors = <&thermal 0>;
> +
> + trips {
> + threshold: trip-point0 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + target: trip-point1 {
> + temperature = <105000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit: cpu_crit0 {
> + temperature = <117000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&target>;
> + cooling-device =
> + <&cpu0
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu1
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu2
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <&cpu3
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <100>;
> + };
> + };
> + };
> + };
> +
> +
Only one blank line.
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
> + };
> +};
Best regards,
Krzysztof
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH v2 00/15] Initial Mediatek MT8365 SOC and MT8365-EVK board support
2022-11-07 21:10 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
This adds minimal support for the MediaTek 8365 SOC and the EVK reference
board, allowing the board to boot to initramfs with serial port I/O.
GPIO keys are supported, MMC is partially supported (needs the clocks
driver for full support).
v2:
- Add missing dt-bindings documentation
- Small cleanups addressing issues in v1 pointed out by Krzysztof Kozlowski
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH v2 00/15] Initial Mediatek MT8365 SOC and MT8365-EVK board support
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
This adds minimal support for the MediaTek 8365 SOC and the EVK reference
board, allowing the board to boot to initramfs with serial port I/O.
GPIO keys are supported, MMC is partially supported (needs the clocks
driver for full support).
v2:
- Add missing dt-bindings documentation
- Small cleanups addressing issues in v1 pointed out by Krzysztof Kozlowski
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
This adds minimal support for the Mediatek 8365 SOC and the EVK reference
board, allowing the board to boot to initramfs with serial port I/O.
GPIO keys are supported, MMC is partially supported (needs the clocks
driver for full support).
Signed-off-by: Fabien Parent <fparent@baylibre.com>
[bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++
3 files changed, 946 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 0ec90cb3ef289..e668fd50a3326 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
new file mode 100644
index 0000000000000..74e0f75231637
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2022 BayLibre, SAS.
+ * Authors:
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
+#include "mt8365.dtsi"
+
+/ {
+ model = "MediaTek MT8365 Open Platform EVK";
+ compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys>;
+
+ key-volume-up {
+ gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xc0000000>;
+ };
+
+ usb_otg_vbus: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&pio {
+ dpi_func_pins: dpi-func-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
+ <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
+ <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
+ <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
+ <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
+ <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
+ <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
+ <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
+ <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
+ <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
+ <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
+ <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
+ <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
+ <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
+ <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
+ <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ dpi_idle_pins: dpi-idle-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
+ <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
+ <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
+ <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
+ <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
+ <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
+ <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
+ <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
+ <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
+ <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
+ <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
+ <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
+ <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
+ <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
+ <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
+ <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
+ };
+ };
+
+ gpio_keys: gpio-keys-pins {
+ pins {
+ pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
+ <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ bias-pull-up;
+ };
+ };
+
+ ite_pins: ite-pins {
+ pins-rst-ite {
+ pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
+ output-high;
+ };
+
+ pins-irq-ite {
+ pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-pwr {
+ pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
+ <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
+ output-high;
+ };
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_pins_default: mmc1-default-pins {
+ pins-cd {
+ pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
+ bias-pull-up;
+ };
+
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
+ <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
+ <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
+ <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
+ };
+ };
+
+ usb_pins: usb-pins {
+ pins-id {
+ pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-usb0-vbus {
+ pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
+ output-high;
+ };
+
+ pin-usb1-vbus {
+ pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
+ output-high;
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ pins {
+ pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
+ <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
+ };
+ };
+};
+
+&pwm {
+ pinctrl-0 = <&pwm_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
new file mode 100644
index 0000000000000..1cf2172081b20
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) 2018 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+#include <dt-bindings/clock/mediatek,mt8365-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "mediatek,mt8365";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@43000000 {
+ no-map;
+ reg = <0 0x43000000 0 0x20000>;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x80000>,
+ <0 0x0c080000 0 0x80000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8365-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8365-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ syscfg_pctl: syscfg-pctl@10005000 {
+ compatible = "mediatek,mt8365-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8365-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
+ };
+
+ gpt: apxgpt@10008000 {
+ compatible = "mediatek,mt8365-timer",
+ "mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYS_26M_D2>;
+ clock-names = "clk13m";
+ };
+
+ pio: pinctrl@1000b000 {
+ compatible = "mediatek,mt8365-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8365-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8365-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
+ <&infracfg CLK_IFR_PMIC_AP>,
+ <&infracfg CLK_IFR_PWRAP_SYS>,
+ <&infracfg CLK_IFR_PWRAP_TMR>;
+ clock-names = "spi", "wrap", "sys", "tmr";
+ };
+
+ keypad: keypad@10010000 {
+ compatible = "mediatek,mt6779-keypad";
+ reg = <0 0x10010000 0 0x1000>;
+ wakeup-source;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&clk26m>;
+ clock-names = "kpd";
+ status = "disabled";
+ };
+
+ mcucfg: syscon@10200000 {
+ compatible = "mediatek,mt8365-mcucfg", "syscon";
+ reg = <0 0x10200000 0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt8365-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x20>;
+ };
+
+ infracfg: infracfg@1020e000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x1020e000 0 0x1000>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt8365-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x100>;
+ clocks = <&infracfg CLK_IFR_TRNG>;
+ clock-names = "rng";
+ };
+
+ apdma: dma-controller@11000280 {
+ compatible = "mediatek,mt8365-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000280 0 0x80>,
+ <0 0x11000300 0 0x80>,
+ <0 0x11000380 0 0x80>,
+ <0 0x11000400 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <6>;
+ clocks = <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt8365-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt8365-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_PWM_HCLK>,
+ <&infracfg CLK_IFR_PWM>,
+ <&infracfg CLK_IFR_PWM1>,
+ <&infracfg CLK_IFR_PWM2>,
+ <&infracfg CLK_IFR_PWM3>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11007000 0 0xa0>,
+ <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C0_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11008000 0 0xa0>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C1_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11009000 0 0xa0>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C2_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt8365-spi",
+ "mediatek,mt7622-spi";
+ reg = <0 0x1100a000 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_IFR_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ thermal: thermal@1100b000 {
+ compatible = "mediatek,mt8365-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_THERM>,
+ <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "therm", "auxadc";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ };
+
+ i2c3: i2c@1100f000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x1100f000 0 0xa0>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C3_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssusb: usb@11201000 {
+ compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: usb@11200000 {
+ compatible = "mediatek,mt8365-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>,
+ <&infracfg CLK_IFR_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck", "xhci_ck";
+ status = "disabled";
+ };
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_IFR_MSDC0_HCLK>,
+ <&infracfg CLK_IFR_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&infracfg CLK_IFR_MSDC1_HCLK>,
+ <&infracfg CLK_IFR_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ ethernet: ethernet@112a0000 {
+ compatible = "mediatek,mt8365-eth";
+ reg = <0 0x112a0000 0 0x1000>;
+ mediatek,pericfg = <&infracfg>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <&infracfg CLK_IFR_NIC_AXI>,
+ <&infracfg CLK_IFR_NIC_SLV_AXI>;
+ clock-names = "core", "reg", "trans";
+ status = "disabled";
+ };
+
+ mipi_tx0: dsi-phy@11c00000 {
+ compatible = "mediatek,mt8365-mipi-tx",
+ "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c00000 0 0x800>;
+ clocks = <&clk26m>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ };
+
+ efuse: efuse@11c50000 {
+ compatible = "mediatek,mt8365-efuse", "mediatek,efuse";
+ reg = <0 0x11c50000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
+ };
+
+ u3phy: t-phy@11cc0000 {
+ compatible = "mediatek,mt8365-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #phy-cells = <1>;
+ ranges;
+
+ u2port0: usb-phy@11cc0000 {
+ reg = <0 0x11cc0000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@11cc1000 {
+ reg = <0 0x11cc1000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt8365-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8365-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@15000000 {
+ compatible = "mediatek,mt8365-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8365-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8365-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apu: syscon@19020000 {
+ compatible = "mediatek,mt8365-apu", "syscon";
+ reg = <0 0x19020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point1 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit0 {
+ temperature = <117000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device =
+ <&cpu0
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu1
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu2
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu3
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ contribution = <100>;
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
This adds minimal support for the Mediatek 8365 SOC and the EVK reference
board, allowing the board to boot to initramfs with serial port I/O.
GPIO keys are supported, MMC is partially supported (needs the clocks
driver for full support).
Signed-off-by: Fabien Parent <fparent@baylibre.com>
[bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++
3 files changed, 946 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 0ec90cb3ef289..e668fd50a3326 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
new file mode 100644
index 0000000000000..74e0f75231637
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021-2022 BayLibre, SAS.
+ * Authors:
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
+#include "mt8365.dtsi"
+
+/ {
+ model = "MediaTek MT8365 Open Platform EVK";
+ compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys>;
+
+ key-volume-up {
+ gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xc0000000>;
+ };
+
+ usb_otg_vbus: regulator-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&pio {
+ dpi_func_pins: dpi-func-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
+ <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
+ <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
+ <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
+ <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
+ <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
+ <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
+ <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
+ <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
+ <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
+ <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
+ <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
+ <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
+ <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
+ <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
+ <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
+ drive-strength = <MTK_DRIVE_4mA>;
+ };
+ };
+
+ dpi_idle_pins: dpi-idle-pins {
+ pins {
+ pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
+ <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
+ <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
+ <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
+ <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
+ <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
+ <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
+ <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
+ <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
+ <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
+ <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
+ <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
+ <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
+ <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
+ <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
+ <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
+ };
+ };
+
+ gpio_keys: gpio-keys-pins {
+ pins {
+ pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ i2c1_pins: i2c1-pins {
+ pins {
+ pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
+ <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
+ mediatek,pull-up-adv = <3>;
+ mediatek,drive-strength-adv = <00>;
+ bias-pull-up;
+ };
+ };
+
+ ite_pins: ite-pins {
+ pins-rst-ite {
+ pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
+ output-high;
+ };
+
+ pins-irq-ite {
+ pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-pwr {
+ pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
+ <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
+ output-high;
+ };
+ };
+
+ mmc0_pins_default: mmc0-default-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ bias-pull-down;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
+ <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
+ <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
+ <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
+ <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
+ <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
+ <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
+ <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
+ <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
+ drive-strength = <MTK_DRIVE_10mA>;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_pins_default: mmc1-default-pins {
+ pins-cd {
+ pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
+ bias-pull-up;
+ };
+
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc1_pins_uhs: mmc1-uhs-pins {
+ pins-clk {
+ pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-cmd-dat {
+ pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
+ <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
+ <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
+ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
+ <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ uart0_pins: uart0-pins {
+ pins {
+ pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
+ <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ pins {
+ pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
+ <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ pins {
+ pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
+ <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
+ };
+ };
+
+ usb_pins: usb-pins {
+ pins-id {
+ pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ pins-usb0-vbus {
+ pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
+ output-high;
+ };
+
+ pin-usb1-vbus {
+ pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
+ output-high;
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ pins {
+ pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
+ <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
+ };
+ };
+};
+
+&pwm {
+ pinctrl-0 = <&pwm_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-0 = <&uart2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
new file mode 100644
index 0000000000000..1cf2172081b20
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
@@ -0,0 +1,601 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) 2018 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS
+ * Fabien Parent <fparent@baylibre.com>
+ * Bernhard Rosenkränzer <bero@baylibre.com>
+ */
+#include <dt-bindings/clock/mediatek,mt8365-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "mediatek,mt8365";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ #cooling-cells = <2>;
+ enable-method = "psci";
+ };
+ };
+
+ clk26m: oscillator {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@43000000 {
+ no-map;
+ reg = <0 0x43000000 0 0x20000>;
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x80000>,
+ <0 0x0c080000 0 0x80000>;
+
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8365-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8365-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ syscfg_pctl: syscfg-pctl@10005000 {
+ compatible = "mediatek,mt8365-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8365-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
+ };
+
+ gpt: apxgpt@10008000 {
+ compatible = "mediatek,mt8365-timer",
+ "mediatek,mt6577-timer";
+ reg = <0 0x10008000 0 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYS_26M_D2>;
+ clock-names = "clk13m";
+ };
+
+ pio: pinctrl@1000b000 {
+ compatible = "mediatek,mt8365-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8365-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pwrap: pwrap@1000d000 {
+ compatible = "mediatek,mt8365-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
+ <&infracfg CLK_IFR_PMIC_AP>,
+ <&infracfg CLK_IFR_PWRAP_SYS>,
+ <&infracfg CLK_IFR_PWRAP_TMR>;
+ clock-names = "spi", "wrap", "sys", "tmr";
+ };
+
+ keypad: keypad@10010000 {
+ compatible = "mediatek,mt6779-keypad";
+ reg = <0 0x10010000 0 0x1000>;
+ wakeup-source;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&clk26m>;
+ clock-names = "kpd";
+ status = "disabled";
+ };
+
+ mcucfg: syscon@10200000 {
+ compatible = "mediatek,mt8365-mcucfg", "syscon";
+ reg = <0 0x10200000 0 0x2000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,mt8365-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x10200a80 0 0x20>;
+ };
+
+ infracfg: infracfg@1020e000 {
+ compatible = "mediatek,mt8365-infracfg", "syscon";
+ reg = <0 0x1020e000 0 0x1000>;
+ };
+
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt8365-rng",
+ "mediatek,mt7623-rng";
+ reg = <0 0x1020f000 0 0x100>;
+ clocks = <&infracfg CLK_IFR_TRNG>;
+ clock-names = "rng";
+ };
+
+ apdma: dma-controller@11000280 {
+ compatible = "mediatek,mt8365-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000280 0 0x80>,
+ <0 0x11000300 0 0x80>,
+ <0 0x11000380 0 0x80>,
+ <0 0x11000400 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
+ dma-requests = <6>;
+ clocks = <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "apdma";
+ #dma-cells = <1>;
+ };
+
+ auxadc: adc@11001000 {
+ compatible = "mediatek,mt8365-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11001000 0 0x1000>;
+ clocks = <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x1000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ uart2: serial@11004000 {
+ compatible = "mediatek,mt8365-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11004000 0 0x1000>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
+ clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ pwm: pwm@11006000 {
+ compatible = "mediatek,mt8365-pwm";
+ reg = <0 0x11006000 0 0x1000>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_PWM_HCLK>,
+ <&infracfg CLK_IFR_PWM>,
+ <&infracfg CLK_IFR_PWM1>,
+ <&infracfg CLK_IFR_PWM2>,
+ <&infracfg CLK_IFR_PWM3>;
+ clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
+ };
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11007000 0 0xa0>,
+ <0 0x11000080 0 0x80>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C0_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@11008000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11008000 0 0xa0>,
+ <0 0x11000100 0 0x80>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C1_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11009000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x11009000 0 0xa0>,
+ <0 0x11000180 0 0x80>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C2_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi: spi@1100a000 {
+ compatible = "mediatek,mt8365-spi",
+ "mediatek,mt7622-spi";
+ reg = <0 0x1100a000 0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_IFR_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ thermal: thermal@1100b000 {
+ compatible = "mediatek,mt8365-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_IFR_THERM>,
+ <&infracfg CLK_IFR_AUXADC>;
+ clock-names = "therm", "auxadc";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ #thermal-sensor-cells = <1>;
+ };
+
+ i2c3: i2c@1100f000 {
+ compatible = "mediatek,mt8365-i2c",
+ "mediatek,mt8168-i2c";
+ reg = <0 0x1100f000 0 0xa0>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <1>;
+ clocks = <&infracfg CLK_IFR_I2C3_AXI>,
+ <&infracfg CLK_IFR_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ssusb: usb@11201000 {
+ compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u2port1 PHY_TYPE_USB2>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: usb@11200000 {
+ compatible = "mediatek,mt8365-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
+ <&infracfg CLK_IFR_SSUSB_REF>,
+ <&infracfg CLK_IFR_SSUSB_SYS>,
+ <&infracfg CLK_IFR_ICUSB>,
+ <&infracfg CLK_IFR_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck",
+ "dma_ck", "xhci_ck";
+ status = "disabled";
+ };
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x1000>,
+ <0 0x11cd0000 0 0x1000>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+ <&infracfg CLK_IFR_MSDC0_HCLK>,
+ <&infracfg CLK_IFR_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c90000 0 0x1000>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+ <&infracfg CLK_IFR_MSDC1_HCLK>,
+ <&infracfg CLK_IFR_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ ethernet: ethernet@112a0000 {
+ compatible = "mediatek,mt8365-eth";
+ reg = <0 0x112a0000 0 0x1000>;
+ mediatek,pericfg = <&infracfg>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&topckgen CLK_TOP_ETH_SEL>,
+ <&infracfg CLK_IFR_NIC_AXI>,
+ <&infracfg CLK_IFR_NIC_SLV_AXI>;
+ clock-names = "core", "reg", "trans";
+ status = "disabled";
+ };
+
+ mipi_tx0: dsi-phy@11c00000 {
+ compatible = "mediatek,mt8365-mipi-tx",
+ "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c00000 0 0x800>;
+ clocks = <&clk26m>;
+ clock-names = "ref_clk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clock-output-names = "mipi_tx0_pll";
+ };
+
+ efuse: efuse@11c50000 {
+ compatible = "mediatek,mt8365-efuse", "mediatek,efuse";
+ reg = <0 0x11c50000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
+ };
+
+ u3phy: t-phy@11cc0000 {
+ compatible = "mediatek,mt8365-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ #phy-cells = <1>;
+ ranges;
+
+ u2port0: usb-phy@11cc0000 {
+ reg = <0 0x11cc0000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u2port1: usb-phy@11cc1000 {
+ reg = <0 0x11cc1000 0 0x400>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
+ <&topckgen CLK_TOP_USB20_48M_EN>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ mfgcfg: syscon@13000000 {
+ compatible = "mediatek,mt8365-mfgcfg", "syscon";
+ reg = <0 0x13000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8365-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: syscon@15000000 {
+ compatible = "mediatek,mt8365-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8365-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: syscon@17000000 {
+ compatible = "mediatek,mt8365-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apu: syscon@19020000 {
+ compatible = "mediatek,mt8365-apu", "syscon";
+ reg = <0 0x19020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ threshold: trip-point0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point1 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit0 {
+ temperature = <117000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device =
+ <&cpu0
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu1
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu2
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>,
+ <&cpu3
+ THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ contribution = <100>;
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+};
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 02/15] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 762c62e428ef2..835af28b46de0 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -20,6 +20,7 @@ Required properties:
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
+ "mediatek,mt8365-wdt", "mediatek,mt6589-wdt": for MT8365
- reg : Specifies base physical address and size of the registers.
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 02/15] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
index 762c62e428ef2..835af28b46de0 100644
--- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
@@ -20,6 +20,7 @@ Required properties:
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
"mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
+ "mediatek,mt8365-wdt", "mediatek,mt6589-wdt": for MT8365
- reg : Specifies base physical address and size of the registers.
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 03/15] dt-bindings: iio: adc: mediatek: add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding for the ADC present in MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
.../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
index 7f79a06e76f59..ed582c6e7ea9c 100644
--- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
@@ -38,6 +38,7 @@ properties:
- mediatek,mt8188-auxadc
- mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
+ - mediatek,mt8365-auxadc
- const: mediatek,mt8173-auxadc
reg:
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 03/15] dt-bindings: iio: adc: mediatek: add MT8365 SoC bindings
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding for the ADC present in MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
.../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
index 7f79a06e76f59..ed582c6e7ea9c 100644
--- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
@@ -38,6 +38,7 @@ properties:
- mediatek,mt8188-auxadc
- mediatek,mt8195-auxadc
- mediatek,mt8516-auxadc
+ - mediatek,mt8365-auxadc
- const: mediatek,mt8173-auxadc
reg:
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 04/15] dt-bindings: i2c: i2c-mt65xx: add binding for MT8365 SoC
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 I2C controllers.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
index 421563bf576cd..2cfed35bfd9e9 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
@@ -45,6 +45,10 @@ properties:
- enum:
- mediatek,mt8195-i2c
- const: mediatek,mt8192-i2c
+ - items:
+ - enum:
+ - mediatek,mt8365-i2c
+ - const: mediatek,mt8168-i2c
reg:
items:
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 04/15] dt-bindings: i2c: i2c-mt65xx: add binding for MT8365 SoC
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 I2C controllers.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
index 421563bf576cd..2cfed35bfd9e9 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml
@@ -45,6 +45,10 @@ properties:
- enum:
- mediatek,mt8195-i2c
- const: mediatek,mt8192-i2c
+ - items:
+ - enum:
+ - mediatek,mt8365-i2c
+ - const: mediatek,mt8168-i2c
reg:
items:
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 05/15] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
index 80750b0f458a8..25934871a4d85 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
@@ -27,6 +27,7 @@ properties:
- mediatek,mt8188-mtu3
- mediatek,mt8192-mtu3
- mediatek,mt8195-mtu3
+ - mediatek,mt8365-mtu3
- const: mediatek,mtu3
reg:
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 05/15] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
index 80750b0f458a8..25934871a4d85 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
@@ -27,6 +27,7 @@ properties:
- mediatek,mt8188-mtu3
- mediatek,mt8192-mtu3
- mediatek,mt8195-mtu3
+ - mediatek,mt8365-mtu3
- const: mediatek,mtu3
reg:
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 06/15] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
index 939623867a646..3b92725bbc99b 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
@@ -34,6 +34,7 @@ properties:
- mediatek,mt8188-xhci
- mediatek,mt8192-xhci
- mediatek,mt8195-xhci
+ - mediatek,mt8365-xhci
- const: mediatek,mtk-xhci
reg:
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 06/15] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
index 939623867a646..3b92725bbc99b 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
@@ -34,6 +34,7 @@ properties:
- mediatek,mt8188-xhci
- mediatek,mt8192-xhci
- mediatek,mt8195-xhci
+ - mediatek,mt8365-xhci
- const: mediatek,mtk-xhci
reg:
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 07/15] dt-bindings: mmc: mtk-sd: add bindings for MT8365 SoC
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add MMC bindings for MT8365 bindings.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 6f8ecb4788eb8..36f9fce8f4795 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -35,6 +35,9 @@ properties:
- mediatek,mt8192-mmc
- mediatek,mt8195-mmc
- const: mediatek,mt8183-mmc
+ - items:
+ - const: mediatek,mt8365-mmc
+ - const: mediatek,mt8183-mmc
reg:
minItems: 1
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 07/15] dt-bindings: mmc: mtk-sd: add bindings for MT8365 SoC
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add MMC bindings for MT8365 bindings.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 6f8ecb4788eb8..36f9fce8f4795 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -35,6 +35,9 @@ properties:
- mediatek,mt8192-mmc
- mediatek,mt8195-mmc
- const: mediatek,mt8183-mmc
+ - items:
+ - const: mediatek,mt8365-mmc
+ - const: mediatek,mt8183-mmc
reg:
minItems: 1
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 08/15] dt-bindings: nvmem: mediatek,efuse: add MT8365 bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add bindings documentation for the efuse driver on MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
index 75e0a516e59a2..6893f2a6ea225 100644
--- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
+++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
@@ -34,6 +34,7 @@ properties:
- mediatek,mt8192-efuse
- mediatek,mt8195-efuse
- mediatek,mt8516-efuse
+ - mediatek,mt8365-efuse
- const: mediatek,efuse
- const: mediatek,mt8173-efuse
deprecated: true
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 08/15] dt-bindings: nvmem: mediatek,efuse: add MT8365 bindings
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
From: Fabien Parent <fparent@baylibre.com>
Add bindings documentation for the efuse driver on MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
index 75e0a516e59a2..6893f2a6ea225 100644
--- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
+++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
@@ -34,6 +34,7 @@ properties:
- mediatek,mt8192-efuse
- mediatek,mt8195-efuse
- mediatek,mt8516-efuse
+ - mediatek,mt8365-efuse
- const: mediatek,efuse
- const: mediatek,mt8173-efuse
deprecated: true
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 09/15] dt-bindings: mfd: syscon: Add mt8365-syscfg
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Document Mediatek mt8365-syscfg
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 4e4baf53796de..3d868e42e7bca 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -50,6 +50,7 @@ properties:
- marvell,armada-3700-usb2-host-misc
- mediatek,mt8135-pctl-a-syscfg
- mediatek,mt8135-pctl-b-syscfg
+ - mediatek,mt8365-syscfg
- microchip,lan966x-cpu-syscon
- microchip,sparx5-cpu-syscon
- mstar,msc313-pmsleep
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 09/15] dt-bindings: mfd: syscon: Add mt8365-syscfg
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Document Mediatek mt8365-syscfg
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/mfd/syscon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml
index 4e4baf53796de..3d868e42e7bca 100644
--- a/Documentation/devicetree/bindings/mfd/syscon.yaml
+++ b/Documentation/devicetree/bindings/mfd/syscon.yaml
@@ -50,6 +50,7 @@ properties:
- marvell,armada-3700-usb2-host-misc
- mediatek,mt8135-pctl-a-syscfg
- mediatek,mt8135-pctl-b-syscfg
+ - mediatek,mt8365-syscfg
- microchip,lan966x-cpu-syscon
- microchip,sparx5-cpu-syscon
- mstar,msc313-pmsleep
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 10/15] dt-bindings: timer: Add compatible for Mediatek MT8365
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add dt-binding documentation of timer for Mediatek MT8365 SoC
platform.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index 8bbb6e94508b2..c1f40aca2d48c 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -20,6 +20,7 @@ Required properties:
* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
+ * "mediatek,mt8365-timer" for MT8365 compatible timers (GPT)
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
For those SoCs that use SYST
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 10/15] dt-bindings: timer: Add compatible for Mediatek MT8365
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add dt-binding documentation of timer for Mediatek MT8365 SoC
platform.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
index 8bbb6e94508b2..c1f40aca2d48c 100644
--- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
@@ -20,6 +20,7 @@ Required properties:
* "mediatek,mt8135-timer" for MT8135 compatible timers (GPT)
* "mediatek,mt8173-timer" for MT8173 compatible timers (GPT)
* "mediatek,mt8516-timer" for MT8516 compatible timers (GPT)
+ * "mediatek,mt8365-timer" for MT8365 compatible timers (GPT)
* "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT)
For those SoCs that use SYST
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 11/15] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add devicetree bindings for Mediatek MT8365 pinctrl driver.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
.../pinctrl/mediatek,mt8365-pinctrl.yaml | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
new file mode 100644
index 0000000000000..bddff8c2fd382
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8365 Pin Controller
+
+maintainers:
+ - Bernhard Rosenkränzer <bero@baylibre.com>
+
+description: |+
+ The MediaTek's MT8365 Pin controller is used to control SoC pins.
+
+properties:
+ compatible:
+ const: mediatek,mt8365-pinctrl
+
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ interrupt-controller: true
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 2
+
+allOf:
+ - $ref: "pinctrl.yaml#"
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pio: pinctrl@1000b000 {
+ compatible = "mediatek,mt8365-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 11/15] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add devicetree bindings for Mediatek MT8365 pinctrl driver.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
.../pinctrl/mediatek,mt8365-pinctrl.yaml | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
new file mode 100644
index 0000000000000..bddff8c2fd382
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT8365 Pin Controller
+
+maintainers:
+ - Bernhard Rosenkränzer <bero@baylibre.com>
+
+description: |+
+ The MediaTek's MT8365 Pin controller is used to control SoC pins.
+
+properties:
+ compatible:
+ const: mediatek,mt8365-pinctrl
+
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ interrupt-controller: true
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 2
+
+allOf:
+ - $ref: "pinctrl.yaml#"
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pio: pinctrl@1000b000 {
+ compatible = "mediatek,mt8365-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 12/15] dt-bindings: soc: mediatek: pwrap: add compatible for mt8365
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add dt-binding documentation of pwrap for Mediatek MT8365
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
index d24e2bc444be3..eb6379487c910 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
@@ -31,6 +31,7 @@ Required properties in pwrap device node.
"mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs
"mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
+ "mediatek,mt8365-pwrap" for MT8365 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: "pwrap" is required; "pwrap-bridge" is optional.
"pwrap": Main registers base
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 12/15] dt-bindings: soc: mediatek: pwrap: add compatible for mt8365
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add dt-binding documentation of pwrap for Mediatek MT8365
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
index d24e2bc444be3..eb6379487c910 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
@@ -31,6 +31,7 @@ Required properties in pwrap device node.
"mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs
"mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
+ "mediatek,mt8365-pwrap" for MT8365 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: "pwrap" is required; "pwrap-bridge" is optional.
"pwrap": Main registers base
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 13/15] dt-bindings: irq: mtk, sysirq: add support for mt8365
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add binding documentation of mediatek,sysirq for mt8365 SoC.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
.../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 84ced3f4179b9..3ffc60184e445 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -25,6 +25,7 @@ Required properties:
"mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
+ "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- reg: Physical base address of the intpol registers and length of memory
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 13/15] dt-bindings: irq: mtk, sysirq: add support for mt8365
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add binding documentation of mediatek,sysirq for mt8365 SoC.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
.../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 84ced3f4179b9..3ffc60184e445 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -25,6 +25,7 @@ Required properties:
"mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
+ "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- reg: Physical base address of the intpol registers and length of memory
--
2.38.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 14/15] dt-bindings: thermal: mediatek: add documentation for MT8365 SoC
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add binding documentation for the Mediatek MT8365 SoC.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
index 5c7e7bdd029ab..d1b30733dfce3 100644
--- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
@@ -15,6 +15,7 @@ Required properties:
- "mediatek,mt7622-thermal" : For MT7622 SoC
- "mediatek,mt8183-thermal" : For MT8183 family of SoCs
- "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
+ - "mediatek,mt8365-thermal" : for MT8365 family of SoCs
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
- clocks, clock-names: Clocks needed for the thermal controller. required
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 14/15] dt-bindings: thermal: mediatek: add documentation for MT8365 SoC
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add binding documentation for the Mediatek MT8365 SoC.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
index 5c7e7bdd029ab..d1b30733dfce3 100644
--- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt
@@ -15,6 +15,7 @@ Required properties:
- "mediatek,mt7622-thermal" : For MT7622 SoC
- "mediatek,mt8183-thermal" : For MT8183 family of SoCs
- "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs
+ - "mediatek,mt8365-thermal" : for MT8365 family of SoCs
- reg: Address range of the thermal controller
- interrupts: IRQ for the thermal controller
- clocks, clock-names: Clocks needed for the thermal controller. required
--
2.38.1
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^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 15/15] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
-1 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add bindings for the Mediatek mt8365-evk board.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index d76ce4c3819db..6781fcdb9fe69 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -246,6 +246,10 @@ properties:
- enum:
- mediatek,mt8516-pumpkin
- const: mediatek,mt8516
+ - items:
+ - enum:
+ - mediatek,mt8365-evk
+ - const: mediatek, mt8365
additionalProperties: true
--
2.38.1
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v2 15/15] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board
@ 2022-11-15 2:54 ` Bernhard Rosenkränzer
0 siblings, 0 replies; 70+ messages in thread
From: Bernhard Rosenkränzer @ 2022-11-15 2:54 UTC (permalink / raw)
To: linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Add bindings for the Mediatek mt8365-evk board.
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
index d76ce4c3819db..6781fcdb9fe69 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
@@ -246,6 +246,10 @@ properties:
- enum:
- mediatek,mt8516-pumpkin
- const: mediatek,mt8516
+ - items:
+ - enum:
+ - mediatek,mt8365-evk
+ - const: mediatek, mt8365
additionalProperties: true
--
2.38.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:01 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 70+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-11-15 9:01 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Il 15/11/22 03:54, Bernhard Rosenkränzer ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Hello,
There's a mtk-wdt.txt schema conversion around that's well reviewed and that
will land before, if not at the same time, as your mt8365-evk series (judging
by the fact that you anyway have to send a v3...)
Can you please rebase this commit over [1]?
Thanks,
Angelo
[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=693051
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> index 762c62e428ef2..835af28b46de0 100644
> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> @@ -20,6 +20,7 @@ Required properties:
> "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> "mediatek,mt8192-wdt": for MT8192
> "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
> + "mediatek,mt8365-wdt", "mediatek,mt6589-wdt": for MT8365
>
> - reg : Specifies base physical address and size of the registers.
>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings
@ 2022-11-15 9:01 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 70+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-11-15 9:01 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Il 15/11/22 03:54, Bernhard Rosenkränzer ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Hello,
There's a mtk-wdt.txt schema conversion around that's well reviewed and that
will land before, if not at the same time, as your mt8365-evk series (judging
by the fact that you anyway have to send a v3...)
Can you please rebase this commit over [1]?
Thanks,
Angelo
[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=693051
> ---
> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> index 762c62e428ef2..835af28b46de0 100644
> --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
> @@ -20,6 +20,7 @@ Required properties:
> "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
> "mediatek,mt8192-wdt": for MT8192
> "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
> + "mediatek,mt8365-wdt", "mediatek,mt6589-wdt": for MT8365
>
> - reg : Specifies base physical address and size of the registers.
>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 03/15] dt-bindings: iio: adc: mediatek: add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:02 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 70+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-11-15 9:02 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Il 15/11/22 03:54, Bernhard Rosenkränzer ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding for the ADC present in MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
You're sending the patch, hence you have to add your signoff, which is missing.
Please add it.
Regards,
Angelo
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 03/15] dt-bindings: iio: adc: mediatek: add MT8365 SoC bindings
@ 2022-11-15 9:02 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 70+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-11-15 9:02 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Il 15/11/22 03:54, Bernhard Rosenkränzer ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding for the ADC present in MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
You're sending the patch, hence you have to add your signoff, which is missing.
Please add it.
Regards,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:23 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 70+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-11-15 9:23 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Il 15/11/22 03:54, Bernhard Rosenkränzer ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> This adds minimal support for the Mediatek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++
> 3 files changed, 946 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 0ec90cb3ef289..e668fd50a3326 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> new file mode 100644
> index 0000000000000..74e0f75231637
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021-2022 BayLibre, SAS.
> + * Authors:
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
> +#include "mt8365.dtsi"
> +
> +/ {
> + model = "MediaTek MT8365 Open Platform EVK";
> + compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + input-name = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio_keys>;
> +
> + key-volume-up {
> + gpios = <&pio 24 GPIO_ACTIVE_LOW>;
> + label = "volume_up";
> + linux,code = <KEY_VOLUMEUP>;
> + wakeup-source;
> + debounce-interval = <15>;
> + };
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0xc0000000>;
> + };
> +
> + usb_otg_vbus: regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 12 MiB reserved for OP-TEE (BL32)
> + * +-----------------------+ 0x43e0_0000
> + * | SHMEM 2MiB |
> + * +-----------------------+ 0x43c0_0000
> + * | | TA_RAM 8MiB |
> + * + TZDRAM +--------------+ 0x4340_0000
> + * | | TEE_RAM 2MiB |
> + * +-----------------------+ 0x4320_0000
> + */
> + optee_reserved: optee@43200000 {
> + no-map;
> + reg = <0 0x43200000 0 0x00c00000>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&pio {
> + dpi_func_pins: dpi-func-pins {
> + pins {
> + pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
> + <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
> + <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
> + <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
> + <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
> + <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
> + <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
> + <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
> + <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
> + <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
> + <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
> + <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
> + <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
> + <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
> + <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
> + <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
> + drive-strength = <MTK_DRIVE_4mA>;
> + };
> + };
> +
> + dpi_idle_pins: dpi-idle-pins {
> + pins {
> + pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
> + <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
> + <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
> + <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
> + <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
> + <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
> + <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
> + <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
> + <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
> + <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
> + <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
> + <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
> + <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
> + <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
> + <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
> + <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
> + };
> + };
> +
> + gpio_keys: gpio-keys-pins {
> + pins {
> + pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
> + bias-pull-up;
> + input-enable;
> + };
> + };
> +
> + i2c1_pins: i2c1-pins {
> + pins {
> + pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
> + <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
> + mediatek,pull-up-adv = <3>;
> + mediatek,drive-strength-adv = <00>;
> + bias-pull-up;
> + };
> + };
> +
> + ite_pins: ite-pins {
> + pins-rst-ite {
> + pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
> + output-high;
> + };
> +
> + pins-irq-ite {
> + pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
> + input-enable;
> + bias-pull-up;
> + };
> +
> + pins-pwr {
> + pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
> + <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
> + output-high;
> + };
> + };
> +
> + mmc0_pins_default: mmc0-default-pins {
> + pins-clk {
> + pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
> + bias-pull-down;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
> + <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
> + <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
> + <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
> + <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
> + <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
> + <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
> + <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
> + <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
> + input-enable;
> + bias-pull-up;
> + };
> +
> + pins-rst {
> + pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
> + bias-pull-up;
> + };
> + };
> +
> + mmc0_pins_uhs: mmc0-uhs-pins {
> + pins-clk {
> + pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
> + <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
> + <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
> + <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
> + <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
> + <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
> + <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
> + <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
> + <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
> + input-enable;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> + };
> +
> + pins-ds {
> + pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-rst {
> + pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-up;
> + };
> + };
> +
> + mmc1_pins_default: mmc1-default-pins {
> + pins-cd {
> + pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
> + bias-pull-up;
> + };
> +
> + pins-clk {
> + pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
> + <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
> + <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
> + <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
> + <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
> + input-enable;
> + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> + };
> + };
> +
> + mmc1_pins_uhs: mmc1-uhs-pins {
> + pins-clk {
> + pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
> + <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
> + <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
> + <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
> + <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
> + input-enable;
> + drive-strength = <MTK_DRIVE_6mA>;
> + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> + };
> + };
> +
> + uart0_pins: uart0-pins {
> + pins {
> + pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
> + <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
> + };
> + };
> +
> + uart1_pins: uart1-pins {
> + pins {
> + pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
> + <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
> + };
> + };
> +
> + uart2_pins: uart2-pins {
> + pins {
> + pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
> + <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
> + };
> + };
> +
> + usb_pins: usb-pins {
> + pins-id {
> + pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
> + input-enable;
> + bias-pull-up;
> + };
> +
> + pins-usb0-vbus {
> + pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
> + output-high;
> + };
> +
> + pin-usb1-vbus {
> + pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
> + output-high;
> + };
> + };
> +
> + pwm_pins: pwm-pins {
> + pins {
> + pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
> + <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
> + };
> + };
> +};
> +
> +&pwm {
> + pinctrl-0 = <&pwm_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-0 = <&uart1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-0 = <&uart2_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> new file mode 100644
> index 0000000000000..1cf2172081b20
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -0,0 +1,601 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * (C) 2018 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre SAS
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +#include <dt-bindings/clock/mediatek,mt8365-clk.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + compatible = "mediatek,mt8365";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0: cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + #cooling-cells = <2>;
I don't see any CPU caches and I'm totally sure that this SoC does have
a unified 512KB unified L2 cache.
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + #cooling-cells = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + #cooling-cells = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + #cooling-cells = <2>;
> + enable-method = "psci";
> + };
> + }; > +
> + clk26m: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
Does this SoC really not support any idle-state?! Seems pretty odd.
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
> + bl31_secmon_reserved: secmon@43000000 {
> + no-map;
> + reg = <0 0x43000000 0 0x20000>;
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x80000>,
> + <0 0x0c080000 0 0x80000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8365-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8365-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon@10003000 {
> + compatible = "mediatek,mt8365-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + syscfg_pctl: syscfg-pctl@10005000 {
> + compatible = "mediatek,mt8365-syscfg", "syscon";
> + reg = <0 0x10005000 0 0x1000>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8365-wdt",
> + "mediatek,mt6589-wdt";
83 cols is fine, fits in one line.
> + reg = <0 0x10007000 0 0x100>;
> + #reset-cells = <1>;
> + };
> +
> + gpt: apxgpt@10008000 {
This should be timer@10008000
> + compatible = "mediatek,mt8365-timer",
> + "mediatek,mt6577-timer";
> + reg = <0 0x10008000 0 0x1000>;
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SYS_26M_D2>;
> + clock-names = "clk13m";
> + };
> +
..snip..
> +
> + infracfg: infracfg@1020e000 {
> + compatible = "mediatek,mt8365-infracfg", "syscon";
> + reg = <0 0x1020e000 0 0x1000>;
> + };
> +
> + rng: rng@1020f000 {
> + compatible = "mediatek,mt8365-rng",
> + "mediatek,mt7623-rng";
Fits in one line.
> + reg = <0 0x1020f000 0 0x100>;
> + clocks = <&infracfg CLK_IFR_TRNG>;
> + clock-names = "rng";
> + };
> +
..snip..
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
85 cols is probably fine, so this should fit in one line.
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 0>, <&apdma 1>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
..snip..
> +
> + i2c0: i2c@11007000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
Fits in one line.
> + reg = <0 0x11007000 0 0xa0>,
> + <0 0x11000080 0 0x80>;
Same.
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C0_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@11008000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11008000 0 0xa0>,
> + <0 0x11000100 0 0x80>;
...again...
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C1_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@11009000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11009000 0 0xa0>,
> + <0 0x11000180 0 0x80>;
...and again...
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C2_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi: spi@1100a000 {
> + compatible = "mediatek,mt8365-spi",
> + "mediatek,mt7622-spi";
...and it's the same here again...
I'll stop saying the same at every instance, so please check the others :-)
> + reg = <0 0x1100a000 0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_IFR_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + status = "disabled";
> + };
> +
Regards,
Angelo
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support
@ 2022-11-15 9:23 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 70+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-11-15 9:23 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
Il 15/11/22 03:54, Bernhard Rosenkränzer ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> This adds minimal support for the Mediatek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++
> 3 files changed, 946 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 0ec90cb3ef289..e668fd50a3326 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> new file mode 100644
> index 0000000000000..74e0f75231637
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021-2022 BayLibre, SAS.
> + * Authors:
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
> +#include "mt8365.dtsi"
> +
> +/ {
> + model = "MediaTek MT8365 Open Platform EVK";
> + compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
> + firmware {
> + optee {
> + compatible = "linaro,optee-tz";
> + method = "smc";
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + input-name = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio_keys>;
> +
> + key-volume-up {
> + gpios = <&pio 24 GPIO_ACTIVE_LOW>;
> + label = "volume_up";
> + linux,code = <KEY_VOLUMEUP>;
> + wakeup-source;
> + debounce-interval = <15>;
> + };
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0 0x40000000 0 0xc0000000>;
> + };
> +
> + usb_otg_vbus: regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 12 MiB reserved for OP-TEE (BL32)
> + * +-----------------------+ 0x43e0_0000
> + * | SHMEM 2MiB |
> + * +-----------------------+ 0x43c0_0000
> + * | | TA_RAM 8MiB |
> + * + TZDRAM +--------------+ 0x4340_0000
> + * | | TEE_RAM 2MiB |
> + * +-----------------------+ 0x4320_0000
> + */
> + optee_reserved: optee@43200000 {
> + no-map;
> + reg = <0 0x43200000 0 0x00c00000>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins>;
> + clock-frequency = <100000>;
> + status = "okay";
> +};
> +
> +&pio {
> + dpi_func_pins: dpi-func-pins {
> + pins {
> + pinmux = <MT8365_PIN_0_GPIO0__FUNC_DPI_D0>,
> + <MT8365_PIN_1_GPIO1__FUNC_DPI_D1>,
> + <MT8365_PIN_2_GPIO2__FUNC_DPI_D2>,
> + <MT8365_PIN_3_GPIO3__FUNC_DPI_D3>,
> + <MT8365_PIN_4_GPIO4__FUNC_DPI_D4>,
> + <MT8365_PIN_5_GPIO5__FUNC_DPI_D5>,
> + <MT8365_PIN_6_GPIO6__FUNC_DPI_D6>,
> + <MT8365_PIN_7_GPIO7__FUNC_DPI_D7>,
> + <MT8365_PIN_8_GPIO8__FUNC_DPI_D8>,
> + <MT8365_PIN_9_GPIO9__FUNC_DPI_D9>,
> + <MT8365_PIN_10_GPIO10__FUNC_DPI_D10>,
> + <MT8365_PIN_11_GPIO11__FUNC_DPI_D11>,
> + <MT8365_PIN_12_GPIO12__FUNC_DPI_DE>,
> + <MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC>,
> + <MT8365_PIN_14_GPIO14__FUNC_DPI_CK>,
> + <MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC>;
> + drive-strength = <MTK_DRIVE_4mA>;
> + };
> + };
> +
> + dpi_idle_pins: dpi-idle-pins {
> + pins {
> + pinmux = <MT8365_PIN_0_GPIO0__FUNC_GPIO0>,
> + <MT8365_PIN_1_GPIO1__FUNC_GPIO1>,
> + <MT8365_PIN_2_GPIO2__FUNC_GPIO2>,
> + <MT8365_PIN_3_GPIO3__FUNC_GPIO3>,
> + <MT8365_PIN_4_GPIO4__FUNC_GPIO4>,
> + <MT8365_PIN_5_GPIO5__FUNC_GPIO5>,
> + <MT8365_PIN_6_GPIO6__FUNC_GPIO6>,
> + <MT8365_PIN_7_GPIO7__FUNC_GPIO7>,
> + <MT8365_PIN_8_GPIO8__FUNC_GPIO8>,
> + <MT8365_PIN_9_GPIO9__FUNC_GPIO9>,
> + <MT8365_PIN_10_GPIO10__FUNC_GPIO10>,
> + <MT8365_PIN_11_GPIO11__FUNC_GPIO11>,
> + <MT8365_PIN_12_GPIO12__FUNC_GPIO12>,
> + <MT8365_PIN_13_GPIO13__FUNC_GPIO13>,
> + <MT8365_PIN_14_GPIO14__FUNC_GPIO14>,
> + <MT8365_PIN_15_GPIO15__FUNC_GPIO15>;
> + };
> + };
> +
> + gpio_keys: gpio-keys-pins {
> + pins {
> + pinmux = <MT8365_PIN_24_KPCOL0__FUNC_KPCOL0>;
> + bias-pull-up;
> + input-enable;
> + };
> + };
> +
> + i2c1_pins: i2c1-pins {
> + pins {
> + pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>,
> + <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
> + mediatek,pull-up-adv = <3>;
> + mediatek,drive-strength-adv = <00>;
> + bias-pull-up;
> + };
> + };
> +
> + ite_pins: ite-pins {
> + pins-rst-ite {
> + pinmux = <MT8365_PIN_69_CMDAT1__FUNC_GPIO69>;
> + output-high;
> + };
> +
> + pins-irq-ite {
> + pinmux = <MT8365_PIN_68_CMDAT0__FUNC_GPIO68>;
> + input-enable;
> + bias-pull-up;
> + };
> +
> + pins-pwr {
> + pinmux = <MT8365_PIN_70_CMDAT2__FUNC_GPIO70>,
> + <MT8365_PIN_71_CMDAT3__FUNC_GPIO71>;
> + output-high;
> + };
> + };
> +
> + mmc0_pins_default: mmc0-default-pins {
> + pins-clk {
> + pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
> + bias-pull-down;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
> + <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
> + <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
> + <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
> + <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
> + <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
> + <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
> + <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
> + <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
> + input-enable;
> + bias-pull-up;
> + };
> +
> + pins-rst {
> + pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
> + bias-pull-up;
> + };
> + };
> +
> + mmc0_pins_uhs: mmc0-uhs-pins {
> + pins-clk {
> + pinmux = <MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK>;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0>,
> + <MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1>,
> + <MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2>,
> + <MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3>,
> + <MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4>,
> + <MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5>,
> + <MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6>,
> + <MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7>,
> + <MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD>;
> + input-enable;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> + };
> +
> + pins-ds {
> + pinmux = <MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL>;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-rst {
> + pinmux = <MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB>;
> + drive-strength = <MTK_DRIVE_10mA>;
> + bias-pull-up;
> + };
> + };
> +
> + mmc1_pins_default: mmc1-default-pins {
> + pins-cd {
> + pinmux = <MT8365_PIN_76_CMDAT8__FUNC_GPIO76>;
> + bias-pull-up;
> + };
> +
> + pins-clk {
> + pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
> + <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
> + <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
> + <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
> + <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
> + input-enable;
> + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> + };
> + };
> +
> + mmc1_pins_uhs: mmc1-uhs-pins {
> + pins-clk {
> + pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>;
> + drive-strength = <MTK_DRIVE_8mA>;
> + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
> + };
> +
> + pins-cmd-dat {
> + pinmux = <MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0>,
> + <MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1>,
> + <MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2>,
> + <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>,
> + <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>;
> + input-enable;
> + drive-strength = <MTK_DRIVE_6mA>;
> + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
> + };
> + };
> +
> + uart0_pins: uart0-pins {
> + pins {
> + pinmux = <MT8365_PIN_35_URXD0__FUNC_URXD0>,
> + <MT8365_PIN_36_UTXD0__FUNC_UTXD0>;
> + };
> + };
> +
> + uart1_pins: uart1-pins {
> + pins {
> + pinmux = <MT8365_PIN_37_URXD1__FUNC_URXD1>,
> + <MT8365_PIN_38_UTXD1__FUNC_UTXD1>;
> + };
> + };
> +
> + uart2_pins: uart2-pins {
> + pins {
> + pinmux = <MT8365_PIN_39_URXD2__FUNC_URXD2>,
> + <MT8365_PIN_40_UTXD2__FUNC_UTXD2>;
> + };
> + };
> +
> + usb_pins: usb-pins {
> + pins-id {
> + pinmux = <MT8365_PIN_17_GPIO17__FUNC_GPIO17>;
> + input-enable;
> + bias-pull-up;
> + };
> +
> + pins-usb0-vbus {
> + pinmux = <MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS>;
> + output-high;
> + };
> +
> + pin-usb1-vbus {
> + pinmux = <MT8365_PIN_18_GPIO18__FUNC_GPIO18>;
> + output-high;
> + };
> + };
> +
> + pwm_pins: pwm-pins {
> + pins {
> + pinmux = <MT8365_PIN_19_DISP_PWM__FUNC_PWM_A>,
> + <MT8365_PIN_116_I2S_BCK__FUNC_PWM_C>;
> + };
> + };
> +};
> +
> +&pwm {
> + pinctrl-0 = <&pwm_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-0 = <&uart1_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-0 = <&uart2_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> new file mode 100644
> index 0000000000000..1cf2172081b20
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi
> @@ -0,0 +1,601 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * (C) 2018 MediaTek Inc.
> + * Copyright (C) 2022 BayLibre SAS
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +#include <dt-bindings/clock/mediatek,mt8365-clk.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + compatible = "mediatek,mt8365";
> + interrupt-parent = <&sysirq>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0: cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + core2 {
> + cpu = <&cpu2>;
> + };
> + core3 {
> + cpu = <&cpu3>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + #cooling-cells = <2>;
I don't see any CPU caches and I'm totally sure that this SoC does have
a unified 512KB unified L2 cache.
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x1>;
> + #cooling-cells = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x2>;
> + #cooling-cells = <2>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x3>;
> + #cooling-cells = <2>;
> + enable-method = "psci";
> + };
> + }; > +
> + clk26m: oscillator {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
Does this SoC really not support any idle-state?! Seems pretty odd.
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */
> + bl31_secmon_reserved: secmon@43000000 {
> + no-map;
> + reg = <0 0x43000000 0 0x20000>;
> + };
> + };
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x80000>,
> + <0 0x0c080000 0 0x80000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8365-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8365-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon@10003000 {
> + compatible = "mediatek,mt8365-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + syscfg_pctl: syscfg-pctl@10005000 {
> + compatible = "mediatek,mt8365-syscfg", "syscon";
> + reg = <0 0x10005000 0 0x1000>;
> + };
> +
> + watchdog: watchdog@10007000 {
> + compatible = "mediatek,mt8365-wdt",
> + "mediatek,mt6589-wdt";
83 cols is fine, fits in one line.
> + reg = <0 0x10007000 0 0x100>;
> + #reset-cells = <1>;
> + };
> +
> + gpt: apxgpt@10008000 {
This should be timer@10008000
> + compatible = "mediatek,mt8365-timer",
> + "mediatek,mt6577-timer";
> + reg = <0 0x10008000 0 0x1000>;
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_SYS_26M_D2>;
> + clock-names = "clk13m";
> + };
> +
..snip..
> +
> + infracfg: infracfg@1020e000 {
> + compatible = "mediatek,mt8365-infracfg", "syscon";
> + reg = <0 0x1020e000 0 0x1000>;
> + };
> +
> + rng: rng@1020f000 {
> + compatible = "mediatek,mt8365-rng",
> + "mediatek,mt7623-rng";
Fits in one line.
> + reg = <0 0x1020f000 0 0x100>;
> + clocks = <&infracfg CLK_IFR_TRNG>;
> + clock-names = "rng";
> + };
> +
..snip..
> +
> + uart0: serial@11002000 {
> + compatible = "mediatek,mt8365-uart",
> + "mediatek,mt6577-uart";
85 cols is probably fine, so this should fit in one line.
> + reg = <0 0x11002000 0 0x1000>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
> + clock-names = "baud", "bus";
> + dmas = <&apdma 0>, <&apdma 1>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +
..snip..
> +
> + i2c0: i2c@11007000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
Fits in one line.
> + reg = <0 0x11007000 0 0xa0>,
> + <0 0x11000080 0 0x80>;
Same.
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C0_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@11008000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11008000 0 0xa0>,
> + <0 0x11000100 0 0x80>;
...again...
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C1_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@11009000 {
> + compatible = "mediatek,mt8365-i2c",
> + "mediatek,mt8168-i2c";
> + reg = <0 0x11009000 0 0xa0>,
> + <0 0x11000180 0 0x80>;
...and again...
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
> + clock-div = <1>;
> + clocks = <&infracfg CLK_IFR_I2C2_AXI>,
> + <&infracfg CLK_IFR_AP_DMA>;
> + clock-names = "main", "dma";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + spi: spi@1100a000 {
> + compatible = "mediatek,mt8365-spi",
> + "mediatek,mt7622-spi";
...and it's the same here again...
I'll stop saying the same at every instance, so please check the others :-)
> + reg = <0 0x1100a000 0 0x100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_IFR_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + status = "disabled";
> + };
> +
Regards,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:41 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:41 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> This adds minimal support for the Mediatek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++
> 3 files changed, 946 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 0ec90cb3ef289..e668fd50a3326 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> new file mode 100644
> index 0000000000000..74e0f75231637
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021-2022 BayLibre, SAS.
> + * Authors:
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
> +#include "mt8365.dtsi"
> +
> +/ {
> + model = "MediaTek MT8365 Open Platform EVK";
> + compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
Missing bindings.
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
(...)
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x80000>,
> + <0 0x0c080000 0 0x80000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8365-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8365-infracfg", "syscon";
Missing bindings.
Did you order your patches in logical order?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support
@ 2022-11-15 9:41 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:41 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> This adds minimal support for the Mediatek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/Makefile | 1 +
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++
> arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++
> 3 files changed, 946 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
> index 0ec90cb3ef289..e668fd50a3326 100644
> --- a/arch/arm64/boot/dts/mediatek/Makefile
> +++ b/arch/arm64/boot/dts/mediatek/Makefile
> @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb
> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> new file mode 100644
> index 0000000000000..74e0f75231637
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021-2022 BayLibre, SAS.
> + * Authors:
> + * Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
> +#include "mt8365.dtsi"
> +
> +/ {
> + model = "MediaTek MT8365 Open Platform EVK";
> + compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
Missing bindings.
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:921600n8";
> + };
> +
(...)
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x80000>,
> + <0 0x0c080000 0 0x80000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
> +
> + topckgen: syscon@10000000 {
> + compatible = "mediatek,mt8365-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon@10001000 {
> + compatible = "mediatek,mt8365-infracfg", "syscon";
Missing bindings.
Did you order your patches in logical order?
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:42 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:42 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
Drop second, redundant "bindings" from subject.
With that:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 02/15] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings
@ 2022-11-15 9:42 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:42 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
Drop second, redundant "bindings" from subject.
With that:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 03/15] dt-bindings: iio: adc: mediatek: add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:42 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:42 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding for the ADC present in MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Drop second, redundant "bindings" from subject.
> ---
> .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> index 7f79a06e76f59..ed582c6e7ea9c 100644
> --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> @@ -38,6 +38,7 @@ properties:
> - mediatek,mt8188-auxadc
> - mediatek,mt8195-auxadc
> - mediatek,mt8516-auxadc
> + - mediatek,mt8365-auxadc
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 03/15] dt-bindings: iio: adc: mediatek: add MT8365 SoC bindings
@ 2022-11-15 9:42 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:42 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding for the ADC present in MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Drop second, redundant "bindings" from subject.
> ---
> .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> index 7f79a06e76f59..ed582c6e7ea9c 100644
> --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml
> @@ -38,6 +38,7 @@ properties:
> - mediatek,mt8188-auxadc
> - mediatek,mt8195-auxadc
> - mediatek,mt8516-auxadc
> + - mediatek,mt8365-auxadc
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 05/15] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:43 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:43 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
1. Drop second, redundant "bindings" from subject.
2. This is a friendly reminder during the review process.
It looks like you received a tag and forgot to add it.
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions. However, there's no need to repost patches *only* to add the
tags. The upstream maintainer will do that for acks received on the
version they apply.
https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540
If a tag was not added on purpose, please state why and what changed.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 05/15] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings
@ 2022-11-15 9:43 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:43 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
1. Drop second, redundant "bindings" from subject.
2. This is a friendly reminder during the review process.
It looks like you received a tag and forgot to add it.
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions. However, there's no need to repost patches *only* to add the
tags. The upstream maintainer will do that for acks received on the
version they apply.
https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540
If a tag was not added on purpose, please state why and what changed.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 06/15] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:44 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:44 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
>
This is a friendly reminder during the review process.
It looks like you received a tag and forgot to add it.
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions. However, there's no need to repost patches *only* to add the
tags. The upstream maintainer will do that for acks received on the
version they apply.
https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540
If a tag was not added on purpose, please state why and what changed.
Also:
Drop second, redundant "bindings" from subject.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 06/15] dt-bindings: usb: mediatek,mtk-xhci: add MT8365 SoC bindings
@ 2022-11-15 9:44 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:44 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add binding documentation for the MT8365 SoC.
>
This is a friendly reminder during the review process.
It looks like you received a tag and forgot to add it.
If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new
versions. However, there's no need to repost patches *only* to add the
tags. The upstream maintainer will do that for acks received on the
version they apply.
https://elixir.bootlin.com/linux/v5.17/source/Documentation/process/submitting-patches.rst#L540
If a tag was not added on purpose, please state why and what changed.
Also:
Drop second, redundant "bindings" from subject.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 07/15] dt-bindings: mmc: mtk-sd: add bindings for MT8365 SoC
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:44 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:44 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add MMC bindings for MT8365 bindings.
Drop second, redundant "bindings" from subject.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 6f8ecb4788eb8..36f9fce8f4795 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -35,6 +35,9 @@ properties:
> - mediatek,mt8192-mmc
> - mediatek,mt8195-mmc
> - const: mediatek,mt8183-mmc
> + - items:
> + - const: mediatek,mt8365-mmc
> + - const: mediatek,mt8183-mmc
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 07/15] dt-bindings: mmc: mtk-sd: add bindings for MT8365 SoC
@ 2022-11-15 9:44 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:44 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add MMC bindings for MT8365 bindings.
Drop second, redundant "bindings" from subject.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 6f8ecb4788eb8..36f9fce8f4795 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -35,6 +35,9 @@ properties:
> - mediatek,mt8192-mmc
> - mediatek,mt8195-mmc
> - const: mediatek,mt8183-mmc
> + - items:
> + - const: mediatek,mt8365-mmc
> + - const: mediatek,mt8183-mmc
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
Thank you.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 08/15] dt-bindings: nvmem: mediatek,efuse: add MT8365 bindings
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:45 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:45 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add bindings documentation for the efuse driver on MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> index 75e0a516e59a2..6893f2a6ea225 100644
> --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> @@ -34,6 +34,7 @@ properties:
> - mediatek,mt8192-efuse
> - mediatek,mt8195-efuse
> - mediatek,mt8516-efuse
> + - mediatek,mt8365-efuse
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
So you ignored all my comments... awesome.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 08/15] dt-bindings: nvmem: mediatek,efuse: add MT8365 bindings
@ 2022-11-15 9:45 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:45 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add bindings documentation for the efuse driver on MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> index 75e0a516e59a2..6893f2a6ea225 100644
> --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml
> @@ -34,6 +34,7 @@ properties:
> - mediatek,mt8192-efuse
> - mediatek,mt8195-efuse
> - mediatek,mt8516-efuse
> + - mediatek,mt8365-efuse
This is a friendly reminder during the review process.
It seems my previous comments were not fully addressed. Maybe my
feedback got lost between the quotes, maybe you just forgot to apply it.
Please go back to the previous discussion and either implement all
requested changes or keep discussing them.
So you ignored all my comments... awesome.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 09/15] dt-bindings: mfd: syscon: Add mt8365-syscfg
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:45 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:45 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Document Mediatek mt8365-syscfg
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 09/15] dt-bindings: mfd: syscon: Add mt8365-syscfg
@ 2022-11-15 9:45 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:45 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Document Mediatek mt8365-syscfg
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 10/15] dt-bindings: timer: Add compatible for Mediatek MT8365
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:46 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:46 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add dt-binding documentation of timer for Mediatek MT8365 SoC
> platform.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 10/15] dt-bindings: timer: Add compatible for Mediatek MT8365
@ 2022-11-15 9:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:46 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add dt-binding documentation of timer for Mediatek MT8365 SoC
> platform.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 11/15] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:46 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:46 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add devicetree bindings for Mediatek MT8365 pinctrl driver.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> .../pinctrl/mediatek,mt8365-pinctrl.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
> new file mode 100644
> index 0000000000000..bddff8c2fd382
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT8365 Pin Controller
> +
> +maintainers:
> + - Bernhard Rosenkränzer <bero@baylibre.com>
> +
> +description: |+
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 11/15] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC
@ 2022-11-15 9:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:46 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add devicetree bindings for Mediatek MT8365 pinctrl driver.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> .../pinctrl/mediatek,mt8365-pinctrl.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
> new file mode 100644
> index 0000000000000..bddff8c2fd382
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT8365 Pin Controller
> +
> +maintainers:
> + - Bernhard Rosenkränzer <bero@baylibre.com>
> +
> +description: |+
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 12/15] dt-bindings: soc: mediatek: pwrap: add compatible for mt8365
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:46 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:46 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add dt-binding documentation of pwrap for Mediatek MT8365
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 12/15] dt-bindings: soc: mediatek: pwrap: add compatible for mt8365
@ 2022-11-15 9:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:46 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add dt-binding documentation of pwrap for Mediatek MT8365
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
I am not going to review this - please go through comments you received.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 15/15] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 9:47 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:47 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add bindings for the Mediatek mt8365-evk board.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
You document a patch after using a compatible - that's broken order.
> ---
> Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
> index d76ce4c3819db..6781fcdb9fe69 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
> @@ -246,6 +246,10 @@ properties:
> - enum:
> - mediatek,mt8516-pumpkin
> - const: mediatek,mt8516
> + - items:
> + - enum:
> + - mediatek,mt8365-evk
> + - const: mediatek, mt8365
No spaces in compatibles.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 15/15] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board
@ 2022-11-15 9:47 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 9:47 UTC (permalink / raw)
To: Bernhard Rosenkränzer, linux-mediatek
Cc: linux-arm-kernel, linux-kernel, devicetree, robh+dt,
krzysztof.kozlowski+dt, matthias.bgg
On 15/11/2022 03:54, Bernhard Rosenkränzer wrote:
> Add bindings for the Mediatek mt8365-evk board.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
You document a patch after using a compatible - that's broken order.
> ---
> Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml
> index d76ce4c3819db..6781fcdb9fe69 100644
> --- a/Documentation/devicetree/bindings/arm/mediatek.yaml
> +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml
> @@ -246,6 +246,10 @@ properties:
> - enum:
> - mediatek,mt8516-pumpkin
> - const: mediatek,mt8516
> + - items:
> + - enum:
> + - mediatek,mt8365-evk
> + - const: mediatek, mt8365
No spaces in compatibles.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 00/15] Initial Mediatek MT8365 SOC and MT8365-EVK board support
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 13:50 ` Rob Herring
-1 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2022-11-15 13:50 UTC (permalink / raw)
To: Bernhard Rosenkränzer
Cc: linux-mediatek, linux-arm-kernel, linux-kernel, devicetree,
krzysztof.kozlowski+dt, matthias.bgg
On Tue, Nov 15, 2022 at 03:54:06AM +0100, Bernhard Rosenkränzer wrote:
> This adds minimal support for the MediaTek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> v2:
> - Add missing dt-bindings documentation
> - Small cleanups addressing issues in v1 pointed out by Krzysztof Kozlowski
Other than this email, your patches are missing Content-Type headers yet
are UTF-8 encoded. Looks like they've been edited in mutt as there are
some mutt headers.
Rob
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 00/15] Initial Mediatek MT8365 SOC and MT8365-EVK board support
@ 2022-11-15 13:50 ` Rob Herring
0 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2022-11-15 13:50 UTC (permalink / raw)
To: Bernhard Rosenkränzer
Cc: linux-mediatek, linux-arm-kernel, linux-kernel, devicetree,
krzysztof.kozlowski+dt, matthias.bgg
On Tue, Nov 15, 2022 at 03:54:06AM +0100, Bernhard Rosenkränzer wrote:
> This adds minimal support for the MediaTek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> GPIO keys are supported, MMC is partially supported (needs the clocks
> driver for full support).
>
> v2:
> - Add missing dt-bindings documentation
> - Small cleanups addressing issues in v1 pointed out by Krzysztof Kozlowski
Other than this email, your patches are missing Content-Type headers yet
are UTF-8 encoded. Looks like they've been edited in mutt as there are
some mutt headers.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 11/15] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC
2022-11-15 2:54 ` Bernhard Rosenkränzer
@ 2022-11-15 14:11 ` Rob Herring
-1 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2022-11-15 14:11 UTC (permalink / raw)
To: Bernhard Rosenkränzer
Cc: krzysztof.kozlowski+dt, devicetree, linux-mediatek, matthias.bgg,
robh+dt, linux-arm-kernel, linux-kernel
On Tue, 15 Nov 2022 03:54:17 +0100, Bernhard Rosenkränzer wrote:
> Add devicetree bindings for Mediatek MT8365 pinctrl driver.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> .../pinctrl/mediatek,mt8365-pinctrl.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml: properties:reg: 'anyOf' conditional failed, one must be fixed:
'minItems' is not one of ['maxItems', 'description', 'deprecated']
hint: Only "maxItems" is required for a single entry if there are no constraints defined for the values.
'minItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf']
'maxItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf']
1 is less than the minimum of 2
hint: Arrays must be described with a combination of minItems/maxItems/items
hint: cell array properties must define how many entries and what the entries are when there is more than one entry.
from schema $id: http://devicetree.org/meta-schemas/core.yaml#
Error: Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.example.dts:34.29-30 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:406: Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1492: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v2 11/15] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC
@ 2022-11-15 14:11 ` Rob Herring
0 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2022-11-15 14:11 UTC (permalink / raw)
To: Bernhard Rosenkränzer
Cc: krzysztof.kozlowski+dt, devicetree, linux-mediatek, matthias.bgg,
robh+dt, linux-arm-kernel, linux-kernel
On Tue, 15 Nov 2022 03:54:17 +0100, Bernhard Rosenkränzer wrote:
> Add devicetree bindings for Mediatek MT8365 pinctrl driver.
>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> .../pinctrl/mediatek,mt8365-pinctrl.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml: properties:reg: 'anyOf' conditional failed, one must be fixed:
'minItems' is not one of ['maxItems', 'description', 'deprecated']
hint: Only "maxItems" is required for a single entry if there are no constraints defined for the values.
'minItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf']
'maxItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf']
1 is less than the minimum of 2
hint: Arrays must be described with a combination of minItems/maxItems/items
hint: cell array properties must define how many entries and what the entries are when there is more than one entry.
from schema $id: http://devicetree.org/meta-schemas/core.yaml#
Error: Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.example.dts:34.29-30 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:406: Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1492: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
end of thread, other threads:[~2022-11-15 14:12 UTC | newest]
Thread overview: 70+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-07 21:10 [PATCH] arm64: dts: mediatek: Initial mt8365-evk support Bernhard Rosenkränzer
2022-11-07 21:10 ` Bernhard Rosenkränzer
2022-11-08 10:02 ` Krzysztof Kozlowski
2022-11-08 10:02 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 00/15] Initial Mediatek MT8365 SOC and MT8365-EVK board support Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 2:54 ` [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:23 ` AngeloGioacchino Del Regno
2022-11-15 9:23 ` AngeloGioacchino Del Regno
2022-11-15 9:41 ` Krzysztof Kozlowski
2022-11-15 9:41 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 02/15] dt-bindings: watchdog: mtk-wdt: Add MT8365 SoC bindings Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:01 ` AngeloGioacchino Del Regno
2022-11-15 9:01 ` AngeloGioacchino Del Regno
2022-11-15 9:42 ` Krzysztof Kozlowski
2022-11-15 9:42 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 03/15] dt-bindings: iio: adc: mediatek: add " Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:02 ` AngeloGioacchino Del Regno
2022-11-15 9:02 ` AngeloGioacchino Del Regno
2022-11-15 9:42 ` Krzysztof Kozlowski
2022-11-15 9:42 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 04/15] dt-bindings: i2c: i2c-mt65xx: add binding for MT8365 SoC Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 2:54 ` [PATCH v2 05/15] dt-bindings: usb: mediatek,mtu3: add MT8365 SoC bindings Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:43 ` Krzysztof Kozlowski
2022-11-15 9:43 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 06/15] dt-bindings: usb: mediatek,mtk-xhci: " Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:44 ` Krzysztof Kozlowski
2022-11-15 9:44 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 07/15] dt-bindings: mmc: mtk-sd: add bindings for MT8365 SoC Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:44 ` Krzysztof Kozlowski
2022-11-15 9:44 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 08/15] dt-bindings: nvmem: mediatek,efuse: add MT8365 bindings Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:45 ` Krzysztof Kozlowski
2022-11-15 9:45 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 09/15] dt-bindings: mfd: syscon: Add mt8365-syscfg Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:45 ` Krzysztof Kozlowski
2022-11-15 9:45 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 10/15] dt-bindings: timer: Add compatible for Mediatek MT8365 Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:46 ` Krzysztof Kozlowski
2022-11-15 9:46 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 11/15] dt-bindings: pinctrl: add bindings for Mediatek MT8365 SoC Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:46 ` Krzysztof Kozlowski
2022-11-15 9:46 ` Krzysztof Kozlowski
2022-11-15 14:11 ` Rob Herring
2022-11-15 14:11 ` Rob Herring
2022-11-15 2:54 ` [PATCH v2 12/15] dt-bindings: soc: mediatek: pwrap: add compatible for mt8365 Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:46 ` Krzysztof Kozlowski
2022-11-15 9:46 ` Krzysztof Kozlowski
2022-11-15 2:54 ` [PATCH v2 13/15] dt-bindings: irq: mtk, sysirq: add support " Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 2:54 ` [PATCH v2 14/15] dt-bindings: thermal: mediatek: add documentation for MT8365 SoC Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 2:54 ` [PATCH v2 15/15] dt-bindings: arm64: dts: mediatek: Add mt8365-evk board Bernhard Rosenkränzer
2022-11-15 2:54 ` Bernhard Rosenkränzer
2022-11-15 9:47 ` Krzysztof Kozlowski
2022-11-15 9:47 ` Krzysztof Kozlowski
2022-11-15 13:50 ` [PATCH v2 00/15] Initial Mediatek MT8365 SOC and MT8365-EVK board support Rob Herring
2022-11-15 13:50 ` Rob Herring
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