[Qemu-devel] [PATCH v1 0/2] target/microblaze: Add properties to enable exceptions on failed bus accesses

[Qemu-devel] [PATCH v1 0/2] target/microblaze: Add properties to enable exceptions on failed bus accesses

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

This adds the necessary properties to MicroBlaze cores to enable exceptions
on failed bus accesses. There's no board that acutally uses this yet.

This also adds an unimplemented device to the s3adsp1800 board since I used
that board to test this feature. The s3adsp1800 does not enable the exceptions
by default though, so they remain off.

Cheers,
Edgar

Edgar E. Iglesias (2):
  hw/microblaze: s3adsp1800: Create an unimplemented GPIO area
  target/microblaze: Add props enabling exceptions on failed bus
    accesses

 hw/microblaze/petalogix_s3adsp1800_mmu.c |  4 ++++
 target/microblaze/cpu.c                  | 12 +++++++++++-
 target/microblaze/cpu.h                  |  2 ++
 3 files changed, 17 insertions(+), 1 deletion(-)

-- 
2.17.1

[Qemu-devel] [PATCH v1 2/2] target/microblaze: Add props enabling exceptions on failed bus accesses

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add MicroBlaze CPU properties to enable exceptions on failed
bus accesses.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/cpu.c | 12 +++++++++++-
 target/microblaze/cpu.h |  2 ++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 49876b19b3..5596cd5485 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -202,7 +202,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
                         (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
                         (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
-                        (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0);
+                        (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
+                        (cpu->cfg.dopb_bus_exception ?
+                                                 PVR2_DOPB_BUS_EXC_MASK : 0) |
+                        (cpu->cfg.iopb_bus_exception ?
+                                                 PVR2_IOPB_BUS_EXC_MASK : 0);
 
     env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
                                         PVR5_DCACHE_WRITEBACK_MASK : 0;
@@ -265,6 +269,12 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
+    /* Enables bus exceptions on failed data accesses (load/stores).  */
+    DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
+                     cfg.dopb_bus_exception, false),
+    /* Enables bus exceptions on failed instruction fetches.  */
+    DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
+                     cfg.iopb_bus_exception, false),
     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
     DEFINE_PROP_END_OF_LIST(),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 03ca91007d..792bbc97c7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -308,6 +308,8 @@ struct MicroBlazeCPU {
         bool use_mmu;
         bool dcache_writeback;
         bool endi;
+        bool dopb_bus_exception;
+        bool iopb_bus_exception;
         char *version;
         uint8_t pvr;
     } cfg;
-- 
2.17.1

Re: [Qemu-devel] [PATCH v1 2/2] target/microblaze: Add props enabling exceptions on failed bus accesses

[Alistair Francis]

On Fri, Jan 4, 2019 at 6:28 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add MicroBlaze CPU properties to enable exceptions on failed
> bus accesses.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/microblaze/cpu.c | 12 +++++++++++-
>  target/microblaze/cpu.h |  2 ++
>  2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 49876b19b3..5596cd5485 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -202,7 +202,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
>                          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
>                          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
> -                        (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0);
> +                        (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
> +                        (cpu->cfg.dopb_bus_exception ?
> +                                                 PVR2_DOPB_BUS_EXC_MASK : 0) |
> +                        (cpu->cfg.iopb_bus_exception ?
> +                                                 PVR2_IOPB_BUS_EXC_MASK : 0);
>
>      env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
>                                          PVR5_DCACHE_WRITEBACK_MASK : 0;
> @@ -265,6 +269,12 @@ static Property mb_properties[] = {
>      DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
>                       false),
>      DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
> +    /* Enables bus exceptions on failed data accesses (load/stores).  */
> +    DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
> +                     cfg.dopb_bus_exception, false),
> +    /* Enables bus exceptions on failed instruction fetches.  */
> +    DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
> +                     cfg.iopb_bus_exception, false),
>      DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
>      DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
>      DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 03ca91007d..792bbc97c7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -308,6 +308,8 @@ struct MicroBlazeCPU {
>          bool use_mmu;
>          bool dcache_writeback;
>          bool endi;
> +        bool dopb_bus_exception;
> +        bool iopb_bus_exception;
>          char *version;
>          uint8_t pvr;
>      } cfg;
> --
> 2.17.1
>
>

Re: [Qemu-devel] [PATCH v1 1/2] hw/microblaze: s3adsp1800: Create an unimplemented GPIO area

[Luc Michel]

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On 1/4/19 3:28 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Create an unimplemented GPIO area instead of leaving it unassigned.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  hw/microblaze/petalogix_s3adsp1800_mmu.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c
> index 5cf7b84c79..b9f0b0d06e 100644
> --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c
> +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c
> @@ -35,6 +35,7 @@
>  #include "sysemu/sysemu.h"
>  #include "hw/devices.h"
>  #include "hw/boards.h"
> +#include "hw/misc/unimp.h"
>  #include "exec/address-spaces.h"
>  #include "hw/char/xilinx_uartlite.h"
>  
> @@ -47,6 +48,7 @@
>  
>  #define MEMORY_BASEADDR 0x90000000
>  #define FLASH_BASEADDR 0xa0000000
> +#define GPIO_BASEADDR 0x81400000
>  #define INTC_BASEADDR 0x81800000
>  #define TIMER_BASEADDR 0x83c00000
>  #define UARTLITE_BASEADDR 0x84000000
> @@ -122,6 +124,8 @@ petalogix_s3adsp1800_init(MachineState *machine)
>      sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
>      sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
>  
> +    create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
> +
>      microblaze_load_kernel(cpu, ddr_base, ram_size,
>                             machine->initrd_filename,
>                             BINARY_DEVICE_TREE_FILE,
> 


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Re: [Qemu-devel] [PATCH v1 2/2] target/microblaze: Add props enabling exceptions on failed bus accesses

[Luc Michel]

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On 1/4/19 3:28 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Add MicroBlaze CPU properties to enable exceptions on failed
> bus accesses.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  target/microblaze/cpu.c | 12 +++++++++++-
>  target/microblaze/cpu.h |  2 ++
>  2 files changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 49876b19b3..5596cd5485 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -202,7 +202,11 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
>                          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
>                          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
> -                        (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0);
> +                        (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
> +                        (cpu->cfg.dopb_bus_exception ?
> +                                                 PVR2_DOPB_BUS_EXC_MASK : 0) |
> +                        (cpu->cfg.iopb_bus_exception ?
> +                                                 PVR2_IOPB_BUS_EXC_MASK : 0);
>  
>      env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
>                                          PVR5_DCACHE_WRITEBACK_MASK : 0;
> @@ -265,6 +269,12 @@ static Property mb_properties[] = {
>      DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
>                       false),
>      DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
> +    /* Enables bus exceptions on failed data accesses (load/stores).  */
> +    DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
> +                     cfg.dopb_bus_exception, false),
> +    /* Enables bus exceptions on failed instruction fetches.  */
> +    DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
> +                     cfg.iopb_bus_exception, false),
>      DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
>      DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
>      DEFINE_PROP_END_OF_LIST(),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 03ca91007d..792bbc97c7 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -308,6 +308,8 @@ struct MicroBlazeCPU {
>          bool use_mmu;
>          bool dcache_writeback;
>          bool endi;
> +        bool dopb_bus_exception;
> +        bool iopb_bus_exception;
>          char *version;
>          uint8_t pvr;
>      } cfg;
> 


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