* [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
@ 2022-12-05 5:00 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2022-12-05 5:00 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial
Cc: Albert Ou, Greg Kroah-Hartman, Jiri Slaby, Palmer Dabbelt, Paul Walmsley
Per RISC-V semihosting spec [1], adapt the existing Arm semihosting
earlycon driver to RISC-V.
[1] https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/earlycon-arm-semihost.c | 17 ++++++++++++++++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 434f83168546..e94d1265151c 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE
config SERIAL_EARLYCON_ARM_SEMIHOST
bool "Early console using ARM semihosting"
- depends on ARM64 || ARM
+ depends on ARM64 || ARM || RISCV
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
index fcdec5f42376..25a0f91926a3 100644
--- a/drivers/tty/serial/earlycon-arm-semihost.c
+++ b/drivers/tty/serial/earlycon-arm-semihost.c
@@ -6,6 +6,10 @@
* Adapted for ARM and earlycon:
* Copyright (C) 2014 Linaro Ltd.
* Author: Rob Herring <robh@kernel.org>
+ *
+ * Adapted for RISC-V and earlycon:
+ * Copyright (C) 2022 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
*/
#include <linux/kernel.h>
#include <linux/console.h>
@@ -23,7 +27,18 @@
*/
static void smh_putc(struct uart_port *port, unsigned char c)
{
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_RISCV)
+ asm volatile("addi a1, %0, 0\n"
+ "addi a0, zero, 3\n"
+ ".balign 16\n"
+ ".option push\n"
+ ".option norvc\n"
+ "slli zero, zero, 0x1f\n"
+ "ebreak\n"
+ "srai zero, zero, 0x7\n"
+ ".option pop\n"
+ : : "r" (&c) : "a0", "a1", "memory");
+#elif defined(CONFIG_ARM64)
asm volatile("mov x1, %0\n"
"mov x0, #3\n"
"hlt 0xf000\n"
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
@ 2022-12-05 5:00 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2022-12-05 5:00 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial
Cc: Albert Ou, Greg Kroah-Hartman, Jiri Slaby, Palmer Dabbelt, Paul Walmsley
Per RISC-V semihosting spec [1], adapt the existing Arm semihosting
earlycon driver to RISC-V.
[1] https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
drivers/tty/serial/Kconfig | 2 +-
drivers/tty/serial/earlycon-arm-semihost.c | 17 ++++++++++++++++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 434f83168546..e94d1265151c 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -75,7 +75,7 @@ config SERIAL_AMBA_PL011_CONSOLE
config SERIAL_EARLYCON_ARM_SEMIHOST
bool "Early console using ARM semihosting"
- depends on ARM64 || ARM
+ depends on ARM64 || ARM || RISCV
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-arm-semihost.c
index fcdec5f42376..25a0f91926a3 100644
--- a/drivers/tty/serial/earlycon-arm-semihost.c
+++ b/drivers/tty/serial/earlycon-arm-semihost.c
@@ -6,6 +6,10 @@
* Adapted for ARM and earlycon:
* Copyright (C) 2014 Linaro Ltd.
* Author: Rob Herring <robh@kernel.org>
+ *
+ * Adapted for RISC-V and earlycon:
+ * Copyright (C) 2022 tinylab.org
+ * Author: Bin Meng <bmeng@tinylab.org>
*/
#include <linux/kernel.h>
#include <linux/console.h>
@@ -23,7 +27,18 @@
*/
static void smh_putc(struct uart_port *port, unsigned char c)
{
-#ifdef CONFIG_ARM64
+#if defined(CONFIG_RISCV)
+ asm volatile("addi a1, %0, 0\n"
+ "addi a0, zero, 3\n"
+ ".balign 16\n"
+ ".option push\n"
+ ".option norvc\n"
+ "slli zero, zero, 0x1f\n"
+ "ebreak\n"
+ "srai zero, zero, 0x7\n"
+ ".option pop\n"
+ : : "r" (&c) : "a0", "a1", "memory");
+#elif defined(CONFIG_ARM64)
asm volatile("mov x1, %0\n"
"mov x0, #3\n"
"hlt 0xf000\n"
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] serial: Rename earlycon semihost driver
2022-12-05 5:00 ` Bin Meng
@ 2022-12-05 5:00 ` Bin Meng
-1 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2022-12-05 5:00 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial; +Cc: Greg Kroah-Hartman, Jiri Slaby
Now that earlycon semihost driver works on RISC-V too, let's use a
much more generic name for the driver.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
drivers/tty/serial/Kconfig | 12 ++++++------
drivers/tty/serial/Makefile | 2 +-
.../{earlycon-arm-semihost.c => earlycon-semihost.c} | 0
3 files changed, 7 insertions(+), 7 deletions(-)
rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (100%)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index e94d1265151c..a3779472edf6 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -73,17 +73,17 @@ config SERIAL_AMBA_PL011_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
-config SERIAL_EARLYCON_ARM_SEMIHOST
- bool "Early console using ARM semihosting"
+config SERIAL_EARLYCON_SEMIHOST
+ bool "Early console using Arm compatible semihosting"
depends on ARM64 || ARM || RISCV
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
- Support for early debug console using ARM semihosting. This enables
- the console before standard serial driver is probed. This is enabled
- with "earlycon=smh" on the kernel command line. The console is
- enabled when early_param is processed.
+ Support for early debug console using Arm compatible semihosting.
+ This enables the console before standard serial driver is probed.
+ This is enabled with "earlycon=smh" on the kernel command line.
+ The console is enabled when early_param is processed.
config SERIAL_EARLYCON_RISCV_SBI
bool "Early console using RISC-V SBI"
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 238a9557b487..cd9afd9e3018 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -6,7 +6,7 @@
obj-$(CONFIG_SERIAL_CORE) += serial_core.o
obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
-obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
+obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o
obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
# These Sparc drivers have to appear before others such as 8250
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-semihost.c
similarity index 100%
rename from drivers/tty/serial/earlycon-arm-semihost.c
rename to drivers/tty/serial/earlycon-semihost.c
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] serial: Rename earlycon semihost driver
@ 2022-12-05 5:00 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2022-12-05 5:00 UTC (permalink / raw)
To: linux-kernel, linux-riscv, linux-serial; +Cc: Greg Kroah-Hartman, Jiri Slaby
Now that earlycon semihost driver works on RISC-V too, let's use a
much more generic name for the driver.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
---
drivers/tty/serial/Kconfig | 12 ++++++------
drivers/tty/serial/Makefile | 2 +-
.../{earlycon-arm-semihost.c => earlycon-semihost.c} | 0
3 files changed, 7 insertions(+), 7 deletions(-)
rename drivers/tty/serial/{earlycon-arm-semihost.c => earlycon-semihost.c} (100%)
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index e94d1265151c..a3779472edf6 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -73,17 +73,17 @@ config SERIAL_AMBA_PL011_CONSOLE
your boot loader (lilo or loadlin) about how to pass options to the
kernel at boot time.)
-config SERIAL_EARLYCON_ARM_SEMIHOST
- bool "Early console using ARM semihosting"
+config SERIAL_EARLYCON_SEMIHOST
+ bool "Early console using Arm compatible semihosting"
depends on ARM64 || ARM || RISCV
select SERIAL_CORE
select SERIAL_CORE_CONSOLE
select SERIAL_EARLYCON
help
- Support for early debug console using ARM semihosting. This enables
- the console before standard serial driver is probed. This is enabled
- with "earlycon=smh" on the kernel command line. The console is
- enabled when early_param is processed.
+ Support for early debug console using Arm compatible semihosting.
+ This enables the console before standard serial driver is probed.
+ This is enabled with "earlycon=smh" on the kernel command line.
+ The console is enabled when early_param is processed.
config SERIAL_EARLYCON_RISCV_SBI
bool "Early console using RISC-V SBI"
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 238a9557b487..cd9afd9e3018 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -6,7 +6,7 @@
obj-$(CONFIG_SERIAL_CORE) += serial_core.o
obj-$(CONFIG_SERIAL_EARLYCON) += earlycon.o
-obj-$(CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST) += earlycon-arm-semihost.o
+obj-$(CONFIG_SERIAL_EARLYCON_SEMIHOST) += earlycon-semihost.o
obj-$(CONFIG_SERIAL_EARLYCON_RISCV_SBI) += earlycon-riscv-sbi.o
# These Sparc drivers have to appear before others such as 8250
diff --git a/drivers/tty/serial/earlycon-arm-semihost.c b/drivers/tty/serial/earlycon-semihost.c
similarity index 100%
rename from drivers/tty/serial/earlycon-arm-semihost.c
rename to drivers/tty/serial/earlycon-semihost.c
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
2022-12-05 5:00 ` Bin Meng
@ 2022-12-06 6:35 ` Jiri Slaby
-1 siblings, 0 replies; 8+ messages in thread
From: Jiri Slaby @ 2022-12-06 6:35 UTC (permalink / raw)
To: Bin Meng, linux-kernel, linux-riscv, linux-serial
Cc: Albert Ou, Greg Kroah-Hartman, Palmer Dabbelt, Paul Walmsley
On 05. 12. 22, 6:00, Bin Meng wrote:
...
> --- a/drivers/tty/serial/earlycon-arm-semihost.c
> +++ b/drivers/tty/serial/earlycon-arm-semihost.c
...
> @@ -23,7 +27,18 @@
> */
> static void smh_putc(struct uart_port *port, unsigned char c)
> {
> -#ifdef CONFIG_ARM64
> +#if defined(CONFIG_RISCV)
> + asm volatile("addi a1, %0, 0\n"
> + "addi a0, zero, 3\n"
> + ".balign 16\n"
> + ".option push\n"
> + ".option norvc\n"
> + "slli zero, zero, 0x1f\n"
> + "ebreak\n"
> + "srai zero, zero, 0x7\n"
> + ".option pop\n"
> + : : "r" (&c) : "a0", "a1", "memory");
> +#elif defined(CONFIG_ARM64)
> asm volatile("mov x1, %0\n"
> "mov x0, #3\n"
> "hlt 0xf000\n"
Hmm, can we implement all those smh_putc() variants in respective
arch/*/include/semihost.h instead?
thanks,
--
js
suse labs
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
@ 2022-12-06 6:35 ` Jiri Slaby
0 siblings, 0 replies; 8+ messages in thread
From: Jiri Slaby @ 2022-12-06 6:35 UTC (permalink / raw)
To: Bin Meng, linux-kernel, linux-riscv, linux-serial
Cc: Albert Ou, Greg Kroah-Hartman, Palmer Dabbelt, Paul Walmsley
On 05. 12. 22, 6:00, Bin Meng wrote:
...
> --- a/drivers/tty/serial/earlycon-arm-semihost.c
> +++ b/drivers/tty/serial/earlycon-arm-semihost.c
...
> @@ -23,7 +27,18 @@
> */
> static void smh_putc(struct uart_port *port, unsigned char c)
> {
> -#ifdef CONFIG_ARM64
> +#if defined(CONFIG_RISCV)
> + asm volatile("addi a1, %0, 0\n"
> + "addi a0, zero, 3\n"
> + ".balign 16\n"
> + ".option push\n"
> + ".option norvc\n"
> + "slli zero, zero, 0x1f\n"
> + "ebreak\n"
> + "srai zero, zero, 0x7\n"
> + ".option pop\n"
> + : : "r" (&c) : "a0", "a1", "memory");
> +#elif defined(CONFIG_ARM64)
> asm volatile("mov x1, %0\n"
> "mov x0, #3\n"
> "hlt 0xf000\n"
Hmm, can we implement all those smh_putc() variants in respective
arch/*/include/semihost.h instead?
thanks,
--
js
suse labs
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
2022-12-06 6:35 ` Jiri Slaby
@ 2022-12-06 14:23 ` Bin Meng
-1 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2022-12-06 14:23 UTC (permalink / raw)
To: Jiri Slaby
Cc: Bin Meng, linux-kernel, linux-riscv, linux-serial, Albert Ou,
Greg Kroah-Hartman, Palmer Dabbelt, Paul Walmsley
On Tue, Dec 6, 2022 at 2:47 PM Jiri Slaby <jirislaby@kernel.org> wrote:
>
> On 05. 12. 22, 6:00, Bin Meng wrote:
> ...
> > --- a/drivers/tty/serial/earlycon-arm-semihost.c
> > +++ b/drivers/tty/serial/earlycon-arm-semihost.c
> ...
> > @@ -23,7 +27,18 @@
> > */
> > static void smh_putc(struct uart_port *port, unsigned char c)
> > {
> > -#ifdef CONFIG_ARM64
> > +#if defined(CONFIG_RISCV)
> > + asm volatile("addi a1, %0, 0\n"
> > + "addi a0, zero, 3\n"
> > + ".balign 16\n"
> > + ".option push\n"
> > + ".option norvc\n"
> > + "slli zero, zero, 0x1f\n"
> > + "ebreak\n"
> > + "srai zero, zero, 0x7\n"
> > + ".option pop\n"
> > + : : "r" (&c) : "a0", "a1", "memory");
> > +#elif defined(CONFIG_ARM64)
> > asm volatile("mov x1, %0\n"
> > "mov x0, #3\n"
> > "hlt 0xf000\n"
>
> Hmm, can we implement all those smh_putc() variants in respective
> arch/*/include/semihost.h instead?
>
I think so. Will do in v2.
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V
@ 2022-12-06 14:23 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2022-12-06 14:23 UTC (permalink / raw)
To: Jiri Slaby
Cc: Bin Meng, linux-kernel, linux-riscv, linux-serial, Albert Ou,
Greg Kroah-Hartman, Palmer Dabbelt, Paul Walmsley
On Tue, Dec 6, 2022 at 2:47 PM Jiri Slaby <jirislaby@kernel.org> wrote:
>
> On 05. 12. 22, 6:00, Bin Meng wrote:
> ...
> > --- a/drivers/tty/serial/earlycon-arm-semihost.c
> > +++ b/drivers/tty/serial/earlycon-arm-semihost.c
> ...
> > @@ -23,7 +27,18 @@
> > */
> > static void smh_putc(struct uart_port *port, unsigned char c)
> > {
> > -#ifdef CONFIG_ARM64
> > +#if defined(CONFIG_RISCV)
> > + asm volatile("addi a1, %0, 0\n"
> > + "addi a0, zero, 3\n"
> > + ".balign 16\n"
> > + ".option push\n"
> > + ".option norvc\n"
> > + "slli zero, zero, 0x1f\n"
> > + "ebreak\n"
> > + "srai zero, zero, 0x7\n"
> > + ".option pop\n"
> > + : : "r" (&c) : "a0", "a1", "memory");
> > +#elif defined(CONFIG_ARM64)
> > asm volatile("mov x1, %0\n"
> > "mov x0, #3\n"
> > "hlt 0xf000\n"
>
> Hmm, can we implement all those smh_putc() variants in respective
> arch/*/include/semihost.h instead?
>
I think so. Will do in v2.
Regards,
Bin
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-12-06 14:23 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-05 5:00 [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V Bin Meng
2022-12-05 5:00 ` Bin Meng
2022-12-05 5:00 ` [PATCH 2/2] serial: Rename earlycon semihost driver Bin Meng
2022-12-05 5:00 ` Bin Meng
2022-12-06 6:35 ` [PATCH 1/2] serial: Adapt Arm semihosting earlycon driver to RISC-V Jiri Slaby
2022-12-06 6:35 ` Jiri Slaby
2022-12-06 14:23 ` Bin Meng
2022-12-06 14:23 ` Bin Meng
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