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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@collabora.com>
To: Rob Herring <robh@kernel.org>
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
	mturquette@baylibre.com, sboyd@kernel.org,
	p.zabel@pengutronix.de, y.oudjana@protonmail.com,
	jason-jh.lin@mediatek.com, ck.hu@mediatek.com,
	fparent@baylibre.com, rex-bc.chen@mediatek.com,
	tinghan.shen@mediatek.com, chun-jie.chen@mediatek.com,
	weiyi.lu@mediatek.com, ikjn@chromium.org,
	miles.chen@mediatek.com, sam.shih@mediatek.com,
	wenst@chromium.org, bgolaszewski@baylibre.com,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
	konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
	martin.botka@somainline.org,
	~postmarketos/upstreaming@lists.sr.ht,
	phone-devel@vger.kernel.org, paul.bouchara@somainline.org,
	kernel@collabora.com
Subject: Re: [PATCH 4/5] dt-bindings: arm: mediatek: Add clock driver bindings for MT6795
Date: Tue, 17 May 2022 09:48:25 +0200	[thread overview]
Message-ID: <b3e34db8-4e79-f6e3-35b8-e32891f2c85b@collabora.com> (raw)
In-Reply-To: <20220516172819.GA2938099-robh@kernel.org>

Il 16/05/22 19:28, Rob Herring ha scritto:
> On Fri, May 13, 2022 at 06:50:49PM +0200, AngeloGioacchino Del Regno wrote:
>> Add the bindings for the clock drivers of the MediaTek Helio X10
>> MT6795 SoC.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../arm/mediatek/mediatek,mt6795-clock.yaml   | 67 +++++++++++++++++
>>   .../mediatek/mediatek,mt6795-sys-clock.yaml   | 73 +++++++++++++++++++
>>   2 files changed, 140 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>>   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>> new file mode 100644
>> index 000000000000..b7d96d0ed867
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>> @@ -0,0 +1,67 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-clock.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: MediaTek Functional Clock Controller for MT6795
>> +
>> +maintainers:
>> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
>> +
>> +description: |
>> +  The clock architecture in MediaTek like below
>> +  PLLs -->
>> +          dividers -->
>> +                      muxes
>> +                           -->
>> +                              clock gate
>> +
>> +  The devices provide clock gate control in different IP blocks.
>> +
>> +properties:
>> +  compatible:
>> +    items:
> 
> Don't need 'items' if only 1 item.
> 
>> +      - enum:
>> +          - mediatek,mt6795-mfgcfg
>> +          - mediatek,mt6795-vdecsys
>> +          - mediatek,mt6795-vencsys
> 
> blank line.
> 
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
> 
> Why is #clock-cells optional?
> 

I've used one of the other mediatek,mt(something)-(sys-)clock.yaml as a base
for these ones, giving for granted that they were correct, but now that you're
pointing that out... effectively, I should've checked if the ones that are
already merged in were correct *before* using these as a base for mine.

Thanks for your review: I'll send a v2 soon... and I will also separately
send some fixes for the existing ones, as your review comments also apply
to these ones.

Regards,
Angelo


WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Rob Herring <robh@kernel.org>
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
	mturquette@baylibre.com, sboyd@kernel.org,
	p.zabel@pengutronix.de, y.oudjana@protonmail.com,
	jason-jh.lin@mediatek.com, ck.hu@mediatek.com,
	fparent@baylibre.com, rex-bc.chen@mediatek.com,
	tinghan.shen@mediatek.com, chun-jie.chen@mediatek.com,
	weiyi.lu@mediatek.com, ikjn@chromium.org,
	miles.chen@mediatek.com, sam.shih@mediatek.com,
	wenst@chromium.org, bgolaszewski@baylibre.com,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
	konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
	martin.botka@somainline.org,
	~postmarketos/upstreaming@lists.sr.ht,
	phone-devel@vger.kernel.org, paul.bouchara@somainline.org,
	kernel@collabora.com
Subject: Re: [PATCH 4/5] dt-bindings: arm: mediatek: Add clock driver bindings for MT6795
Date: Tue, 17 May 2022 09:48:25 +0200	[thread overview]
Message-ID: <b3e34db8-4e79-f6e3-35b8-e32891f2c85b@collabora.com> (raw)
In-Reply-To: <20220516172819.GA2938099-robh@kernel.org>

Il 16/05/22 19:28, Rob Herring ha scritto:
> On Fri, May 13, 2022 at 06:50:49PM +0200, AngeloGioacchino Del Regno wrote:
>> Add the bindings for the clock drivers of the MediaTek Helio X10
>> MT6795 SoC.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../arm/mediatek/mediatek,mt6795-clock.yaml   | 67 +++++++++++++++++
>>   .../mediatek/mediatek,mt6795-sys-clock.yaml   | 73 +++++++++++++++++++
>>   2 files changed, 140 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>>   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>> new file mode 100644
>> index 000000000000..b7d96d0ed867
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>> @@ -0,0 +1,67 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-clock.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: MediaTek Functional Clock Controller for MT6795
>> +
>> +maintainers:
>> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
>> +
>> +description: |
>> +  The clock architecture in MediaTek like below
>> +  PLLs -->
>> +          dividers -->
>> +                      muxes
>> +                           -->
>> +                              clock gate
>> +
>> +  The devices provide clock gate control in different IP blocks.
>> +
>> +properties:
>> +  compatible:
>> +    items:
> 
> Don't need 'items' if only 1 item.
> 
>> +      - enum:
>> +          - mediatek,mt6795-mfgcfg
>> +          - mediatek,mt6795-vdecsys
>> +          - mediatek,mt6795-vencsys
> 
> blank line.
> 
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
> 
> Why is #clock-cells optional?
> 

I've used one of the other mediatek,mt(something)-(sys-)clock.yaml as a base
for these ones, giving for granted that they were correct, but now that you're
pointing that out... effectively, I should've checked if the ones that are
already merged in were correct *before* using these as a base for mine.

Thanks for your review: I'll send a v2 soon... and I will also separately
send some fixes for the existing ones, as your review comments also apply
to these ones.

Regards,
Angelo


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
To: Rob Herring <robh@kernel.org>
Cc: krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
	mturquette@baylibre.com, sboyd@kernel.org,
	p.zabel@pengutronix.de, y.oudjana@protonmail.com,
	jason-jh.lin@mediatek.com, ck.hu@mediatek.com,
	fparent@baylibre.com, rex-bc.chen@mediatek.com,
	tinghan.shen@mediatek.com, chun-jie.chen@mediatek.com,
	weiyi.lu@mediatek.com, ikjn@chromium.org,
	miles.chen@mediatek.com, sam.shih@mediatek.com,
	wenst@chromium.org, bgolaszewski@baylibre.com,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
	konrad.dybcio@somainline.org, marijn.suijten@somainline.org,
	martin.botka@somainline.org,
	~postmarketos/upstreaming@lists.sr.ht,
	phone-devel@vger.kernel.org, paul.bouchara@somainline.org,
	kernel@collabora.com
Subject: Re: [PATCH 4/5] dt-bindings: arm: mediatek: Add clock driver bindings for MT6795
Date: Tue, 17 May 2022 09:48:25 +0200	[thread overview]
Message-ID: <b3e34db8-4e79-f6e3-35b8-e32891f2c85b@collabora.com> (raw)
In-Reply-To: <20220516172819.GA2938099-robh@kernel.org>

Il 16/05/22 19:28, Rob Herring ha scritto:
> On Fri, May 13, 2022 at 06:50:49PM +0200, AngeloGioacchino Del Regno wrote:
>> Add the bindings for the clock drivers of the MediaTek Helio X10
>> MT6795 SoC.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>   .../arm/mediatek/mediatek,mt6795-clock.yaml   | 67 +++++++++++++++++
>>   .../mediatek/mediatek,mt6795-sys-clock.yaml   | 73 +++++++++++++++++++
>>   2 files changed, 140 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>>   create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-sys-clock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>> new file mode 100644
>> index 000000000000..b7d96d0ed867
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt6795-clock.yaml
>> @@ -0,0 +1,67 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt6795-clock.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: MediaTek Functional Clock Controller for MT6795
>> +
>> +maintainers:
>> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> +  - Chun-Jie Chen <chun-jie.chen@mediatek.com>
>> +
>> +description: |
>> +  The clock architecture in MediaTek like below
>> +  PLLs -->
>> +          dividers -->
>> +                      muxes
>> +                           -->
>> +                              clock gate
>> +
>> +  The devices provide clock gate control in different IP blocks.
>> +
>> +properties:
>> +  compatible:
>> +    items:
> 
> Don't need 'items' if only 1 item.
> 
>> +      - enum:
>> +          - mediatek,mt6795-mfgcfg
>> +          - mediatek,mt6795-vdecsys
>> +          - mediatek,mt6795-vencsys
> 
> blank line.
> 
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
> 
> Why is #clock-cells optional?
> 

I've used one of the other mediatek,mt(something)-(sys-)clock.yaml as a base
for these ones, giving for granted that they were correct, but now that you're
pointing that out... effectively, I should've checked if the ones that are
already merged in were correct *before* using these as a base for mine.

Thanks for your review: I'll send a v2 soon... and I will also separately
send some fixes for the existing ones, as your review comments also apply
to these ones.

Regards,
Angelo


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-05-17  7:48 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-13 16:50 [PATCH 0/5] MediaTek Helio X10 MT6795 - Clock drivers AngeloGioacchino Del Regno
2022-05-13 16:50 ` AngeloGioacchino Del Regno
2022-05-13 16:50 ` AngeloGioacchino Del Regno
2022-05-13 16:50 ` [PATCH 1/5] dt-bindings: mediatek: Document MT6795 system controllers bindings AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-16 16:03   ` Rob Herring
2022-05-16 16:03     ` Rob Herring
2022-05-16 16:03     ` Rob Herring
2022-05-13 16:50 ` [PATCH 2/5] dt-bindings: clock: Add MediaTek Helio X10 MT6795 clock bindings AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 16:50 ` [PATCH 3/5] dt-bindings: reset: Add bindings for MT6795 Helio X10 reset controllers AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 16:50 ` [PATCH 4/5] dt-bindings: arm: mediatek: Add clock driver bindings for MT6795 AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 20:48   ` Rob Herring
2022-05-13 20:48     ` Rob Herring
2022-05-13 20:48     ` Rob Herring
2022-05-16 17:28   ` Rob Herring
2022-05-16 17:28     ` Rob Herring
2022-05-16 17:28     ` Rob Herring
2022-05-17  7:48     ` AngeloGioacchino Del Regno [this message]
2022-05-17  7:48       ` AngeloGioacchino Del Regno
2022-05-17  7:48       ` AngeloGioacchino Del Regno
2022-05-13 16:50 ` [PATCH 5/5] clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 16:50   ` AngeloGioacchino Del Regno
2022-05-13 22:00   ` kernel test robot
2022-05-13 22:00     ` kernel test robot
2022-05-13 22:00     ` kernel test robot
2022-05-13 23:01   ` kernel test robot
2022-05-13 23:01     ` kernel test robot
2022-05-13 23:01     ` kernel test robot
2022-05-16 11:30   ` Matthias Brugger
2022-05-16 11:30     ` Matthias Brugger
2022-05-16 11:30     ` Matthias Brugger
2022-05-17  8:07     ` AngeloGioacchino Del Regno
2022-05-17  8:07       ` AngeloGioacchino Del Regno
2022-05-17  8:07       ` AngeloGioacchino Del Regno
2022-05-17  8:48       ` Matthias Brugger
2022-05-17  8:48         ` Matthias Brugger
2022-05-17  8:48         ` Matthias Brugger
2022-05-17  8:59         ` AngeloGioacchino Del Regno
2022-05-17  8:59           ` AngeloGioacchino Del Regno
2022-05-17  8:59           ` AngeloGioacchino Del Regno
2022-05-13 16:54 ` [PATCH 0/5] MediaTek Helio X10 MT6795 - Clock drivers AngeloGioacchino Del Regno
2022-05-13 16:54   ` AngeloGioacchino Del Regno
2022-05-13 16:54   ` AngeloGioacchino Del Regno
2022-05-18  0:47   ` Rob Herring
2022-05-18  0:47     ` Rob Herring
2022-05-18  0:47     ` Rob Herring

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