[PATCH v2 1/3] clk: imx8mm: Add support for PCIe clocks

[PATCH v2 1/3] clk: imx8mm: Add support for PCIe clocks

[Tim Harvey]

Add support for PCIe clocks required to enable PCIe support on
iMX8MM SoC.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v2: no changes
---
 drivers/clk/imx/clk-imx8mm.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index b5c253e49663..c2f01b385201 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
 static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
 					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
 
+static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
+					       "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
+
+static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
+					      "clk_ext3", "clk_ext4", "sys_pll1_400m", };
+
+static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
+					      "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
+
 #ifndef CONFIG_SPL_BUILD
 static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
 					 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
@@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev)
 		imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
 
 	/* IP */
+	clk_dm(IMX8MM_CLK_PCIE1_CTRL,
+	       imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
+				   base + 0xa300));
+	clk_dm(IMX8MM_CLK_PCIE1_PHY,
+	       imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
+				   base + 0xa380));
+	clk_dm(IMX8MM_CLK_PCIE1_AUX,
+	       imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
+				   base + 0xa400));
 	clk_dm(IMX8MM_CLK_USDHC1,
 	       imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
 				   base + 0xac00));
@@ -339,6 +357,9 @@ static int imx8mm_clk_probe(struct udevice *dev)
 	       imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
 #endif
 
+	clk_dm(IMX8MM_CLK_PCIE1_ROOT,
+	       imx_clk_gate4("pcie1_root_clk", "pcie1_ctrl", base + 0x4250, 0));
+
 #if CONFIG_IS_ENABLED(DM_SPI)
 	clk_dm(IMX8MM_CLK_ECSPI1,
 	       imx8m_clk_composite("ecspi1", imx8mm_ecspi1_sels, base + 0xb280));
-- 
2.25.1

[PATCH v2 2/3] pci: dw_imx: add support for IMX8MM

[Tim Harvey]

Add support for the IMX8MM SoC by adding driver data with the compatible
string of the GPR controller.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v2: do not cache chip info in priv per Marek's suggestion
---
 drivers/pci/pcie_dw_imx.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie_dw_imx.c b/drivers/pci/pcie_dw_imx.c
index a2ee228224b5..fdb463710ba1 100644
--- a/drivers/pci/pcie_dw_imx.c
+++ b/drivers/pci/pcie_dw_imx.c
@@ -56,6 +56,18 @@ struct pcie_dw_imx {
 	struct udevice			*vpcie;
 };
 
+struct pcie_chip_info {
+	const char *gpr;
+};
+
+static const struct pcie_chip_info imx8mm_chip_info = {
+	.gpr = "fsl,imx8mm-iomuxc-gpr",
+};
+
+static const struct pcie_chip_info imx8mp_chip_info = {
+	.gpr = "fsl,imx8mp-iomuxc-gpr",
+};
+
 static void pcie_dw_configure(struct pcie_dw_imx *priv, u32 cap_speed)
 {
 	dw_pcie_dbi_write_enable(&priv->dw, true);
@@ -242,6 +254,7 @@ static int pcie_dw_imx_remove(struct udevice *dev)
 
 static int pcie_dw_imx_of_to_plat(struct udevice *dev)
 {
+	struct pcie_chip_info *info = (void *)dev_get_driver_data(dev);
 	struct pcie_dw_imx *priv = dev_get_priv(dev);
 	ofnode gpr;
 	int ret;
@@ -287,7 +300,7 @@ static int pcie_dw_imx_of_to_plat(struct udevice *dev)
 		goto err_phy;
 	}
 
-	gpr = ofnode_by_compatible(ofnode_null(), "fsl,imx8mp-iomuxc-gpr");
+	gpr = ofnode_by_compatible(ofnode_null(), info->gpr);
 	if (ofnode_equal(gpr, ofnode_null())) {
 		dev_err(dev, "unable to find GPR node\n");
 		ret = -ENODEV;
@@ -322,7 +335,8 @@ static const struct dm_pci_ops pcie_dw_imx_ops = {
 };
 
 static const struct udevice_id pcie_dw_imx_ids[] = {
-	{ .compatible = "fsl,imx8mp-pcie" },
+	{ .compatible = "fsl,imx8mm-pcie", .data = (ulong)&imx8mm_chip_info, },
+	{ .compatible = "fsl,imx8mp-pcie", .data = (ulong)&imx8mp_chip_info, },
 	{ }
 };
 
-- 
2.25.1

[PATCH v2 3/3] imx8mm_venice_defconfig: Enable PCIe/NVMe support

[Tim Harvey]

Enable PCIe/NVMe support. Also, enable the reset
driver which is a prerequisite for PCIe support.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---
v2: no changes
---
 configs/imx8mm_venice_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index 517b70b69477..0f97b4b84243 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mm-venice-gw71xx-0x"
 CONFIG_SPL_TEXT_BASE=0x7E1000
 CONFIG_TARGET_IMX8MM_VENICE=y
 CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=524288
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
@@ -20,6 +21,7 @@ CONFIG_SPL_STACK=0x920000
 CONFIG_SPL=y
 CONFIG_ENV_OFFSET_REDUND=0x3f8000
 CONFIG_SYS_LOAD_ADDR=0x48200000
+CONFIG_PCI=y
 CONFIG_SYS_MEMTEST_START=0x40000000
 CONFIG_SYS_MEMTEST_END=0x80000000
 CONFIG_FIT=y
@@ -60,6 +62,7 @@ CONFIG_CMD_FUSE=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_DHCP6=y
@@ -120,6 +123,9 @@ CONFIG_PHY_GIGE=y
 CONFIG_FEC_MXC=y
 CONFIG_KSZ9477=y
 CONFIG_MII=y
+CONFIG_NVME_PCI=y
+CONFIG_PCIE_DW_IMX=y
+CONFIG_PHY_IMX8M_PCIE=y
 CONFIG_PINCTRL=y
 CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_IMX8M=y
-- 
2.25.1

Re: [PATCH v2 2/3] pci: dw_imx: add support for IMX8MM

[Marek Vasut]

On 4/18/24 7:56 PM, Tim Harvey wrote:
> Add support for the IMX8MM SoC by adding driver data with the compatible
> string of the GPR controller.
> 
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>

Reviewed-by: Marek Vasut <marex@denx.de>

Re: [PATCH v2 1/3] clk: imx8mm: Add support for PCIe clocks

[Marek Vasut]

On 4/18/24 7:56 PM, Tim Harvey wrote:
> Add support for PCIe clocks required to enable PCIe support on
> iMX8MM SoC.
> 
> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> ---
> v2: no changes
> ---
>   drivers/clk/imx/clk-imx8mm.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> index b5c253e49663..c2f01b385201 100644
> --- a/drivers/clk/imx/clk-imx8mm.c
> +++ b/drivers/clk/imx/clk-imx8mm.c
> @@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
>   static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
>   					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
>   
> +static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
> +					       "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
> +
> +static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
> +					      "clk_ext3", "clk_ext4", "sys_pll1_400m", };
> +
> +static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
> +					      "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
> +
>   #ifndef CONFIG_SPL_BUILD
>   static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
>   					 "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
> @@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev)
>   		imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
>   
>   	/* IP */
> +	clk_dm(IMX8MM_CLK_PCIE1_CTRL,
> +	       imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
> +				   base + 0xa300));
> +	clk_dm(IMX8MM_CLK_PCIE1_PHY,
> +	       imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
> +				   base + 0xa380));
> +	clk_dm(IMX8MM_CLK_PCIE1_AUX,
> +	       imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
> +				   base + 0xa400));

Maybe this should be behind IS_ENABLED() like the SPI clock to avoid 
growth of SPL ?

Re: [PATCH v2 1/3] clk: imx8mm: Add support for PCIe clocks

[Tim Harvey]

On Thu, Apr 18, 2024 at 11:14 AM Marek Vasut <marex@denx.de> wrote:
>
> On 4/18/24 7:56 PM, Tim Harvey wrote:
> > Add support for PCIe clocks required to enable PCIe support on
> > iMX8MM SoC.
> >
> > Signed-off-by: Tim Harvey <tharvey@gateworks.com>
> > ---
> > v2: no changes
> > ---
> >   drivers/clk/imx/clk-imx8mm.c | 21 +++++++++++++++++++++
> >   1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
> > index b5c253e49663..c2f01b385201 100644
> > --- a/drivers/clk/imx/clk-imx8mm.c
> > +++ b/drivers/clk/imx/clk-imx8mm.c
> > @@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
> >   static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
> >                                        "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
> >
> > +static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
> > +                                            "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
> > +
> > +static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
> > +                                           "clk_ext3", "clk_ext4", "sys_pll1_400m", };
> > +
> > +static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
> > +                                           "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
> > +
> >   #ifndef CONFIG_SPL_BUILD
> >   static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
> >                                        "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
> > @@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev)
> >               imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
> >
> >       /* IP */
> > +     clk_dm(IMX8MM_CLK_PCIE1_CTRL,
> > +            imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
> > +                                base + 0xa300));
> > +     clk_dm(IMX8MM_CLK_PCIE1_PHY,
> > +            imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
> > +                                base + 0xa380));
> > +     clk_dm(IMX8MM_CLK_PCIE1_AUX,
> > +            imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
> > +                                base + 0xa400));
>
> Maybe this should be behind IS_ENABLED() like the SPI clock to avoid
> growth of SPL ?

Makes sense... I'll add that in a v3. Thanks for the review!

Best Regards,

Tim

Re: [PATCH v2 1/3] clk: imx8mm: Add support for PCIe clocks

[Marek Vasut]

On 4/18/24 8:24 PM, Tim Harvey wrote:
> On Thu, Apr 18, 2024 at 11:14 AM Marek Vasut <marex@denx.de> wrote:
>>
>> On 4/18/24 7:56 PM, Tim Harvey wrote:
>>> Add support for PCIe clocks required to enable PCIe support on
>>> iMX8MM SoC.
>>>
>>> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
>>> ---
>>> v2: no changes
>>> ---
>>>    drivers/clk/imx/clk-imx8mm.c | 21 +++++++++++++++++++++
>>>    1 file changed, 21 insertions(+)
>>>
>>> diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
>>> index b5c253e49663..c2f01b385201 100644
>>> --- a/drivers/clk/imx/clk-imx8mm.c
>>> +++ b/drivers/clk/imx/clk-imx8mm.c
>>> @@ -66,6 +66,15 @@ static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_
>>>    static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
>>>                                         "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
>>>
>>> +static const char *imx8mm_pcie1_ctrl_sels[] = {"clock-osc-24m", "sys_pll2_250m", "sys_pll2_200m", "sys_pll1_266m",
>>> +                                            "sys_pll1_800m", "sys_pll2_500m", "sys_pll2_333m", "sys_pll3_out", };
>>> +
>>> +static const char *imx8mm_pcie1_phy_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll2_500m", "clk_ext1", "clk_ext2",
>>> +                                           "clk_ext3", "clk_ext4", "sys_pll1_400m", };
>>> +
>>> +static const char *imx8mm_pcie1_aux_sels[] = {"clock-osc-24m", "sys_pll2_200m", "sys_pll2_50m", "sys_pll3_out",
>>> +                                           "sys_pll2_100m", "sys_pll1_80m", "sys_pll1_160m", "sys_pll1_200m", };
>>> +
>>>    #ifndef CONFIG_SPL_BUILD
>>>    static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
>>>                                         "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
>>> @@ -256,6 +265,15 @@ static int imx8mm_clk_probe(struct udevice *dev)
>>>                imx8m_clk_composite("usb_bus", imx8mm_usb_bus_sels, base + 0x8b80));
>>>
>>>        /* IP */
>>> +     clk_dm(IMX8MM_CLK_PCIE1_CTRL,
>>> +            imx8m_clk_composite("pcie1_ctrl", imx8mm_pcie1_ctrl_sels,
>>> +                                base + 0xa300));
>>> +     clk_dm(IMX8MM_CLK_PCIE1_PHY,
>>> +            imx8m_clk_composite("pcie1_phy", imx8mm_pcie1_phy_sels,
>>> +                                base + 0xa380));
>>> +     clk_dm(IMX8MM_CLK_PCIE1_AUX,
>>> +            imx8m_clk_composite("pcie1_aux", imx8mm_pcie1_aux_sels,
>>> +                                base + 0xa400));
>>
>> Maybe this should be behind IS_ENABLED() like the SPI clock to avoid
>> growth of SPL ?
> 
> Makes sense... I'll add that in a v3. Thanks for the review!

Of course, glad I could help.