From: John Youn <johnyoun@synopsys.com> To: John Youn <johnyoun@synopsys.com> To: Felipe Balbi <balbi@kernel.org> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org> To: linux-usb@vger.kernel.org To: linux-kernel@vger.kernel.org Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Cc: Remi Pommarel <repk@triplefau.lt> Cc: Caesar Wang <caesar.upstream@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Tao Huang <huangtao@rock-chips.com> Cc: Michael Niewoehner <linux@mniewoehner.de> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Julius Werner <jwerner@chromium.org> Cc: Doug Anderson <dianders@chromium.org> Subject: [PATCH v5 3/3] usb: dwc2: Properly account for the force mode delays Date: Wed, 07 Sep 2016 19:39:43 -0700 [thread overview] Message-ID: <b4aac4b197241b8199c5300656d245692eb45856.1473302184.git.johnyoun@synopsys.com> (raw) In-Reply-To: <cover.1473302184.git.johnyoun@synopsys.com> When a force mode bit is set and the IDDIG debounce filter is enabled, there is a delay for the forced mode to take effect. This delay is due to the IDDIG debounce filter and is variable depending on the platform's PHY clock speed. To account for this delay we can poll for the expected mode. On a clear force mode, since we don't know what mode to poll for, delay for a fixed 100 ms. This is the maximum delay based on the slowest PHY clock speed. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: John Youn <johnyoun@synopsys.com> --- drivers/usb/dwc2/core.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index a3068e0..fa9b26b 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -395,9 +395,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg) * Checks are done in this function to determine whether doing a force * would be valid or not. * - * If a force is done, it requires a 25ms delay to take effect. - * - * Returns true if the mode was forced. + * If a force is done, it requires a IDDIG debounce filter delay if + * the filter is configured and enabled. We poll the current mode of + * the controller to account for this delay. */ static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) { @@ -432,12 +432,18 @@ static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) gusbcfg |= set; dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); - msleep(25); + dwc2_wait_for_mode(hsotg, host); return true; } -/* - * Clears the force mode bits. +/** + * dwc2_clear_force_mode() - Clears the force mode bits. + * + * After clearing the bits, wait up to 100 ms to account for any + * potential IDDIG filter delay. We can't know if we expect this delay + * or not because the value of the connector ID status is affected by + * the force mode. We only need to call this once during probe if + * dr_mode == OTG. */ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) { @@ -448,11 +454,8 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) gusbcfg &= ~GUSBCFG_FORCEDEVMODE; dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); - /* - * NOTE: This long sleep is _very_ important, otherwise the core will - * not stay in host mode after a connector ID change! - */ - msleep(25); + if (dwc2_iddig_filter_enabled(hsotg)) + usleep_range(100000, 110000); } /* @@ -475,12 +478,6 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) __func__, hsotg->dr_mode); break; } - - /* - * NOTE: This is required for some rockchip soc based - * platforms. - */ - msleep(50); } /* -- 2.9.0
WARNING: multiple messages have this Message-ID (diff)
From: johnyoun@synopsys.com (John Youn) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 3/3] usb: dwc2: Properly account for the force mode delays Date: Wed, 07 Sep 2016 19:39:43 -0700 [thread overview] Message-ID: <b4aac4b197241b8199c5300656d245692eb45856.1473302184.git.johnyoun@synopsys.com> (raw) In-Reply-To: <cover.1473302184.git.johnyoun@synopsys.com> When a force mode bit is set and the IDDIG debounce filter is enabled, there is a delay for the forced mode to take effect. This delay is due to the IDDIG debounce filter and is variable depending on the platform's PHY clock speed. To account for this delay we can poll for the expected mode. On a clear force mode, since we don't know what mode to poll for, delay for a fixed 100 ms. This is the maximum delay based on the slowest PHY clock speed. Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: John Youn <johnyoun@synopsys.com> --- drivers/usb/dwc2/core.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index a3068e0..fa9b26b 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -395,9 +395,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg) * Checks are done in this function to determine whether doing a force * would be valid or not. * - * If a force is done, it requires a 25ms delay to take effect. - * - * Returns true if the mode was forced. + * If a force is done, it requires a IDDIG debounce filter delay if + * the filter is configured and enabled. We poll the current mode of + * the controller to account for this delay. */ static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) { @@ -432,12 +432,18 @@ static bool dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) gusbcfg |= set; dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); - msleep(25); + dwc2_wait_for_mode(hsotg, host); return true; } -/* - * Clears the force mode bits. +/** + * dwc2_clear_force_mode() - Clears the force mode bits. + * + * After clearing the bits, wait up to 100 ms to account for any + * potential IDDIG filter delay. We can't know if we expect this delay + * or not because the value of the connector ID status is affected by + * the force mode. We only need to call this once during probe if + * dr_mode == OTG. */ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) { @@ -448,11 +454,8 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) gusbcfg &= ~GUSBCFG_FORCEDEVMODE; dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); - /* - * NOTE: This long sleep is _very_ important, otherwise the core will - * not stay in host mode after a connector ID change! - */ - msleep(25); + if (dwc2_iddig_filter_enabled(hsotg)) + usleep_range(100000, 110000); } /* @@ -475,12 +478,6 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) __func__, hsotg->dr_mode); break; } - - /* - * NOTE: This is required for some rockchip soc based - * platforms. - */ - msleep(50); } /* -- 2.9.0
next prev parent reply other threads:[~2016-09-08 2:40 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-09-08 2:39 [PATCH v5 0/3] usb: dwc2: Fix core reset and force mode delays John Youn 2016-09-08 2:39 ` John Youn 2016-09-08 2:39 ` [PATCH v5 1/3] usb: dwc2: gadget: Only initialize device if in device mode John Youn 2016-09-08 2:39 ` John Youn 2016-09-08 2:39 ` [PATCH v5 2/3] usb: dwc2: Add delay to core soft reset John Youn 2016-09-08 2:39 ` John Youn 2016-09-08 2:39 ` John Youn [this message] 2016-09-08 2:39 ` [PATCH v5 3/3] usb: dwc2: Properly account for the force mode delays John Youn [not found] ` <b4aac4b197241b8199c5300656d245692eb45856.1473302184.git.johnyoun-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> 2016-09-11 21:19 ` Heiko Stuebner 2016-09-12 5:20 ` Stefan Wahren [not found] ` <1336050364.27663.591ba3c4-a2b5-418f-9999-6b3cd631f440.open-xchange-7tX72C7vayboQLBSYMtkGA@public.gmane.org> 2016-09-12 11:05 ` Heiko Stuebner 2016-09-13 18:07 ` Stefan Wahren [not found] ` <19473401.122600.97acfbc9-df96-4427-b533-911010ce5c3f.open-xchange-7tX72C7vayboQLBSYMtkGA@public.gmane.org> 2016-09-13 18:39 ` Heiko Stübner 2016-09-13 19:04 ` John Youn [not found] ` <97a3539d-7176-086f-71f9-371d8d4b016c-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> 2016-09-14 14:05 ` Heiko Stübner 2016-09-14 21:10 ` John Youn [not found] ` <6b0c9143-63b3-c5c3-7122-bbbb0c9f610b-HKixBCOQz3hWk0Htik3J/w@public.gmane.org> 2016-09-15 7:08 ` Stefan Wahren [not found] ` <ad02126f-6c0e-9216-f7ab-ec528eeda2e2-eS4NqCHxEME@public.gmane.org> 2016-09-15 19:39 ` John Youn 2016-09-16 2:16 ` John Youn
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