[PATCH v2] soc: imx: gpcv2: Assert reset before ungating clock

[PATCH v2] soc: imx: gpcv2: Assert reset before ungating clock

[Marek Vasut]

In case the power domain clock are ungated before the reset is asserted,
the system might freeze completely. This is likely due to a device is an
undefined state being attached to bus, which sporadically leads to a bus
hang. Assert the reset before the clock are enabled to assure the device
is in defined state before being attached to bus.

Fixes: fe58c887fb8ca ("soc: imx: gpcv2: add support for optional resets")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
To: linux-arm-kernel@lists.infradead.org
---
V2: - Always assert the reset before enabling clock
    - Update commit message
    - Add Fixes tag
---
 drivers/soc/imx/gpcv2.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 85aa86e1338af..f38a4420e94a6 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -333,6 +333,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		}
 	}
 
+	reset_control_assert(domain->reset);
+
+	/* delays for reset to propagate */
+	udelay(5);
+
 	/* Enable reset clocks for all devices in the domain */
 	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
 	if (ret) {
@@ -340,8 +345,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
 		goto out_regulator_disable;
 	}
 
-	reset_control_assert(domain->reset);
-
 	if (domain->bits.pxx) {
 		/* request the domain to power up */
 		regmap_update_bits(domain->regmap, domain->regs->pup,
-- 
2.35.1


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Re: [PATCH v2] soc: imx: gpcv2: Assert reset before ungating clock

[Lucas Stach]

Am Mittwoch, dem 03.08.2022 um 01:37 +0200 schrieb Marek Vasut:
> In case the power domain clock are ungated before the reset is asserted,
> the system might freeze completely. This is likely due to a device is an
> undefined state being attached to bus, which sporadically leads to a bus
> hang. Assert the reset before the clock are enabled to assure the device
> is in defined state before being attached to bus.
> 
> Fixes: fe58c887fb8ca ("soc: imx: gpcv2: add support for optional resets")
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> To: linux-arm-kernel@lists.infradead.org
> ---
> V2: - Always assert the reset before enabling clock
>     - Update commit message
>     - Add Fixes tag
> ---
>  drivers/soc/imx/gpcv2.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 85aa86e1338af..f38a4420e94a6 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -333,6 +333,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>  		}
>  	}
>  
> +	reset_control_assert(domain->reset);
> +
> +	/* delays for reset to propagate */
> +	udelay(5);
> +
Most peripheral resets in the i.MX are synchronous, so they won't
propagate without the clocks being enabled. If this delay is really
necessary, it should be placed after the clock enable below.

Regards,
Lucas

>  	/* Enable reset clocks for all devices in the domain */
>  	ret = clk_bulk_prepare_enable(domain->num_clks, domain->clks);
>  	if (ret) {
> @@ -340,8 +345,6 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>  		goto out_regulator_disable;
>  	}
>  
> -	reset_control_assert(domain->reset);
> -
>  	if (domain->bits.pxx) {
>  		/* request the domain to power up */
>  		regmap_update_bits(domain->regmap, domain->regs->pup,



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