[PATCH 1/5] drm/amdgpu/sdma4: drop unused register header

[PATCH 1/5] drm/amdgpu/sdma4: drop unused register header

[Alex Deucher]

nbio registers are not used in this file.

Cc: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 5c24708..7cb5320 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -35,7 +35,6 @@
 #include "vega10/MMHUB/mmhub_1_0_offset.h"
 #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
 #include "vega10/HDP/hdp_4_0_offset.h"
-#include "vega10/NBIO/nbio_6_1_offset.h"
 #include "raven1/SDMA0/sdma0_4_1_default.h"
 
 #include "soc15_common.h"
-- 
2.5.5

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[PATCH 2/5] drm/amdgpu/sdma4: set wptr shadow atomically

[Alex Deucher]

No functional change until wptr polling uses this
location (future patch).

Cc: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 7cb5320..9392799 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -301,8 +301,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 				lower_32_bits(ring->wptr << 2),
 				upper_32_bits(ring->wptr << 2));
 		/* XXX check if swapping is necessary on BE */
-		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
-		adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
+		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs],
+			     (ring->wptr << 2));
 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 				ring->doorbell_index, ring->wptr << 2);
 
-- 
2.5.5

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[PATCH 3/5] drm/amdgpu/sdma4: drop hdp flush from wptr shadow update

[Alex Deucher]

The wb buffer is in system memory, not vram so the flush
is useless.

Cc: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 9392799..3ffdf88 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -312,7 +312,6 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 					offset = adev->sdma.instance[i].poll_mem_offs;
 					atomic64_set((atomic64_t *)&adev->wb.wb[offset],
 						     (ring->wptr << 2));
-					nbio_v6_1_hdp_flush(adev);
 				}
 			}
 		}
-- 
2.5.5

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[PATCH 4/5] drm/amdgpu/sdma4: drop allocation of poll_mem_offs

[Alex Deucher]

We already allocate this as part of the ring structure,
use that instead.

Cc: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    |  1 -
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 45 +++++++---------------------------
 2 files changed, 9 insertions(+), 37 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 89f7b4f..5f8d2e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1209,7 +1209,6 @@ struct amdgpu_sdma_instance {
 
 	struct amdgpu_ring	ring;
 	bool			burst_nop;
-	uint32_t		poll_mem_offs;
 };
 
 struct amdgpu_sdma {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3ffdf88..7a88264 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -287,8 +287,6 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring *ring)
  */
 static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 {
-	int i;
-	u32 offset;
 	struct amdgpu_device *adev = ring->adev;
 
 	DRM_DEBUG("Setting write pointer\n");
@@ -305,16 +303,6 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
 			     (ring->wptr << 2));
 		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 				ring->doorbell_index, ring->wptr << 2);
-
-		if (amdgpu_sriov_vf(adev)) {
-			for (i = 0; i < adev->sdma.num_instances; i++) {
-				if (&adev->sdma.instance[i].ring == ring) {
-					offset = adev->sdma.instance[i].poll_mem_offs;
-					atomic64_set((atomic64_t *)&adev->wb.wb[offset],
-						     (ring->wptr << 2));
-				}
-			}
-		}
 		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 	} else {
 		int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
@@ -585,12 +573,13 @@ static void sdma_v4_0_enable(struct amdgpu_device *adev, bool enable)
 static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 {
 	struct amdgpu_ring *ring;
-	u32 rb_cntl, ib_cntl, wptr_poll_addr_lo, wptr_poll_addr_hi, wptr_poll_cntl;
+	u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 	u32 rb_bufsz;
-	u32 wb_offset, poll_offset;
+	u32 wb_offset;
 	u32 doorbell;
 	u32 doorbell_offset;
 	u32 temp;
+	u64 wptr_gpu_addr;
 	int i, r;
 
 	for (i = 0; i < adev->sdma.num_instances; i++) {
@@ -701,17 +690,14 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 			amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 
 		if (amdgpu_sriov_vf(adev)) {
-			poll_offset = adev->sdma.instance[i].poll_mem_offs * 4;
-
+			wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 			wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
-			wptr_poll_addr_lo = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO));
-			wptr_poll_addr_lo = REG_SET_FIELD(wptr_poll_addr_lo, SDMA0_GFX_RB_WPTR_POLL_ADDR_LO, ADDR,
-								lower_32_bits(adev->wb.gpu_addr + poll_offset) >> 2);
-			wptr_poll_addr_hi = upper_32_bits(adev->wb.gpu_addr + poll_offset);
 			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
 
-			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), wptr_poll_addr_lo);
-			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), wptr_poll_addr_hi);
+			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+			       lower_32_bits(wptr_gpu_addr));
+			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+			       upper_32_bits(wptr_gpu_addr));
 			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
 		}
 	}
@@ -1274,15 +1260,6 @@ static int sdma_v4_0_sw_init(void *handle)
 				     (i == 0) ?
 				     AMDGPU_SDMA_IRQ_TRAP0 :
 				     AMDGPU_SDMA_IRQ_TRAP1);
-
-		if (amdgpu_sriov_vf(adev)) {
-			r = amdgpu_wb_get_64bit(adev,
-						&adev->sdma.instance[i].poll_mem_offs);
-			if (r) {
-				dev_err(adev->dev, "(%d) failed to allocate SDMA poll mem wb.\n", r);
-				return r;
-			}
-		}
 		if (r)
 			return r;
 	}
@@ -1295,13 +1272,9 @@ static int sdma_v4_0_sw_fini(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int i;
 
-	for (i = 0; i < adev->sdma.num_instances; i++) {
+	for (i = 0; i < adev->sdma.num_instances; i++)
 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
-		if (amdgpu_sriov_vf(adev))
-			amdgpu_wb_free_64bit(adev,
-					     adev->sdma.instance[i].poll_mem_offs);
-	}
 	return 0;
 }
 
-- 
2.5.5

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[PATCH 5/5] drm/amdgpu/sdma4: move wptr polling setup

[Alex Deucher]

Move it up before ring enablement with all of the other
engine setup and explicitly disable it for bare metal.

Cc: Frank Min <Frank.Min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 24 +++++++++++++-----------
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 7a88264..87a3ca1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -661,6 +661,19 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_F32_CNTL), temp);
 		}
 
+		/* setup the wptr shadow polling */
+		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
+		WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+		       lower_32_bits(wptr_gpu_addr));
+		WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+		       upper_32_bits(wptr_gpu_addr));
+		wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
+		if (amdgpu_sriov_vf(adev))
+			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
+		else
+			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 0);
+		WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
+
 		/* enable DMA RB */
 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 		WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
@@ -689,17 +702,6 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
 		if (adev->mman.buffer_funcs_ring == ring)
 			amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size);
 
-		if (amdgpu_sriov_vf(adev)) {
-			wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
-			wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
-			wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, F32_POLL_ENABLE, 1);
-
-			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
-			       lower_32_bits(wptr_gpu_addr));
-			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
-			       upper_32_bits(wptr_gpu_addr));
-			WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), wptr_poll_cntl);
-		}
 	}
 
 	return 0;
-- 
2.5.5

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Re: [PATCH 2/5] drm/amdgpu/sdma4: set wptr shadow atomically

[Felix Kuehling]

On 17-07-27 03:46 PM, Alex Deucher wrote:
> No functional change until wptr polling uses this
> location (future patch).
>
> Cc: Frank Min <Frank.Min@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 7cb5320..9392799 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -301,8 +301,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
>  				lower_32_bits(ring->wptr << 2),
>  				upper_32_bits(ring->wptr << 2));
>  		/* XXX check if swapping is necessary on BE */
> -		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
> -		adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
> +		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs],
> +			     (ring->wptr << 2));

This looks a bit awkward. Would "writeq" do the job? That's what we use
for updating kernel queue doorbells in KFD.

The generic implementation of atomic64_set uses a spinlock. But that
doesn't do anything for protecting against concurrent access by the GPU
hardware.

Regards,
  Felix

>  		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
>  				ring->doorbell_index, ring->wptr << 2);
>  

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Re: [PATCH 2/5] drm/amdgpu/sdma4: set wptr shadow atomically

[Alex Deucher]

On Thu, Jul 27, 2017 at 4:39 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
>
> On 17-07-27 03:46 PM, Alex Deucher wrote:
>> No functional change until wptr polling uses this
>> location (future patch).
>>
>> Cc: Frank Min <Frank.Min@amd.com>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> index 7cb5320..9392799 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> @@ -301,8 +301,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
>>                               lower_32_bits(ring->wptr << 2),
>>                               upper_32_bits(ring->wptr << 2));
>>               /* XXX check if swapping is necessary on BE */
>> -             adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
>> -             adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
>> +             atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs],
>> +                          (ring->wptr << 2));
>
> This looks a bit awkward. Would "writeq" do the job? That's what we use
> for updating kernel queue doorbells in KFD.

Probably.  We just want to make sure the whole 64 bit value is updated
before the GPU polls the value.

Alex

>
> The generic implementation of atomic64_set uses a spinlock. But that
> doesn't do anything for protecting against concurrent access by the GPU
> hardware.
>
> Regards,
>   Felix
>
>>               DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
>>                               ring->doorbell_index, ring->wptr << 2);
>>
>
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> amd-gfx@lists.freedesktop.org
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Re: [PATCH 2/5] drm/amdgpu/sdma4: set wptr shadow atomically

[Christian König]

Am 27.07.2017 um 22:50 schrieb Alex Deucher:
> On Thu, Jul 27, 2017 at 4:39 PM, Felix Kuehling <felix.kuehling@amd.com> wrote:
>> On 17-07-27 03:46 PM, Alex Deucher wrote:
>>> No functional change until wptr polling uses this
>>> location (future patch).
>>>
>>> Cc: Frank Min <Frank.Min@amd.com>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++--
>>>   1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> index 7cb5320..9392799 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> @@ -301,8 +301,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring *ring)
>>>                                lower_32_bits(ring->wptr << 2),
>>>                                upper_32_bits(ring->wptr << 2));
>>>                /* XXX check if swapping is necessary on BE */
>>> -             adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
>>> -             adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
>>> +             atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs],
>>> +                          (ring->wptr << 2));
>> This looks a bit awkward. Would "writeq" do the job? That's what we use
>> for updating kernel queue doorbells in KFD.
> Probably.  We just want to make sure the whole 64 bit value is updated
> before the GPU polls the value.

writeq is for iomem and does endian conversion IIRC.

How about WRITE_ONCE()?

Christian.

>
> Alex
>
>> The generic implementation of atomic64_set uses a spinlock. But that
>> doesn't do anything for protecting against concurrent access by the GPU
>> hardware.
>>
>> Regards,
>>    Felix
>>
>>>                DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
>>>                                ring->doorbell_index, ring->wptr << 2);
>>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx


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Re: [PATCH 1/5] drm/amdgpu/sdma4: drop unused register header

[Christian König]

Am 27.07.2017 um 21:46 schrieb Alex Deucher:
> nbio registers are not used in this file.
>
> Cc: Frank Min <Frank.Min@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

Patches #1 and #3-#5 are Reviewed-by: Christian König 
<christian.koenig@amd.com>.

I agree with Felix that #2 looks a bit ugly, but using writeq doesn't 
sounds like the correct answer either.

If WRITE_ONCE() does the job then I would use that one.

Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 5c24708..7cb5320 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -35,7 +35,6 @@
>   #include "vega10/MMHUB/mmhub_1_0_offset.h"
>   #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
>   #include "vega10/HDP/hdp_4_0_offset.h"
> -#include "vega10/NBIO/nbio_6_1_offset.h"
>   #include "raven1/SDMA0/sdma0_4_1_default.h"
>   
>   #include "soc15_common.h"


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