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From: Lucas Stach <l.stach@pengutronix.de>
To: Richard Zhu <hongxing.zhu@nxp.com>,
	kishon@ti.com, vkoul@kernel.org, robh@kernel.org,
	galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: Re: [PATCH v2 3/4] arm64: dts: imx8mm: add the pcie phy support
Date: Mon, 27 Sep 2021 10:35:09 +0200	[thread overview]
Message-ID: <b7604aa25a5d6746025fadeea42a7cc4b5f884ff.camel@pengutronix.de> (raw)
In-Reply-To: <1632641983-1455-4-git-send-email-hongxing.zhu@nxp.com>

Am Sonntag, dem 26.09.2021 um 15:39 +0800 schrieb Richard Zhu:
> Add the PCIe PHY support on iMX8MM platforms.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |  4 ++++
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 12 ++++++++++++

This should be split into 2 patches: one for the SoC and one for the
EVK board.

>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index e033d0257b5a..e7f398433486 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -289,6 +289,10 @@ pca6416: gpio@20 {
>  	};
>  };
>  
> +&pcie_phy {
> +	status = "okay";
> +};
> +
>  &sai3 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_sai3>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index e7648c3b8390..de231d531ba4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -998,6 +998,18 @@ usbmisc2: usbmisc@32e50200 {
>  				reg = <0x32e50200 0x200>;
>  			};
>  
> +			pcie_phy: pcie-phy@32f00000 {
> +				compatible = "fsl,imx8mm-pcie-phy";
> +				reg = <0x32f00000 0x10000>;
> +				clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				clock-names = "phy";
> +				assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				assigned-clock-rates = <100000000>;
> +				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
> +				#phy-cells = <0>;
> +				fsl,refclk-pad-mode = <1>;

Move this to the board DT, as the pad mode is a board level decision.
Also use the enum instead of raw value.

> +				status = "disabled";
> +			};
>  		};
>  
>  		dma_apbh: dma-controller@33000000 {



WARNING: multiple messages have this Message-ID (diff)
From: Lucas Stach <l.stach@pengutronix.de>
To: Richard Zhu <hongxing.zhu@nxp.com>,
	kishon@ti.com, vkoul@kernel.org,  robh@kernel.org,
	galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,  kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: Re: [PATCH v2 3/4] arm64: dts: imx8mm: add the pcie phy support
Date: Mon, 27 Sep 2021 10:35:09 +0200	[thread overview]
Message-ID: <b7604aa25a5d6746025fadeea42a7cc4b5f884ff.camel@pengutronix.de> (raw)
In-Reply-To: <1632641983-1455-4-git-send-email-hongxing.zhu@nxp.com>

Am Sonntag, dem 26.09.2021 um 15:39 +0800 schrieb Richard Zhu:
> Add the PCIe PHY support on iMX8MM platforms.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |  4 ++++
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 12 ++++++++++++

This should be split into 2 patches: one for the SoC and one for the
EVK board.

>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index e033d0257b5a..e7f398433486 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -289,6 +289,10 @@ pca6416: gpio@20 {
>  	};
>  };
>  
> +&pcie_phy {
> +	status = "okay";
> +};
> +
>  &sai3 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_sai3>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index e7648c3b8390..de231d531ba4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -998,6 +998,18 @@ usbmisc2: usbmisc@32e50200 {
>  				reg = <0x32e50200 0x200>;
>  			};
>  
> +			pcie_phy: pcie-phy@32f00000 {
> +				compatible = "fsl,imx8mm-pcie-phy";
> +				reg = <0x32f00000 0x10000>;
> +				clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				clock-names = "phy";
> +				assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				assigned-clock-rates = <100000000>;
> +				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
> +				#phy-cells = <0>;
> +				fsl,refclk-pad-mode = <1>;

Move this to the board DT, as the pad mode is a board level decision.
Also use the enum instead of raw value.

> +				status = "disabled";
> +			};
>  		};
>  
>  		dma_apbh: dma-controller@33000000 {



-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Lucas Stach <l.stach@pengutronix.de>
To: Richard Zhu <hongxing.zhu@nxp.com>,
	kishon@ti.com, vkoul@kernel.org,  robh@kernel.org,
	galak@kernel.crashing.org, shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,  kernel@pengutronix.de,
	linux-imx@nxp.com
Subject: Re: [PATCH v2 3/4] arm64: dts: imx8mm: add the pcie phy support
Date: Mon, 27 Sep 2021 10:35:09 +0200	[thread overview]
Message-ID: <b7604aa25a5d6746025fadeea42a7cc4b5f884ff.camel@pengutronix.de> (raw)
In-Reply-To: <1632641983-1455-4-git-send-email-hongxing.zhu@nxp.com>

Am Sonntag, dem 26.09.2021 um 15:39 +0800 schrieb Richard Zhu:
> Add the PCIe PHY support on iMX8MM platforms.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |  4 ++++
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi     | 12 ++++++++++++

This should be split into 2 patches: one for the SoC and one for the
EVK board.

>  2 files changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> index e033d0257b5a..e7f398433486 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
> @@ -289,6 +289,10 @@ pca6416: gpio@20 {
>  	};
>  };
>  
> +&pcie_phy {
> +	status = "okay";
> +};
> +
>  &sai3 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_sai3>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index e7648c3b8390..de231d531ba4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -998,6 +998,18 @@ usbmisc2: usbmisc@32e50200 {
>  				reg = <0x32e50200 0x200>;
>  			};
>  
> +			pcie_phy: pcie-phy@32f00000 {
> +				compatible = "fsl,imx8mm-pcie-phy";
> +				reg = <0x32f00000 0x10000>;
> +				clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				clock-names = "phy";
> +				assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
> +				assigned-clock-rates = <100000000>;
> +				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
> +				#phy-cells = <0>;
> +				fsl,refclk-pad-mode = <1>;

Move this to the board DT, as the pad mode is a board level decision.
Also use the enum instead of raw value.

> +				status = "disabled";
> +			};
>  		};
>  
>  		dma_apbh: dma-controller@33000000 {



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-09-27  8:35 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-26  7:39 [PATCH v2 0/4] add the imx8 pcie phy driver support Richard Zhu
2021-09-26  7:39 ` Richard Zhu
2021-09-26  7:39 ` Richard Zhu
2021-09-26  7:39 ` [PATCH v2 1/4] dt-bindings: phy: phy-imx8-pcie: Add binding for the pad modes of imx8 pcie phy Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-27  8:27   ` Lucas Stach
2021-09-27  8:27     ` Lucas Stach
2021-09-27  8:27     ` Lucas Stach
2021-09-28  2:28     ` Richard Zhu
2021-09-28  2:28       ` Richard Zhu
2021-09-28  2:28       ` Richard Zhu
2021-09-26  7:39 ` [PATCH v2 2/4] dt-bindings: phy: add imx8 pcie phy driver support Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-27  8:32   ` Lucas Stach
2021-09-27  8:32     ` Lucas Stach
2021-09-27  8:32     ` Lucas Stach
2021-09-28  2:37     ` Richard Zhu
2021-09-28  2:37       ` Richard Zhu
2021-09-28  2:37       ` Richard Zhu
2021-09-26  7:39 ` [PATCH v2 3/4] arm64: dts: imx8mm: add the pcie phy support Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-27  8:35   ` Lucas Stach [this message]
2021-09-27  8:35     ` Lucas Stach
2021-09-27  8:35     ` Lucas Stach
2021-09-28  2:38     ` Richard Zhu
2021-09-28  2:38       ` Richard Zhu
2021-09-28  2:38       ` Richard Zhu
2021-09-26  7:39 ` [PATCH v2 4/4] phy: freescale: pcie: initialize the imx8 pcie standalone phy driver Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-26  7:39   ` Richard Zhu
2021-09-27  8:43   ` Lucas Stach
2021-09-27  8:43     ` Lucas Stach
2021-09-27  8:43     ` Lucas Stach
2021-09-28  7:09     ` Richard Zhu
2021-09-28  7:09       ` Richard Zhu
2021-09-28  7:09       ` Richard Zhu
2021-09-28  8:43       ` Lucas Stach
2021-09-28  8:43         ` Lucas Stach
2021-09-28  8:43         ` Lucas Stach
2021-10-11  7:47         ` Richard Zhu
2021-10-11  7:47           ` Richard Zhu
2021-10-11  7:47           ` Richard Zhu

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