* [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues
@ 2022-09-14 10:11 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis via @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
ROM flow. This series makes it more configurguable from the command line
and fixes the default.
Alistair Francis (3):
target/riscv: Set the CPU resetvec directly
hw/riscv: opentitan: Fixup resetvec
hw/riscv: opentitan: Expose the resetvec as a SoC property
include/hw/riscv/opentitan.h | 2 ++
target/riscv/cpu.h | 3 +--
hw/riscv/opentitan.c | 8 +++++++-
target/riscv/cpu.c | 13 +++----------
target/riscv/machine.c | 6 +++---
5 files changed, 16 insertions(+), 16 deletions(-)
--
2.37.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues
@ 2022-09-14 10:11 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
ROM flow. This series makes it more configurguable from the command line
and fixes the default.
Alistair Francis (3):
target/riscv: Set the CPU resetvec directly
hw/riscv: opentitan: Fixup resetvec
hw/riscv: opentitan: Expose the resetvec as a SoC property
include/hw/riscv/opentitan.h | 2 ++
target/riscv/cpu.h | 3 +--
hw/riscv/opentitan.c | 8 +++++++-
target/riscv/cpu.c | 13 +++----------
target/riscv/machine.c | 6 +++---
5 files changed, 16 insertions(+), 16 deletions(-)
--
2.37.2
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/3] target/riscv: Set the CPU resetvec directly
2022-09-14 10:11 ` Alistair Francis
@ 2022-09-14 10:11 ` Alistair Francis
-1 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis via @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
Instead of using our properties to set a config value which then might
be used to set the resetvec (depending on your timing), let's instead
just set the resetvec directly in the env struct.
This allows us to set the reset vec from the command line with:
-global driver=riscv.hart_array,property=resetvec,value=0x20000400
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 +--
target/riscv/cpu.c | 13 +++----------
target/riscv/machine.c | 6 +++---
3 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 06751e1e3e..22344a620b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -190,7 +190,7 @@ struct CPUArchState {
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
target_ulong geilen;
- target_ulong resetvec;
+ uint64_t resetvec;
target_ulong mhartid;
/*
@@ -474,7 +474,6 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool debug;
- uint64_t resetvec;
bool short_isa_string;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aee14a239a..b29c88b9f0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -228,13 +228,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
env->vext_ver = vext_ver;
}
-static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
-{
-#ifndef CONFIG_USER_ONLY
- env->resetvec = resetvec;
-#endif
-}
-
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -336,7 +329,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
cpu->cfg.mmu = false;
}
#endif
@@ -676,7 +668,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_set_feature(env, RISCV_FEATURE_DEBUG);
}
- set_resetvec(env, cpu->cfg.resetvec);
#ifndef CONFIG_USER_ONLY
if (cpu->cfg.ext_sstc) {
@@ -1079,7 +1070,9 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
- DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+#ifndef CONFIG_USER_ONLY
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
+#endif
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 41098f6ad0..c4e6b3bba4 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -308,8 +308,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 4,
- .minimum_version_id = 4,
+ .version_id = 5,
+ .minimum_version_id = 5,
.post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -331,7 +331,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT32(env.features, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_UINTTL(env.virt, RISCVCPU),
- VMSTATE_UINTTL(env.resetvec, RISCVCPU),
+ VMSTATE_UINT64(env.resetvec, RISCVCPU),
VMSTATE_UINTTL(env.mhartid, RISCVCPU),
VMSTATE_UINT64(env.mstatus, RISCVCPU),
VMSTATE_UINT64(env.mip, RISCVCPU),
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 1/3] target/riscv: Set the CPU resetvec directly
@ 2022-09-14 10:11 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
Instead of using our properties to set a config value which then might
be used to set the resetvec (depending on your timing), let's instead
just set the resetvec directly in the env struct.
This allows us to set the reset vec from the command line with:
-global driver=riscv.hart_array,property=resetvec,value=0x20000400
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 3 +--
target/riscv/cpu.c | 13 +++----------
target/riscv/machine.c | 6 +++---
3 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 06751e1e3e..22344a620b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -190,7 +190,7 @@ struct CPUArchState {
/* This contains QEMU specific information about the virt state. */
target_ulong virt;
target_ulong geilen;
- target_ulong resetvec;
+ uint64_t resetvec;
target_ulong mhartid;
/*
@@ -474,7 +474,6 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool debug;
- uint64_t resetvec;
bool short_isa_string;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index aee14a239a..b29c88b9f0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -228,13 +228,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver)
env->vext_ver = vext_ver;
}
-static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
-{
-#ifndef CONFIG_USER_ONLY
- env->resetvec = resetvec;
-#endif
-}
-
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -336,7 +329,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
cpu->cfg.mmu = false;
}
#endif
@@ -676,7 +668,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_set_feature(env, RISCV_FEATURE_DEBUG);
}
- set_resetvec(env, cpu->cfg.resetvec);
#ifndef CONFIG_USER_ONLY
if (cpu->cfg.ext_sstc) {
@@ -1079,7 +1070,9 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
- DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+#ifndef CONFIG_USER_ONLY
+ DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
+#endif
DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 41098f6ad0..c4e6b3bba4 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -308,8 +308,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
const VMStateDescription vmstate_riscv_cpu = {
.name = "cpu",
- .version_id = 4,
- .minimum_version_id = 4,
+ .version_id = 5,
+ .minimum_version_id = 5,
.post_load = riscv_cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -331,7 +331,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT32(env.features, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_UINTTL(env.virt, RISCVCPU),
- VMSTATE_UINTTL(env.resetvec, RISCVCPU),
+ VMSTATE_UINT64(env.resetvec, RISCVCPU),
VMSTATE_UINTTL(env.mhartid, RISCVCPU),
VMSTATE_UINT64(env.mstatus, RISCVCPU),
VMSTATE_UINT64(env.mip, RISCVCPU),
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/3] hw/riscv: opentitan: Fixup resetvec
2022-09-14 10:11 ` Alistair Francis
@ 2022-09-14 10:11 ` Alistair Francis
-1 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis via @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
The resetvec for the OpenTitan machine ended up being set to an out of
date value, so let's fix that and bump it to the correct start address
(after the boot ROM)
Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version"
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index af13dbe3b1..45c92c9bbc 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490,
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/3] hw/riscv: opentitan: Fixup resetvec
@ 2022-09-14 10:11 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
The resetvec for the OpenTitan machine ended up being set to an out of
date value, so let's fix that and bump it to the correct start address
(after the boot ROM)
Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version"
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index af13dbe3b1..45c92c9bbc 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490,
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
2022-09-14 10:11 ` Alistair Francis
@ 2022-09-14 10:11 ` Alistair Francis
-1 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis via @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
QEMU we don't run the ROM code and instead just jump to the next stage.
This means we need to be a little more flexible about what the resetvec
is.
This patch allows us to set the resetvec from the command line with
something like this:
-global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400
This way as the next stage changes we can update the resetvec.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 8 +++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 26d960f288..6665cd5794 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -46,6 +46,8 @@ struct LowRISCIbexSoCState {
IbexTimerState timer;
IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
+ uint32_t resetvec;
+
MemoryRegion flash_mem;
MemoryRegion rom;
MemoryRegion flash_alias;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 45c92c9bbc..be7ff1eea0 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
@@ -297,10 +297,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
}
+static Property lowrisc_ibex_soc_props[] = {
+ DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, lowrisc_ibex_soc_props);
dc->realize = lowrisc_ibex_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
@ 2022-09-14 10:11 ` Alistair Francis
0 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2022-09-14 10:11 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, Alistair Francis, bmeng.cn,
Alistair Francis, alistair23
On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
QEMU we don't run the ROM code and instead just jump to the next stage.
This means we need to be a little more flexible about what the resetvec
is.
This patch allows us to set the resetvec from the command line with
something like this:
-global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400
This way as the next stage changes we can update the resetvec.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/opentitan.h | 2 ++
hw/riscv/opentitan.c | 8 +++++++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 26d960f288..6665cd5794 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -46,6 +46,8 @@ struct LowRISCIbexSoCState {
IbexTimerState timer;
IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
+ uint32_t resetvec;
+
MemoryRegion flash_mem;
MemoryRegion rom;
MemoryRegion flash_alias;
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 45c92c9bbc..be7ff1eea0 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", s->resetvec,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
@@ -297,10 +297,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
}
+static Property lowrisc_ibex_soc_props[] = {
+ DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400),
+ DEFINE_PROP_END_OF_LIST()
+};
+
static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ device_class_set_props(dc, lowrisc_ibex_soc_props);
dc->realize = lowrisc_ibex_soc_realize;
/* Reason: Uses serial_hds in realize function, thus can't be used twice */
dc->user_creatable = false;
--
2.37.2
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly
2022-09-14 10:11 ` Alistair Francis
(?)
@ 2022-09-17 0:53 ` Wilfred Mallawa
-1 siblings, 0 replies; 17+ messages in thread
From: Wilfred Mallawa @ 2022-09-17 0:53 UTC (permalink / raw)
To: qemu-riscv, Alistair Francis, qemu-devel
Cc: palmer, bin.meng, bmeng.cn, alistair23
On Wed, 2022-09-14 at 12:11 +0200, Alistair Francis via wrote:
> Instead of using our properties to set a config value which then
> might
> be used to set the resetvec (depending on your timing), let's instead
> just set the resetvec directly in the env struct.
>
> This allows us to set the reset vec from the command line with:
> -global
> driver=riscv.hart_array,property=resetvec,value=0x20000400
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 3 +--
> target/riscv/cpu.c | 13 +++----------
> target/riscv/machine.c | 6 +++---
> 3 files changed, 7 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 06751e1e3e..22344a620b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -190,7 +190,7 @@ struct CPUArchState {
> /* This contains QEMU specific information about the virt state.
> */
> target_ulong virt;
> target_ulong geilen;
> - target_ulong resetvec;
> + uint64_t resetvec;
>
> target_ulong mhartid;
> /*
> @@ -474,7 +474,6 @@ struct RISCVCPUConfig {
> bool pmp;
> bool epmp;
> bool debug;
> - uint64_t resetvec;
>
> bool short_isa_string;
> };
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index aee14a239a..b29c88b9f0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -228,13 +228,6 @@ static void set_vext_version(CPURISCVState *env,
> int vext_ver)
> env->vext_ver = vext_ver;
> }
>
> -static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
> -{
> -#ifndef CONFIG_USER_ONLY
> - env->resetvec = resetvec;
> -#endif
> -}
> -
> static void riscv_any_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -336,7 +329,6 @@ static void rv32_imafcu_nommu_cpu_init(Object
> *obj)
>
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> cpu->cfg.mmu = false;
> }
> #endif
> @@ -676,7 +668,6 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> riscv_set_feature(env, RISCV_FEATURE_DEBUG);
> }
>
> - set_resetvec(env, cpu->cfg.resetvec);
>
> #ifndef CONFIG_USER_ONLY
> if (cpu->cfg.ext_sstc) {
> @@ -1079,7 +1070,9 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid,
> RISCV_CPU_MARCHID),
> DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid,
> RISCV_CPU_MIMPID),
>
> - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec,
> DEFAULT_RSTVEC),
> +#ifndef CONFIG_USER_ONLY
> + DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec,
> DEFAULT_RSTVEC),
> +#endif
>
> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU,
> cfg.short_isa_string, false),
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 41098f6ad0..c4e6b3bba4 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -308,8 +308,8 @@ static const VMStateDescription
> vmstate_pmu_ctr_state = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 4,
> - .minimum_version_id = 4,
> + .version_id = 5,
> + .minimum_version_id = 5,
> .post_load = riscv_cpu_post_load,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -331,7 +331,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINT32(env.features, RISCVCPU),
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> VMSTATE_UINTTL(env.virt, RISCVCPU),
> - VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> + VMSTATE_UINT64(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> VMSTATE_UINT64(env.mip, RISCVCPU),
Reviewed by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/3] hw/riscv: opentitan: Fixup resetvec
2022-09-14 10:11 ` Alistair Francis
(?)
@ 2022-09-17 0:53 ` Wilfred Mallawa
-1 siblings, 0 replies; 17+ messages in thread
From: Wilfred Mallawa @ 2022-09-17 0:53 UTC (permalink / raw)
To: qemu-riscv, Alistair Francis, qemu-devel
Cc: palmer, bin.meng, bmeng.cn, alistair23
On Wed, 2022-09-14 at 12:11 +0200, Alistair Francis via wrote:
> The resetvec for the OpenTitan machine ended up being set to an out
> of
> date value, so let's fix that and bump it to the correct start
> address
> (after the boot ROM)
>
> Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version"
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/riscv/opentitan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index af13dbe3b1..45c92c9bbc 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState
> *dev_soc, Error **errp)
> &error_abort);
> object_property_set_int(OBJECT(&s->cpus), "num-harts", ms-
> >smp.cpus,
> &error_abort);
> - object_property_set_int(OBJECT(&s->cpus), "resetvec",
> 0x20000490,
> + object_property_set_int(OBJECT(&s->cpus), "resetvec",
> 0x20000400,
> &error_abort);
> sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
>
Reviewed by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
2022-09-14 10:11 ` Alistair Francis
(?)
@ 2022-09-17 0:57 ` Wilfred Mallawa
-1 siblings, 0 replies; 17+ messages in thread
From: Wilfred Mallawa @ 2022-09-17 0:57 UTC (permalink / raw)
To: qemu-riscv, Alistair Francis, qemu-devel
Cc: palmer, bin.meng, bmeng.cn, alistair23
On Wed, 2022-09-14 at 12:11 +0200, Alistair Francis via wrote:
> On the OpenTitan hardware the resetvec is fixed at the start of ROM.
> In
> QEMU we don't run the ROM code and instead just jump to the next
> stage.
> This means we need to be a little more flexible about what the
> resetvec
> is.
>
> This patch allows us to set the resetvec from the command line with
> something like this:
> -global
> driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400
>
> This way as the next stage changes we can update the resetvec.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 2 ++
> hw/riscv/opentitan.c | 8 +++++++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/riscv/opentitan.h
> b/include/hw/riscv/opentitan.h
> index 26d960f288..6665cd5794 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -46,6 +46,8 @@ struct LowRISCIbexSoCState {
> IbexTimerState timer;
> IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
>
> + uint32_t resetvec;
> +
> MemoryRegion flash_mem;
> MemoryRegion rom;
> MemoryRegion flash_alias;
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 45c92c9bbc..be7ff1eea0 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState
> *dev_soc, Error **errp)
> &error_abort);
> object_property_set_int(OBJECT(&s->cpus), "num-harts", ms-
> >smp.cpus,
> &error_abort);
> - object_property_set_int(OBJECT(&s->cpus), "resetvec",
> 0x20000400,
> + object_property_set_int(OBJECT(&s->cpus), "resetvec", s-
> >resetvec,
> &error_abort);
> sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
>
> @@ -297,10 +297,16 @@ static void
> lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size);
> }
>
> +static Property lowrisc_ibex_soc_props[] = {
> + DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec,
> 0x20000400),
> + DEFINE_PROP_END_OF_LIST()
> +};
> +
> static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> + device_class_set_props(dc, lowrisc_ibex_soc_props);
> dc->realize = lowrisc_ibex_soc_realize;
> /* Reason: Uses serial_hds in realize function, thus can't be
> used twice */
> dc->user_creatable = false;
Nice! I tested this on https://github.com/tock/tock/pull/3056 , with
the addition of `global
driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000450 `
Alot more convienient with this patch for when the entry point changes,
will look into parsing the manifest to dynamically set it!
Reviewed by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly
2022-09-14 10:11 ` Alistair Francis
@ 2022-09-17 21:01 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-09-17 21:01 UTC (permalink / raw)
To: Alistair Francis, qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, bmeng.cn, alistair23
On 14/9/22 12:11, Alistair Francis via wrote:
> Instead of using our properties to set a config value which then might
> be used to set the resetvec (depending on your timing), let's instead
> just set the resetvec directly in the env struct.
>
> This allows us to set the reset vec from the command line with:
> -global driver=riscv.hart_array,property=resetvec,value=0x20000400
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 3 +--
> target/riscv/cpu.c | 13 +++----------
> target/riscv/machine.c | 6 +++---
> 3 files changed, 7 insertions(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly
@ 2022-09-17 21:01 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-09-17 21:01 UTC (permalink / raw)
To: Alistair Francis, qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, bmeng.cn, alistair23
On 14/9/22 12:11, Alistair Francis via wrote:
> Instead of using our properties to set a config value which then might
> be used to set the resetvec (depending on your timing), let's instead
> just set the resetvec directly in the env struct.
>
> This allows us to set the reset vec from the command line with:
> -global driver=riscv.hart_array,property=resetvec,value=0x20000400
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 3 +--
> target/riscv/cpu.c | 13 +++----------
> target/riscv/machine.c | 6 +++---
> 3 files changed, 7 insertions(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
2022-09-14 10:11 ` Alistair Francis
@ 2022-09-17 21:03 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-09-17 21:03 UTC (permalink / raw)
To: Alistair Francis, qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, bmeng.cn, alistair23
On 14/9/22 12:11, Alistair Francis via wrote:
> On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
> QEMU we don't run the ROM code and instead just jump to the next stage.
> This means we need to be a little more flexible about what the resetvec
> is.
>
> This patch allows us to set the resetvec from the command line with
> something like this:
> -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400
>
> This way as the next stage changes we can update the resetvec.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 2 ++
> hw/riscv/opentitan.c | 8 +++++++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
@ 2022-09-17 21:03 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-09-17 21:03 UTC (permalink / raw)
To: Alistair Francis, qemu-riscv, qemu-devel
Cc: Palmer Dabbelt, Bin Meng, bmeng.cn, alistair23
On 14/9/22 12:11, Alistair Francis via wrote:
> On the OpenTitan hardware the resetvec is fixed at the start of ROM. In
> QEMU we don't run the ROM code and instead just jump to the next stage.
> This means we need to be a little more flexible about what the resetvec
> is.
>
> This patch allows us to set the resetvec from the command line with
> something like this:
> -global driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x20000400
>
> This way as the next stage changes we can update the resetvec.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> include/hw/riscv/opentitan.h | 2 ++
> hw/riscv/opentitan.c | 8 +++++++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues
2022-09-14 10:11 ` Alistair Francis
` (3 preceding siblings ...)
(?)
@ 2022-09-19 23:33 ` Alistair Francis
-1 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2022-09-19 23:33 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Bin Meng, Bin Meng
On Wed, Sep 14, 2022 at 8:11 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The OpenTitan resetvec is dynamic on QEMU as we don't run the full boot
> ROM flow. This series makes it more configurguable from the command line
> and fixes the default.
>
> Alistair Francis (3):
> target/riscv: Set the CPU resetvec directly
> hw/riscv: opentitan: Fixup resetvec
> hw/riscv: opentitan: Expose the resetvec as a SoC property
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> include/hw/riscv/opentitan.h | 2 ++
> target/riscv/cpu.h | 3 +--
> hw/riscv/opentitan.c | 8 +++++++-
> target/riscv/cpu.c | 13 +++----------
> target/riscv/machine.c | 6 +++---
> 5 files changed, 16 insertions(+), 16 deletions(-)
>
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly
2022-09-14 10:11 ` Alistair Francis
` (2 preceding siblings ...)
(?)
@ 2022-09-27 8:29 ` Frank Chang
-1 siblings, 0 replies; 17+ messages in thread
From: Frank Chang @ 2022-09-27 8:29 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-riscv, qemu-devel, Palmer Dabbelt, Bin Meng, bmeng.cn, alistair23
[-- Attachment #1: Type: text/plain, Size: 3934 bytes --]
Reviewed-by: Frank Chang <frank.chang@sifive.com>
On Wed, Sep 14, 2022 at 6:12 PM Alistair Francis via <qemu-riscv@nongnu.org>
wrote:
> Instead of using our properties to set a config value which then might
> be used to set the resetvec (depending on your timing), let's instead
> just set the resetvec directly in the env struct.
>
> This allows us to set the reset vec from the command line with:
> -global driver=riscv.hart_array,property=resetvec,value=0x20000400
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 3 +--
> target/riscv/cpu.c | 13 +++----------
> target/riscv/machine.c | 6 +++---
> 3 files changed, 7 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 06751e1e3e..22344a620b 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -190,7 +190,7 @@ struct CPUArchState {
> /* This contains QEMU specific information about the virt state. */
> target_ulong virt;
> target_ulong geilen;
> - target_ulong resetvec;
> + uint64_t resetvec;
>
> target_ulong mhartid;
> /*
> @@ -474,7 +474,6 @@ struct RISCVCPUConfig {
> bool pmp;
> bool epmp;
> bool debug;
> - uint64_t resetvec;
>
> bool short_isa_string;
> };
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index aee14a239a..b29c88b9f0 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -228,13 +228,6 @@ static void set_vext_version(CPURISCVState *env, int
> vext_ver)
> env->vext_ver = vext_ver;
> }
>
> -static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
> -{
> -#ifndef CONFIG_USER_ONLY
> - env->resetvec = resetvec;
> -#endif
> -}
> -
> static void riscv_any_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -336,7 +329,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
>
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> set_priv_version(env, PRIV_VERSION_1_10_0);
> - set_resetvec(env, DEFAULT_RSTVEC);
> cpu->cfg.mmu = false;
> }
> #endif
> @@ -676,7 +668,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> riscv_set_feature(env, RISCV_FEATURE_DEBUG);
> }
>
> - set_resetvec(env, cpu->cfg.resetvec);
>
> #ifndef CONFIG_USER_ONLY
> if (cpu->cfg.ext_sstc) {
> @@ -1079,7 +1070,9 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid,
> RISCV_CPU_MARCHID),
> DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
>
> - DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec,
> DEFAULT_RSTVEC),
> +#ifndef CONFIG_USER_ONLY
> + DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec,
> DEFAULT_RSTVEC),
> +#endif
>
> DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string,
> false),
>
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 41098f6ad0..c4e6b3bba4 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -308,8 +308,8 @@ static const VMStateDescription vmstate_pmu_ctr_state
> = {
>
> const VMStateDescription vmstate_riscv_cpu = {
> .name = "cpu",
> - .version_id = 4,
> - .minimum_version_id = 4,
> + .version_id = 5,
> + .minimum_version_id = 5,
> .post_load = riscv_cpu_post_load,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -331,7 +331,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINT32(env.features, RISCVCPU),
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> VMSTATE_UINTTL(env.virt, RISCVCPU),
> - VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> + VMSTATE_UINT64(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> VMSTATE_UINT64(env.mip, RISCVCPU),
> --
> 2.37.2
>
>
>
[-- Attachment #2: Type: text/html, Size: 4903 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-09-27 11:25 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-14 10:11 [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues Alistair Francis via
2022-09-14 10:11 ` Alistair Francis
2022-09-14 10:11 ` [PATCH 1/3] target/riscv: Set the CPU resetvec directly Alistair Francis via
2022-09-14 10:11 ` Alistair Francis
2022-09-17 0:53 ` Wilfred Mallawa
2022-09-17 21:01 ` Philippe Mathieu-Daudé via
2022-09-17 21:01 ` Philippe Mathieu-Daudé
2022-09-27 8:29 ` Frank Chang
2022-09-14 10:11 ` [PATCH 2/3] hw/riscv: opentitan: Fixup resetvec Alistair Francis via
2022-09-14 10:11 ` Alistair Francis
2022-09-17 0:53 ` Wilfred Mallawa
2022-09-14 10:11 ` [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis via
2022-09-14 10:11 ` Alistair Francis
2022-09-17 0:57 ` Wilfred Mallawa
2022-09-17 21:03 ` Philippe Mathieu-Daudé via
2022-09-17 21:03 ` Philippe Mathieu-Daudé
2022-09-19 23:33 ` [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.