From: Samuel Holland <samuel.holland@sifive.com> To: Xingyu Wu <xingyu.wu@starfivetech.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 2/2] riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz Date: Sat, 11 May 2024 13:47:08 -0500 [thread overview] Message-ID: <b970012b-c078-4c8d-995d-e2789afa3e4c@sifive.com> (raw) In-Reply-To: <20240507065319.274976-3-xingyu.wu@starfivetech.com> On 2024-05-07 1:53 AM, Xingyu Wu wrote: > CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. > But now PLL0 rate is 1GHz and the cpu frequency loads become > 333/500/500/1000MHz in fact. > > The PLL0 rate should be default set to 1.5GHz and set the > cpu_core rate to 500MHz in safe. Can this be accomplished by instead setting the CLK_SET_RATE_PARENT flag on the CPU_CORE clock? That way PLL0 is automatically set when cpufreq tries to change the CPU core frequency. Then there is no DT change and no compatibility issue. Regards, Samuel > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 45b58b6f3df8..28981b267de4 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -390,6 +390,12 @@ spi_dev0: spi@0 { > }; > }; > > +&syscrg { > + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, > + <&pllclk JH7110_PLLCLK_PLL0_OUT>; > + assigned-clock-rates = <500000000>, <1500000000>; > +}; > + > &sysgpio { > i2c0_pins: i2c0-0 { > i2c-pins {
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel.holland@sifive.com> To: Xingyu Wu <xingyu.wu@starfivetech.com>, Michael Turquette <mturquette@baylibre.com>, Stephen Boyd <sboyd@kernel.org>, Conor Dooley <conor@kernel.org>, Emil Renner Berthing <emil.renner.berthing@canonical.com>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Hal Feng <hal.feng@starfivetech.com>, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH v5 2/2] riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz Date: Sat, 11 May 2024 13:47:08 -0500 [thread overview] Message-ID: <b970012b-c078-4c8d-995d-e2789afa3e4c@sifive.com> (raw) In-Reply-To: <20240507065319.274976-3-xingyu.wu@starfivetech.com> On 2024-05-07 1:53 AM, Xingyu Wu wrote: > CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. > But now PLL0 rate is 1GHz and the cpu frequency loads become > 333/500/500/1000MHz in fact. > > The PLL0 rate should be default set to 1.5GHz and set the > cpu_core rate to 500MHz in safe. Can this be accomplished by instead setting the CLK_SET_RATE_PARENT flag on the CPU_CORE clock? That way PLL0 is automatically set when cpufreq tries to change the CPU core frequency. Then there is no DT change and no compatibility issue. Regards, Samuel > Fixes: e2c510d6d630 ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") > Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> > --- > .../boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 45b58b6f3df8..28981b267de4 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -390,6 +390,12 @@ spi_dev0: spi@0 { > }; > }; > > +&syscrg { > + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, > + <&pllclk JH7110_PLLCLK_PLL0_OUT>; > + assigned-clock-rates = <500000000>, <1500000000>; > +}; > + > &sysgpio { > i2c0_pins: i2c0-0 { > i2c-pins { _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-05-11 18:47 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-05-07 6:53 [PATCH v5 0/2] Add notifier for PLL0 clock and set it 1.5GHz on Xingyu Wu 2024-05-07 6:53 ` Xingyu Wu 2024-05-07 6:53 ` [PATCH v5 1/2] clk: starfive: jh7110-sys: Add notifier for PLL0 clock Xingyu Wu 2024-05-07 6:53 ` Xingyu Wu 2024-05-07 10:11 ` Emil Renner Berthing 2024-05-07 10:11 ` Emil Renner Berthing 2024-05-07 6:53 ` [PATCH v5 2/2] riscv: dts: starfive: visionfive-2: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz Xingyu Wu 2024-05-07 6:53 ` Xingyu Wu 2024-05-07 10:13 ` Emil Renner Berthing 2024-05-07 10:13 ` Emil Renner Berthing 2024-05-11 18:47 ` Samuel Holland [this message] 2024-05-11 18:47 ` Samuel Holland 2024-05-14 7:40 ` Xingyu Wu 2024-05-14 7:40 ` Xingyu Wu 2024-05-10 21:05 ` [PATCH v5 0/2] Add notifier for PLL0 clock and set it 1.5GHz on Conor Dooley 2024-05-10 21:05 ` Conor Dooley 2024-05-11 3:02 ` Xingyu Wu 2024-05-11 3:02 ` Xingyu Wu 2024-05-11 12:18 ` Conor Dooley 2024-05-11 12:18 ` Conor Dooley 2024-05-14 7:40 ` Xingyu Wu 2024-05-14 7:40 ` Xingyu Wu 2024-05-14 18:07 ` Conor Dooley 2024-05-14 18:07 ` Conor Dooley 2024-05-15 2:23 ` Xingyu Wu 2024-05-15 2:23 ` Xingyu Wu 2024-05-15 16:30 ` Conor Dooley 2024-05-15 16:30 ` Conor Dooley
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=b970012b-c078-4c8d-995d-e2789afa3e4c@sifive.com \ --to=samuel.holland@sifive.com \ --cc=aou@eecs.berkeley.edu \ --cc=conor@kernel.org \ --cc=devicetree@vger.kernel.org \ --cc=emil.renner.berthing@canonical.com \ --cc=hal.feng@starfivetech.com \ --cc=krzysztof.kozlowski+dt@linaro.org \ --cc=linux-clk@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mturquette@baylibre.com \ --cc=palmer@dabbelt.com \ --cc=paul.walmsley@sifive.com \ --cc=robh@kernel.org \ --cc=sboyd@kernel.org \ --cc=xingyu.wu@starfivetech.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.