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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Huacai Chen <chenhc@lemote.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	kvm@vger.kernel.org,
	Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH 0/9] target/mips: Simplify MSA TCG logic
Date: Thu, 3 Dec 2020 11:36:43 +0800	[thread overview]
Message-ID: <b98de2d2-98db-1e34-64fd-ec0b4cafae11@flygoat.com> (raw)
In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org>



在 2020/12/3 上午2:44, Philippe Mathieu-Daudé 写道:
> I converted MSA opcodes to decodetree. To keep the series
> small I split it in 2, this is the non-decodetree specific
> patches (so non-decodetree experts can review it ;) ).
>
> First we stop using env->insn_flags to check for MSAi
> presence, then we restrict TCG functions to DisasContext*.

Hi Philippe,

For the whole series,
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>


I'm just curious about how would you deal with so many condition flags
with decodetree?

Unlike other ISAs, MIPS have so many flavors, every ISA level (MIPS-III 
R2 R5 R6)
has it's own instructions, and in my understanding decodetree file won't 
generate
these switches. I was trying to do the same thing but soon find out 
we'll have around
20 decodertree for MIPS.

Thanks.

- Jiaxun

>
> Based-on: <20201130102228.2395100-1-f4bug@amsat.org>
> "target/mips: Allow executing MSA instructions on Loongson-3A4000"
>
> Philippe Mathieu-Daudé (9):
>    target/mips: Introduce ase_msa_available() helper
>    target/mips: Simplify msa_reset()
>    target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
>    target/mips: Simplify MSA TCG logic
>    target/mips: Remove now unused ASE_MSA definition
>    target/mips: Alias MSA vector registers on FPU scalar registers
>    target/mips: Extract msa_translate_init() from mips_tcg_init()
>    target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
>    target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
>
>   target/mips/internal.h           |   8 +-
>   target/mips/mips-defs.h          |   1 -
>   target/mips/kvm.c                |  12 +-
>   target/mips/translate.c          | 206 ++++++++++++++++++-------------
>   target/mips/translate_init.c.inc |  12 +-
>   5 files changed, 138 insertions(+), 101 deletions(-)
>

WARNING: multiple messages have this Message-ID (diff)
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>, qemu-devel@nongnu.org
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	kvm@vger.kernel.org,
	Richard Henderson <richard.henderson@linaro.org>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Huacai Chen <chenhc@lemote.com>,
	Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH 0/9] target/mips: Simplify MSA TCG logic
Date: Thu, 3 Dec 2020 11:36:43 +0800	[thread overview]
Message-ID: <b98de2d2-98db-1e34-64fd-ec0b4cafae11@flygoat.com> (raw)
In-Reply-To: <20201202184415.1434484-1-f4bug@amsat.org>



在 2020/12/3 上午2:44, Philippe Mathieu-Daudé 写道:
> I converted MSA opcodes to decodetree. To keep the series
> small I split it in 2, this is the non-decodetree specific
> patches (so non-decodetree experts can review it ;) ).
>
> First we stop using env->insn_flags to check for MSAi
> presence, then we restrict TCG functions to DisasContext*.

Hi Philippe,

For the whole series,
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>


I'm just curious about how would you deal with so many condition flags
with decodetree?

Unlike other ISAs, MIPS have so many flavors, every ISA level (MIPS-III 
R2 R5 R6)
has it's own instructions, and in my understanding decodetree file won't 
generate
these switches. I was trying to do the same thing but soon find out 
we'll have around
20 decodertree for MIPS.

Thanks.

- Jiaxun

>
> Based-on: <20201130102228.2395100-1-f4bug@amsat.org>
> "target/mips: Allow executing MSA instructions on Loongson-3A4000"
>
> Philippe Mathieu-Daudé (9):
>    target/mips: Introduce ase_msa_available() helper
>    target/mips: Simplify msa_reset()
>    target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
>    target/mips: Simplify MSA TCG logic
>    target/mips: Remove now unused ASE_MSA definition
>    target/mips: Alias MSA vector registers on FPU scalar registers
>    target/mips: Extract msa_translate_init() from mips_tcg_init()
>    target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
>    target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
>
>   target/mips/internal.h           |   8 +-
>   target/mips/mips-defs.h          |   1 -
>   target/mips/kvm.c                |  12 +-
>   target/mips/translate.c          | 206 ++++++++++++++++++-------------
>   target/mips/translate_init.c.inc |  12 +-
>   5 files changed, 138 insertions(+), 101 deletions(-)
>


  parent reply	other threads:[~2020-12-03  3:40 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-02 18:44 [PATCH 0/9] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2020-12-02 18:44 ` Philippe Mathieu-Daudé
2020-12-02 18:44 ` [PATCH 1/9] target/mips: Introduce ase_msa_available() helper Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:08   ` Richard Henderson
2020-12-03 17:08     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 2/9] target/mips: Simplify msa_reset() Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:10   ` Richard Henderson
2020-12-03 17:10     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 3/9] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:10   ` Richard Henderson
2020-12-03 17:10     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 4/9] target/mips: Simplify MSA TCG logic Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:14   ` Richard Henderson
2020-12-03 17:14     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 5/9] target/mips: Remove now unused ASE_MSA definition Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-03 17:15   ` Richard Henderson
2020-12-03 17:15     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 16:28   ` Richard Henderson
2020-12-04 16:28     ` Richard Henderson
2020-12-04 22:40     ` Philippe Mathieu-Daudé
2020-12-04 22:40       ` Philippe Mathieu-Daudé
2020-12-05 12:44       ` Richard Henderson
2020-12-05 12:44         ` Richard Henderson
2020-12-02 18:44 ` [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init() Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 16:30   ` Richard Henderson
2020-12-04 16:30     ` Richard Henderson
2020-12-04 17:23     ` Philippe Mathieu-Daudé
2020-12-04 17:23       ` Philippe Mathieu-Daudé
2020-12-04 18:15       ` Richard Henderson
2020-12-04 18:15         ` Richard Henderson
2020-12-02 18:44 ` [PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 16:31   ` Richard Henderson
2020-12-04 16:31     ` Richard Henderson
2020-12-02 18:44 ` [PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() Philippe Mathieu-Daudé
2020-12-02 18:44   ` Philippe Mathieu-Daudé
2020-12-04 17:04   ` Richard Henderson
2020-12-04 17:04     ` Richard Henderson
2020-12-04 22:53     ` Philippe Mathieu-Daudé
2020-12-04 22:53       ` Philippe Mathieu-Daudé
2020-12-05 12:46       ` Richard Henderson
2020-12-05 12:46         ` Richard Henderson
2020-12-03  3:36 ` Jiaxun Yang [this message]
2020-12-03  3:36   ` [PATCH 0/9] target/mips: Simplify MSA TCG logic Jiaxun Yang
2020-12-03  3:38 ` Jiaxun Yang
2020-12-03  3:38   ` Jiaxun Yang

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