[PATCH 0/5] memorder: Update table layout

[PATCH 0/5] memorder: Update table layout

[Akira Yokosawa]

From acefbb69d69562438d7a7568f671fc85528d5b5f Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Mon, 25 Sep 2017 06:38:06 +0900
Subject: [PATCH 0/5] memorder: Update table layout

Hi Paul,

My first thought was to update a few experimental tables to catch up
the changes in memorder.tex.
But these new tables are likely to change further.
So I changed my mind and converted the 5 tables in memorder.tex using
the new scheme of shading alternate rows. 3 of the 5 tables are already
presented in the style guide.
In the memorder chapter, we already converted code snippets to the
"listing" environment. So using the new table layout in this chapter
sounds reasonable to me.

Patch #1 updates already experimented tables and a similar one.
Patch #2 is an attempt to apply new scheme to the remaining table.
Patch #3 is an improvement of the table changed in Patch #2.
Patch #4 removes experimental tables in style guide.
Patch #5 is a separate patch to improve MoreThanOneValue and
MoreThanOneValue-15CPU figures.

I'd like to know if the changes in Patches #2 and #3 work with you.

        Thanks, Akira
--
Akira Yokosawa (5):
  memorder: Convert tables to alternate-row coloring scheme
  memorder: Convert 'Summary of Memory Ordering' table to new scheme
  styleguide: Remove experimental tables updated in memorder chapter
  memorder: Add multi-column headers to 'Summary of Memory Ordering'
    table
  memorder: Reduce color saturation of MoreThanOneValue figure

 appendix/styleguide/styleguide.tex  | 113 +---------------------
 memorder/MoreThanOneValue-15CPU.fig |   2 +
 memorder/MoreThanOneValue.fig       |  26 ++---
 memorder/memorder.tex               | 183 ++++++++++++++++--------------------
 perfbook.tex                        |   1 +
 utilities/MoreThanOneValue-15CPU.c  |   3 +
 6 files changed, 107 insertions(+), 221 deletions(-)

-- 
2.7.4

[PATCH 1/5] memorder: Convert tables to alternate-row coloring scheme

[Akira Yokosawa]

From a2de9f65f942f0cce79da28099b616f5e8919489 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Sat, 23 Sep 2017 19:54:51 +0900
Subject: [PATCH 1/5] memorder: Convert tables to alternate-row coloring scheme

Instead of updating them in style guide, apply alternate-
row coloring scheme to tables in memorder chapter.
The scheme goes well with the looks of code snippets in "listing"
environment with "ruled" style already employed in this chapter.
Position of captions is not modified at the moment.

Corresponding tables in style guide will be removed later.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 appendix/styleguide/styleguide.tex |   1 -
 memorder/memorder.tex              | 130 +++++++++++++++----------------------
 perfbook.tex                       |   1 +
 3 files changed, 55 insertions(+), 77 deletions(-)

diff --git a/appendix/styleguide/styleguide.tex b/appendix/styleguide/styleguide.tex
index 46d93f6..8bedbef 100644
--- a/appendix/styleguide/styleguide.tex
+++ b/appendix/styleguide/styleguide.tex
@@ -927,7 +927,6 @@ used sparingly, especially in tables of simple structure.
 \restylefloat{table}
 \captionsetup[table]{position=top,hangindent=30pt}
 \renewcommand*{\abovetopsep}{-7pt}
-\definecolor{lightgray}{gray}{0.9}

 For example,
 Table~\ref{tab:future:Refrigeration Power Consumption}
diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 16de2b6..f393e33 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -200,30 +200,29 @@ In particular, these store buffers can cause the memory misordering
 shown in the store-buffering litmus test in
 Listing~\ref{lst:memorder:Memory Misordering: Store-Buffering Litmus Test}.

-\begin{table*}
+\begin{table*}[tbh]
+\rowcolors{6}{}{lightgray}
+\renewcommand*{\arraystretch}{1.1}
 \small
 \centering\OneColumnHSpace{-0.1in}
-\begin{tabular}{r||l|l|l||l|l|l}
-	& \multicolumn{3}{c||}{CPU 0} & \multicolumn{3}{c}{CPU 1} \\
-	\cline{2-7}
+\begin{tabular}{rllllll}
+	\toprule
+	& \multicolumn{3}{c}{CPU 0} & \multicolumn{3}{c}{CPU 1} \\
+	\cmidrule(l){2-4} \cmidrule(l){5-7}
 	& Instruction & Store Buffer & Cache &
 		Instruction & Store Buffer & Cache \\
-	\hline
-	\hline
+	\cmidrule{1-1} \cmidrule(l){2-4} \cmidrule(l){5-7}
 	1 & (Initial state) & & \tco{x1==0} &
 		(Initial state) & & \tco{x0==0} \\
-	\hline
 	2 & \tco{x0 = 2;} & \tco{x0==2} & \tco{x1==0} &
 		\tco{x1 = 2;} & \tco{x1==2} & \tco{x0==0} \\
-	\hline
 	3 & \tco{r2 = x1;} (0) & \tco{x0==2} & \tco{x1==0} &
 		\tco{r2 = x0;} (0) & \tco{x1==2} & \tco{x0==0} \\
-	\hline
 	4 & (Read-invalidate) & \tco{x0==2} & \tco{x0==0} &
 		(Read-invalidate) & \tco{x1==2} & \tco{x1==0} \\
-	\hline
 	5 & (Finish store) & & \tco{x0==2} &
 		(Finish store) & & \tco{x1==2} \\
+	\bottomrule
 \end{tabular}
 \caption{Memory Misordering: Store-Buffering Sequence of Events}
 \label{tab:memorder:Memory Misordering: Store-Buffering Sequence of Events}
@@ -380,33 +379,31 @@ than 800,000 times, as opposed to only 167 times for the
 barrier-free code in
 Listing~\ref{lst:memorder:Memory Misordering: Store-Buffering Litmus Test}.

-\begin{table*}
+\begin{table*}[tbh]
+\rowcolors{6}{}{lightgray}
+\renewcommand*{\arraystretch}{1.1}
 \small
 \centering\OneColumnHSpace{-0.1in}
-\begin{tabular}{r||l|l|l||l|l|l}
-	& \multicolumn{3}{c||}{CPU 0} & \multicolumn{3}{c}{CPU 1} \\
-	\cline{2-7}
+\begin{tabular}{rllllll}
+	\toprule
+	& \multicolumn{3}{c}{CPU 0} & \multicolumn{3}{c}{CPU 1} \\
+	\cmidrule(l){2-4} \cmidrule(l){5-7}
 	& Instruction & Store Buffer & Cache &
 		Instruction & Store Buffer & Cache \\
-	\hline
-	\hline
+	\cmidrule{1-1} \cmidrule(l){2-4} \cmidrule(l){5-7}
 	1 & (Initial state) & & \tco{x1==0} &
 		(Initial state) & & \tco{x0==0} \\
-	\hline
 	2 & \tco{x0 = 2;} & \tco{x0==2} & \tco{x1==0} &
 		\tco{x1 = 2;} & \tco{x1==2} & \tco{x0==0} \\
-	\hline
 	3 & \tco{smp_mb();} & \tco{x0==2} & \tco{x1==0} &
 		\tco{smp_mb();} & \tco{x1==2} & \tco{x0==0} \\
-	\hline
 	4 & (Read-invalidate) & \tco{x0==2} & \tco{x0==0} &
 		(Read-invalidate) & \tco{x1==2} & \tco{x1==0} \\
-	\hline
 	5 & (Finish store) & & \tco{x0==2} &
 		(Finish store) & & \tco{x1==2} \\
-	\hline
 	6 & \tco{r2 = x1;} (2) & & \tco{x1==2} &
 		\tco{r2 = x0;} (2) & & \tco{x0==2} \\
+	\bottomrule
 \end{tabular}
 \caption{Memory Ordering: Store-Buffering Sequence of Events}
 \label{tab:memorder:Memory Ordering: Store-Buffering Sequence of Events}
@@ -426,77 +423,63 @@ Note that variables \co{x0} and \co{x1} each still have more than one
 value on row~2, however, as promised earlier, the \co{smp_mb()}
 instances straighten things out in the end.

-\begin{table*}
+\begin{table*}[tbh]
 \small
-\centering\OneColumnHSpace{-0.8in}
-\begin{tabular}{l||c||c|c|c|c||c|c|c|c|c|c|c}
-	& & \multicolumn{4}{c||}{Prior Ordered Operation} &
+\centering\OneColumnHSpace{-0.7in}
+\renewcommand*{\arraystretch}{1.1}
+\rowcolors{7}{lightgray}{}
+\begin{tabular}{lcccccccccccc}\toprule
+	& & \multicolumn{4}{c}{Prior Ordered Operation} &
 		\multicolumn{7}{c}{Subsequent Ordered Operation} \\
-	\cline{3-6} \cline{7-13}
+	\cmidrule(l){3-6} \cmidrule(l){7-13}
 	Operation Providing Ordering & C &
 		Self & R & W & RMW & Self & R & W & DR & DW & RMW & SV \\
-	\hline
-	\hline
+	\cmidrule(r){1-1} \cmidrule{2-2} \cmidrule(l){3-6} \cmidrule(l){7-13}
 	Store, for example, \tco{WRITE_ONCE()} &  &
 		   Y &   &   &     &      &   &   &    &    &     &  Y \\
-	\hline
 	Load, for example, \tco{READ_ONCE()} &  &
 		   Y &   &   &     &      &   &   &    &  Y &     &  Y \\
-	\hline
 	Unsuccessful RMW operation &  &
 		   Y &   &   &     &      &   &   &    &  Y &     &  Y \\
-	\hline
 	\tco{smp_read_barrier_depends()} &  &
 		     & Y &   &     &      &   &   &  Y &  Y &     &    \\
-	\hline
 	\tco{*_dereference()} &  &
 		   Y &   &   &     &      &   &   &  Y &  Y &     &  Y \\
-	\hline
 	Successful \tco{*_acquire()} &   &
 		   R &   &   &     &      & Y & Y &  Y &  Y &   Y &  Y \\
-	\hline
 	Successful \tco{*_release()} & C &
 		     & Y & Y &   Y &    W &   &   &    &    &     &  Y \\
-	\hline
 	\tco{smp_rmb()} &   &
 		     & Y &   &   R &      & Y &   &  Y &    &   R &    \\
-	\hline
 	\tco{smp_wmb()} &   &
 		     &   & Y &   W &      &   & Y &    &  Y &   W &    \\
-	\hline
 	\tco{smp_mb()} and \tco{synchronize_rcu()} & CP &
 		     & Y & Y &   Y &      & Y & Y &  Y &  Y &   Y &    \\
-	\hline
 	Successful full-strength non-\tco{void} RMW & CP &
 		   Y & Y & Y &   Y &    Y & Y & Y &  Y &  Y &   Y &  Y \\
-	\hline
 	\tco{smp_mb__before_atomic()} & CP &
 		     & Y & Y &   Y &      & a & a & a  & a  &   Y &    \\
-	\hline
 	\tco{smp_mb__after_atomic()} & CP &
 		     & a & a &   Y &      & Y & Y &  Y &  Y &     &    \\
-	\multicolumn{13}{c}{~} \\
-	\multicolumn{1}{r}{Key:} &
-		\multicolumn{12}{l}{C: Ordering is cumulative} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{P: Ordering propagates} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{R: Read, for example, \tco{READ_ONCE()}, or read portion of RMW} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{W: Write, for example, \tco{WRITE_ONCE()}, or write portion of RMW} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{Y: Provides the specified ordering} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{a: Provides specified ordering given intervening RMW atomic operation} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{DR: Dependent read (address dependency, Section~\ref{sec:memorder:Address Dependencies})} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{DW: Dependent write (address, data, or control dependency, Sections~\ref{sec:memorder:Address Dependencies}--\ref{sec:memorder:Control Dependencies})} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{RMW: Atomic read-modify-write operation} \\
-	\multicolumn{1}{r}{} &
-		\multicolumn{12}{l}{SV: Same-variable access} \\
+	\bottomrule
 \end{tabular}
+
+\vspace{5pt}\hfill
+\framebox[\width]{\footnotesize\setlength{\tabcolsep}{3pt}
+\rowcolors{1}{}{}
+\begin{tabular}{lrl}
+	Key:	& C: & Ordering is cumulative \\
+		& P: & Ordering propagates \\
+		& R: & Read, for example, \tco{READ_ONCE()}, or read portion of RMW \\
+		& W: & Write, for example, \tco{WRITE_ONCE()}, or write portion of RMW \\
+		& Y: & Provides the specified ordering \\
+		& a: & Provides specified ordering given intervening RMW atomic operation \\
+		& DR: & Dependent read (address dependency, Section~\ref{sec:memorder:Address Dependencies}) \\
+		& DW: & Dependent write (address, data, or control dependency, Sections~\ref{sec:memorder:Address Dependencies}--\ref{sec:memorder:Control Dependencies}) \\
+		& RMW: & Atomic read-modify-write operation \\
+		& SV: & Same-variable access \\
+\end{tabular}
+}\OneColumnHSpace{-0.9in}
 \caption{Linux-Kernel Memory-Ordering Cheat Sheet}
 \label{tab:memorder:Linux-Kernel Memory-Ordering Cheat Sheet}
 \end{table*}
@@ -1928,46 +1911,41 @@ line to carry this new value to them.
 	Natural from a hardware point of view, that is!
 } \QuickQuizEnd

-\begin{table*}
+\begin{table*}[tbh]
 \small
 \centering\OneColumnHSpace{-0.8in}
-\begin{tabular}{r||l|l|l|l||l|l|l}
-	& \tco{P0()} & \multicolumn{2}{c|}{\tco{P0()} \& \tco{P1()}} & \tco{P1()} & \multicolumn{3}{c}{\tco{P2()}} \\
-	\cline{2-8}
+\renewcommand*{\arraystretch}{1.1}
+\rowcolors{13}{lightgray}{}
+\begin{tabular}{rlllllll}\toprule
+	& \multicolumn{1}{c}{\tco{P0()}} & \multicolumn{2}{c}{\tco{P0()} \& \tco{P1()}} &
+		\multicolumn{1}{c}{\tco{P1()}} & \multicolumn{3}{c}{\tco{P2()}} \\
+	\cmidrule(l){2-2} \cmidrule(l){3-4} \cmidrule(lr){5-5} \cmidrule(l){6-8}
 	& Instruction & Store Buffer & Cache & Instruction &
 			Instruction & Store Buffer & Cache \\
-	\hline
-	\hline
+	\cmidrule{1-1} \cmidrule(l){2-2} \cmidrule(l){3-3} \cmidrule(l){4-4}
+		\cmidrule(lr){5-5} \cmidrule(l){6-6} \cmidrule(l){7-7} \cmidrule(l){8-8}
 	1 & (Initial state) & & \tco{y==0} &
 		(Initial state) &
 			(Initial state) & & \tco{x==0} \\
-	\hline
 	2 & \tco{x = 1;} & \tco{x==1} & \tco{y==0} &
 		 & & & \tco{x==0} \\
-	\hline
 	3 & (Read-Invalidate \tco{x}) & \tco{x==1} & \tco{y==0} & \tco{r1 = x} (1)
 		 & & & \tco{x==0} \\
-	\hline
 	4 &  & \tco{x==1} \tco{y==1} & \tco{y==0} & \tco{y = r1}
 		 & \tco{r2 = y} & & \tco{x==0} \\
-	\hline
 	5 &  & \tco{x==1} & \tco{y==1} & (Finish store)
 		 & (Read \tco{y}) & & \tco{x==0} \\
-	\hline
 	6 & (Respond \tco{y}) & \tco{x==1} & \tco{y==1} &
 		 & (\tco{r2==1}) & & \tco{x==0} \tco{y==1} \\
-	\hline
 	7 & & \tco{x==1} & \tco{y==1} &
 		 & \tco{smp_rmb()} & & \tco{x==0} \tco{y==1} \\
-	\hline
 	8 & & \tco{x==1} & \tco{y==1} &
 		 & \tco{r3 = x (0)} & & \tco{x==0} \tco{y==1} \\
-	\hline
 	9 & & \tco{x==1} & \tco{x==0} \tco{y==1} &
 		 & (Respond \tco{x}) & & \tco{y==1} \\
-	\hline
 	10 & (Finish store) & & \tco{x==1} \tco{y==1} &
 		 &  & & \tco{y==1} \\
+	\bottomrule
 \end{tabular}
 \caption{Memory Ordering: WRC Sequence of Events}
 \label{tab:memorder:Memory Ordering: WRC Sequence of Events}
diff --git a/perfbook.tex b/perfbook.tex
index 415022c..10346c7 100644
--- a/perfbook.tex
+++ b/perfbook.tex
@@ -93,6 +93,7 @@
 \usepackage{bm} % for bold math mode fonts --- should be after math mode font choice
 \usepackage{booktabs}
 \usepackage{arydshln}
+\definecolor{lightgray}{gray}{0.9} % for coloring alternate rows in table

 \IfLmttForCode{
 \AtBeginEnvironment{verbatim}{\renewcommand{\ttdefault}{lmtt}}
-- 
2.7.4

[PATCH 2/5] memorder: Convert 'Summary of Memory Ordering' table to new scheme

[Akira Yokosawa]

From 3834226426b8a0f5f6b032b1167e02fbe7ef7b15 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Sat, 23 Sep 2017 20:14:03 +0900
Subject: [PATCH 2/5] memorder: Convert 'Summary of Memory Ordering' table to new scheme

Employ alternate-row coloring scheme to the remaining table in this
chapter.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 memorder/memorder.tex | 47 ++++++++++++++++++++++++-----------------------
 1 file changed, 24 insertions(+), 23 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index f393e33..00ff31c 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -3675,12 +3675,14 @@ dependencies.
 \label{sec:memorder:Hardware Specifics}
 \OriginallyPublished{Appendix}{sec:memorder:Hardware Specifics}{Memory-Barrier Instructions For Specific CPUs}{Linux Journal}{PaulMcKenney2005i,PaulMcKenney2005j}

-\begin{table*}
+\begin{table*}[tbh]
+\rowcolors{4}{}{lightgray}
 \small
 \centering
 \renewcommand*{\arraystretch}{1.2}\OneColumnHSpace{-.6in}
-\begin{tabular}{l|p{2in}|c|c|c|c|c|c|c|c|c|c|c}
-	\multicolumn{2}{l|}{~}
+\begin{tabular}{lp{2in}ccccccccccc}
+	\toprule
+	\multicolumn{2}{l}{~}
 	& \begin{picture}(6,60)(0,0)
 		\rotatebox{90}{Alpha}
 	  \end{picture}
@@ -3715,56 +3717,54 @@ dependencies.
 		\rotatebox{90}{z~Systems}
 	  \end{picture}
 	\\
-	\hline
+	\cmidrule(r){1-2} \cmidrule{3-13}
 %		 Alpha ARMv8 ARMv7 Itanium MIPS PA-RISC -CPUs PPC SPARC x86 z Systems
-	\hline
-        Memory Ordering
+\cellcolor{white}
+	Memory Ordering
 	& Loads Reordered After Loads or Stores?
 		 & Y   & Y   & Y   & Y     & Y  & Y     & ~   & Y & ~   & ~ & ~ \\
-	\cline{2-13}
 	& Stores Reordered After Stores?
 		 & Y   & Y   & Y   & Y     & Y  & Y     & ~   & Y & ~   & ~ & ~ \\
-	\cline{2-13}
+\cellcolor{white}
 	& Stores Reordered After Loads?
 		 & Y   & Y   & Y   & Y     & Y  & Y     & ~   & Y & Y   & Y & Y \\
-	\cline{2-13}
 	& Atomic Instructions Reordered With Loads or Stores?
 		 & Y   & Y   & Y   & ~     & Y  & ~     & ~   & Y & ~   & ~ & ~ \\
-	\cline{2-13}
+\cellcolor{white}
 	& Dependent Loads Reordered?
 		 & Y   & ~   & ~   & ~     & ~  & ~     & ~   & ~ & ~   & ~ & ~ \\
-	\cline{2-13}
 	& Dependent Stores Reordered?
 		 & ~   & ~   & ~   & ~     & ~  & ~     & ~   & ~ & ~   & ~ & ~ \\
-	\cline{2-13}
+\cellcolor{white}
 	& Non-Sequentially Consistent?
 		 & Y   & Y   & Y   & Y     & Y  & Y     & ~   & Y & Y   & Y & Y \\
-	\cline{2-13}
 	& Non-Multicopy Atomic?
 		 & Y   & Y   & Y   & Y     & Y  & Y     & ~   & Y & Y   & Y & ~ \\
-	\cline{2-13}
+\cellcolor{white}
 	& Non-Other-Multicopy Atomic?
 		 & Y   & ~   & Y   & Y     & Y  & Y     & ~   & Y & Y   & Y & ~ \\
-	\cline{2-13}
 	& Non-Cache Coherent?
 		 & ~   & ~   & ~   & Y     & ~  & ~     & ~   & ~ & ~   & ~ & ~ \\
-	\hline
-        \hline
-        Instructions
+	\cmidrule(r){1-2} \cmidrule{3-13}
+\cellcolor{white}
+	Instructions
 	& Load-Acquire/Store-Release?
 		 & F   & i   & F   & I     & ?  & ?     & ~   & b & ~   & ~ & ~ \\
-        \cline{2-13}
 	& Atomic RMW Instruction Type?
 		 & L   & L   & L   & C     & L  & ?     & ?   & L & ?   & C & C \\
-        \cline{2-13}
+\cellcolor{white}
 	& Incoherent Instruction Cache/Pipeline?
 		 & Y   & Y   & Y   & Y     & Y  & ~     & ~   & Y & Y   & Y & Y \\
+	\bottomrule
 \end{tabular}
+
+\vspace{5pt}\hfill
+\framebox[\width]{\footnotesize\setlength{\tabcolsep}{3pt}
+\rowcolors{1}{}{}
 \renewcommand*{\arraystretch}{1}
 \begin{tabular}{llcl}
-	~ & ~ & ~ & ~\\
-	{ \bf Key: } & ~ & ~ & ~ \\
-	~ & \multicolumn{3}{l}{Load-Acquire/Store-Release?} \\
+	{ \bf Key: }
+	  & \multicolumn{3}{l}{Load-Acquire/Store-Release?} \\
 	~ & ~ & b: & Lightweight memory barrier \\
 	~ & ~ & F: & Full memory barrier \\
 	~ & ~ & i: & Instruction with lightweight ordering \\
@@ -3773,6 +3773,7 @@ dependencies.
 	~ & ~ & C: & Compare-and-exchange instruction \\
 	~ & ~ & L: & Load-linked/store-conditional instruction \\
 \end{tabular}
+}\OneColumnHSpace{-0.7in}
 \caption{Summary of Memory Ordering}
 \label{tab:memorder:Summary of Memory Ordering}
 \end{table*}
-- 
2.7.4

[PATCH 3/5] styleguide: Remove experimental tables updated in memorder chapter

[Akira Yokosawa]

From 3e7f4562704eac72d3652613ea25aee2e00f176d Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Sat, 23 Sep 2017 20:42:16 +0900
Subject: [PATCH 3/5] styleguide: Remove experimental tables updated in memorder chapter

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 appendix/styleguide/styleguide.tex | 112 ++-----------------------------------
 1 file changed, 4 insertions(+), 108 deletions(-)

diff --git a/appendix/styleguide/styleguide.tex b/appendix/styleguide/styleguide.tex
index 8bedbef..bb100a9 100644
--- a/appendix/styleguide/styleguide.tex
+++ b/appendix/styleguide/styleguide.tex
@@ -1383,114 +1383,10 @@ IBM~Q	& $0.015$
 \label{tab:app:styleguide:Refrigeration Power Consumption (arydshln-2)}
 \end{table}

-Tables~\ref{tab:memorder:Linux-Kernel Memory-Ordering Cheat Sheet}
-and~\ref{tab:memorder:Memory Ordering: WRC Sequence of Events}
-recently added in Chapter~\ref{chp:memorder:Memory Ordering}
-can be typeset as
-Tables~\ref{tab:app:styleguide:Linux-Kernel Memory-Ordering Cheat Sheet}
-and~\ref{tab:app:styleguide:Memory Ordering: WRC Sequence of Events}
-using booktabs' ruled lines.
-
-\begin{table*}
-\small
-\centering\OneColumnHSpace{-0.7in}
-\renewcommand*{\arraystretch}{1.1}
-\rowcolors{7}{lightgray}{}
-\begin{tabular}{lcccccccccccc}\toprule
-	& & \multicolumn{4}{c}{Prior Ordered Operation} &
-		\multicolumn{6}{c}{Subsequent Ordered Operation} \\
-	\cmidrule(l){3-6} \cmidrule(l){7-13}
-	Operation Providing Ordering & C &
-		Self & R & W & RMW & Self & R & W & DR & DW & RMW & SV\\
-	\cmidrule(r){1-1} \cmidrule{2-2} \cmidrule(l){3-6} \cmidrule(l){7-13}
-	Write, for example, \tco{WRITE_ONCE()} &  &
-		   Y &   &   &     &      &   &   &    &    &     &  Y \\
-	Load, for example, \tco{READ_ONCE()} &  &
-		   Y &   &   &     &      &   &   &    &  Y &     &  Y \\
-	Unsuccessful RMW operation &  &
-		   Y &   &   &     &      &   &   &    &  Y &     &  Y \\
-	\tco{smp_read_barrier_depends()} &  &
-		     & Y &   &     &      &   &   &  Y &  Y &     &    \\
-	\tco{*_dereference()} &  &
-		   Y &   &   &     &      &   &   &  Y &  Y &     &  Y \\
-	Successful \tco{*_acquire()} &   &
-		   R &   &   &     &      & Y & Y &  Y &  Y &   Y &  Y \\
-	Successful \tco{*_release()} & C &
-		     & Y & Y &   Y &    W &   &   &    &    &     &  Y \\
-	\tco{smp_rmb()} &   &
-		     & Y &   &   R &      & Y &   &  Y &    &   R &    \\
-	\tco{smp_wmb()} &   &
-		     &   & Y &   W &      &   & Y &    &  Y &   W &    \\
-	\tco{smp_mb()} & CP &
-		     & Y & Y &   Y &      & Y & Y &  Y &  Y &   Y &    \\
-	Successful full-strength non-\tco{void} RMW & CP &
-		   Y & Y & Y &   Y &    Y & Y & Y &  Y &  Y &   Y &  Y \\
-	\tco{smp_mb__before_atomic()} & CP &
-		     & Y & Y &   Y &      & a & a & a  & a  &   Y &    \\
-	\tco{smp_mb__after_atomic()} & CP &
-		     & a & a &   Y &      & Y & Y &  Y &  Y &     &    \\
-	\bottomrule
-\end{tabular}
-
-\vspace{5pt}\hfill
-\framebox[\width]{\footnotesize\setlength{\tabcolsep}{3pt}
-\rowcolors{1}{}{}
-\begin{tabular}{lrl}
-	Key:	& C: & Ordering is cumulative \\
-		& P: & Ordering propagates \\
-		& R: & Read, for example, \tco{READ_ONCE()}, or read portion of RMW \\
-		& W: & Write, for example, \tco{WRITE_ONCE()}, or write portion of RMW \\
-		& Y: & Provides the specified ordering \\
-		& a: & Provides specified ordering given intervening RMW atomic operation \\
-		& DR: & Dependent read (address dependency, Section~\ref{sec:memorder:Address Dependencies}) \\
-		& DW: & Dependent write (address, data, or control dependency, Sections~\ref{sec:memorder:Address Dependencies}--\ref{sec:memorder:Control Dependencies}) \\
-		& RMW: & Atomic read-modify-write operation \\
-		& SV: & Same-variable access \\
-\end{tabular}
-}\OneColumnHSpace{-0.9in}
-\caption{Linux-Kernel Memory-Ordering Cheat Sheet}
-\label{tab:app:styleguide:Linux-Kernel Memory-Ordering Cheat Sheet}
-\end{table*}
-
-\begin{table*}
-\small
-\centering\OneColumnHSpace{-0.8in}
-\renewcommand*{\arraystretch}{1.1}
-\rowcolors{13}{lightgray}{}
-\begin{tabular}{rlllllll}\toprule
-	& \multicolumn{1}{c}{\tco{P0()}} & \multicolumn{2}{c}{\tco{P0()} \& \tco{P1()}} &
-		\multicolumn{1}{c}{\tco{P1()}} & \multicolumn{3}{c}{\tco{P2()}} \\
-	\cmidrule(l){2-2} \cmidrule(l){3-4} \cmidrule(lr){5-5} \cmidrule(l){6-8}
-	& Instruction & Store Buffer & Cache & Instruction &
-			Instruction & Store Buffer & Cache \\
-	\cmidrule{1-1} \cmidrule(l){2-2} \cmidrule(l){3-3} \cmidrule(l){4-4}
-		\cmidrule(lr){5-5} \cmidrule(l){6-6} \cmidrule(l){7-7} \cmidrule(l){8-8}
-	1 & (Initial state) & & \tco{y==0} &
-		(Initial state) &
-			(Initial state) & & \tco{x==0} \\
-	2 & \tco{x = 1;} & \tco{x==1} & \tco{y==0} &
-		 & & & \tco{x==0} \\
-	3 & (Read-Invalidate \tco{x}) & \tco{x==1} & \tco{y==0} & \tco{r1 = x} (1)
-		 & & & \tco{x==0} \\
-	4 &  & \tco{x==1} \tco{y==1} & \tco{y==0} & \tco{y = r1}
-		 & \tco{r2 = y} & & \tco{x==0} \\
-	5 &  & \tco{x==1} & \tco{y==1} & (Finish store)
-		 & (Read \tco{y}) & & \tco{x==0} \\
-	6 & (Respond \tco{y}) & \tco{x==1} & \tco{y==1} &
-		 & (\tco{r2==1}) & & \tco{x==0} \tco{y==1} \\
-	7 & & \tco{x==1} & \tco{y==1} &
-		 & \tco{smp_rmb()} & & \tco{x==0} \tco{y==1} \\
-	8 & & \tco{x==1} & \tco{y==1} &
-		 & \tco{r3 = x (0)} & & \tco{x==0} \tco{y==1} \\
-	9 & & \tco{x==1} & \tco{x==0} \tco{y==1} &
-		 & (Respond \tco{x}) & & \tco{y==1} \\
-	10 & (Finish store) & & \tco{x==1} \tco{y==1} &
-		 &  & & \tco{y==1} \\
-	\bottomrule
-\end{tabular}
-\caption{Memory Ordering: WRC Sequence of Events}
-\label{tab:app:styleguide:Memory Ordering: WRC Sequence of Events}
-\end{table*}
+Tables in Chapter~\ref{chp:memorder:Memory Ordering}
+have been recently converted to the scheme presented in this section.
+Refer to \path{memorder/memorder.tex}
+for examples of tables with complex headings.

 \floatstyle{plain}
 \restylefloat{table}
-- 
2.7.4

[PATCH 4/5] memorder: Add multi-column headers to 'Summary of Memory Ordering' table

[Akira Yokosawa]

From 6aa821a7b0717c2944aa67b53086b7da09abee55 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Sun, 24 Sep 2017 00:43:51 +0900
Subject: [PATCH 4/5] memorder: Add multi-column headers to 'Summary of Memory Ordering' table

Also tweak the cell of "Atomic Instructions Reordered With Loads or
Stores?" for it to be vertically positioned at the center of the row.
The width of the column is now specified by the width of the parbox.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 memorder/memorder.tex | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 00ff31c..4f0029a 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -3680,9 +3680,11 @@ dependencies.
 \small
 \centering
 \renewcommand*{\arraystretch}{1.2}\OneColumnHSpace{-.6in}
-\begin{tabular}{lp{2in}ccccccccccc}
+\begin{tabular}{llccccccccccc}
 	\toprule
-	\multicolumn{2}{l}{~}
+	\multicolumn{2}{l}{~} & \multicolumn{11}{c}{CPU Family} \\
+	\cmidrule{3-13}
+	\multicolumn{2}{c}{\raisebox{.5ex}{Property}}
 	& \begin{picture}(6,60)(0,0)
 		\rotatebox{90}{Alpha}
 	  \end{picture}
@@ -3728,7 +3730,7 @@ dependencies.
 \cellcolor{white}
 	& Stores Reordered After Loads?
 		 & Y   & Y   & Y   & Y     & Y  & Y     & ~   & Y & Y   & Y & Y \\
-	& Atomic Instructions Reordered With Loads or Stores?
+	& \parbox[c][6ex]{2in}{\raggedright Atomic Instructions Reordered With\par Loads or Stores?}
 		 & Y   & Y   & Y   & ~     & Y  & ~     & ~   & Y & ~   & ~ & ~ \\
 \cellcolor{white}
 	& Dependent Loads Reordered?
-- 
2.7.4

[PATCH 5/5] memorder: Reduce color saturation of MoreThanOneValue figure

[Akira Yokosawa]

From acefbb69d69562438d7a7568f671fc85528d5b5f Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@gmail.com>
Date: Sun, 24 Sep 2017 23:47:34 +0900
Subject: [PATCH 5/5] memorder: Reduce color saturation of MoreThanOneValue figure

Also add a label at t == 0 and separate unit (ns) from numbers
in x-axis labels.
Also add unit of (tick) to x axis of MoreThanOneValue-15CPU figure.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 memorder/MoreThanOneValue-15CPU.fig |  2 ++
 memorder/MoreThanOneValue.fig       | 26 +++++++++++++++-----------
 memorder/memorder.tex               |  2 +-
 utilities/MoreThanOneValue-15CPU.c  |  3 +++
 4 files changed, 21 insertions(+), 12 deletions(-)

diff --git a/memorder/MoreThanOneValue-15CPU.fig b/memorder/MoreThanOneValue-15CPU.fig
index 3171197..e36c06a 100644
--- a/memorder/MoreThanOneValue-15CPU.fig
+++ b/memorder/MoreThanOneValue-15CPU.fig
@@ -310,6 +310,7 @@ Single
 2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
 	 8200 4200 8200 4300
 4 1 0 50 0 16 9 0.0000 4 90 375 8200 4450 500\001
+4 1 0 50 0 16 9 0.0000 4 90 375 8800 4450 (tick)\001
 4 2 0 50 0 16 8.5 0.0000 4 105 420 670 200 CPU  1\001
 4 2 0 50 0 16 8.5 0.0000 4 105 420 670 470 CPU  2\001
 4 2 0 50 0 16 8.5 0.0000 4 105 420 670 740 CPU  3\001
@@ -465,6 +466,7 @@ Single
 2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
 	 7450 9060 7450 9160
 4 1 0 50 0 16 9 0.0000 4 90 375 7450 9310 45\001
+4 1 0 50 0 16 9 0.0000 4 90 375 8050 9310 (tick)\001
 4 2 0 50 0 16 8.5 0.0000 4 105 420 670 5060 CPU  1\001
 4 2 0 50 0 16 8.5 0.0000 4 105 420 670 5330 CPU  2\001
 4 2 0 50 0 16 8.5 0.0000 4 105 420 670 5600 CPU  3\001
diff --git a/memorder/MoreThanOneValue.fig b/memorder/MoreThanOneValue.fig
index ae46c75..e271344 100644
--- a/memorder/MoreThanOneValue.fig
+++ b/memorder/MoreThanOneValue.fig
@@ -8,13 +8,13 @@ Single
 -2
 1200 2
 6 525 0 5055 1575
-2 2 0 1 0 4 50 0 20 0.000 0 0 -1 0 0 5
+2 2 0 1 0 4 50 0 30 0.000 0 0 -1 0 0 5
 	 765 0 2970 0 2970 270 765 270 765 0
 2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5
 	 585 270 5040 270 5040 540 585 540 585 270
-2 2 0 1 0 2 50 0 20 0.000 0 0 -1 0 0 5
+2 2 0 1 0 2 50 0 30 0.000 0 0 -1 0 0 5
 	 675 810 540 810 540 540 675 540 675 810
-2 2 0 1 0 11 50 0 20 0.000 0 0 -1 0 0 5
+2 2 0 1 0 11 50 0 30 0.000 0 0 -1 0 0 5
 	 720 810 4770 810 4770 1080 720 1080 720 810
 2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5
 	 5040 810 675 810 675 540 5040 540 5040 810
@@ -22,11 +22,11 @@ Single
 	 5040 1080 4770 1080 4770 810 5040 810 5040 1080
 2 2 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 5
 	 5040 0 2970 0 2970 270 5040 270 5040 0
-2 2 0 1 0 0 50 0 20 0.000 0 0 -1 0 0 5
+2 2 0 1 0 0 50 0 10 0.000 0 0 -1 0 0 5
 	 720 1080 540 1080 540 810 720 810 720 1080
-2 2 0 1 0 0 50 0 20 0.000 0 0 -1 0 0 5
+2 2 0 1 0 0 50 0 10 0.000 0 0 -1 0 0 5
 	 585 540 540 540 540 270 585 270 585 540
-2 2 0 1 0 0 50 0 20 0.000 0 0 -1 0 0 5
+2 2 0 1 0 0 50 0 10 0.000 0 0 -1 0 0 5
 	 765 270 540 270 540 0 765 0 765 270
 2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2
 	1 1 1.00 60.00 120.00
@@ -43,17 +43,21 @@ Single
 	 2250 1305 2250 1440
 2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
 	 1395 1305 1395 1440
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+	 540 1305 540 1440
 4 1 0 50 0 18 9 0.0000 4 90 75 1890 180 1\001
 4 1 0 50 0 18 9 0.0000 4 90 75 2835 450 2\001
 4 1 0 50 0 18 9 0.0000 4 90 75 2745 990 4\001
 4 1 0 50 0 18 9 0.0000 4 90 75 4005 180 2\001
 4 1 0 50 0 18 9 0.0000 4 90 75 2880 720 2\001
 4 1 0 50 0 18 9 0.0000 4 90 75 4905 990 2\001
-4 1 0 50 0 16 9 0.0000 4 90 375 1395 1575 100ns\001
-4 1 0 50 0 16 9 0.0000 4 90 375 2250 1575 200ns\001
-4 1 0 50 0 16 9 0.0000 4 90 375 3060 1575 300ns\001
-4 1 0 50 0 16 9 0.0000 4 90 375 3915 1575 400ns\001
-4 1 0 50 0 16 9 0.0000 4 90 375 4770 1575 500ns\001
+4 1 0 50 0 16 9 0.0000 4 90 375 540 1575 0\001
+4 1 0 50 0 16 9 0.0000 4 90 375 1395 1575 100\001
+4 1 0 50 0 16 9 0.0000 4 90 375 2250 1575 200\001
+4 1 0 50 0 16 9 0.0000 4 90 375 3060 1575 300\001
+4 1 0 50 0 16 9 0.0000 4 90 375 3915 1575 400\001
+4 1 0 50 0 16 9 0.0000 4 90 375 4770 1575 500\001
+4 1 0 50 0 16 9 0.0000 4 90 375 5100 1575 (ns)\001
 4 1 0 50 0 18 9 0.0000 4 90 75 604 720 3\001
 -6
 4 0 0 50 0 16 9 0.0000 4 105 420 0 450 CPU 2\001
diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index 4f0029a..3885787 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -841,7 +841,7 @@ to allow observations of intermediate cache states.
 \end{figure}

 Each horizontal bar represents the observations of a given CPU over time,
-with the black regions to the left indicating the time before the
+with the gray regions to the left indicating the time before the
 corresponding CPU's first measurement.
 During the first 5\,ns, only CPU~3 has an opinion about the value of the
 variable.
diff --git a/utilities/MoreThanOneValue-15CPU.c b/utilities/MoreThanOneValue-15CPU.c
index d9fbc75..e06d78b 100644
--- a/utilities/MoreThanOneValue-15CPU.c
+++ b/utilities/MoreThanOneValue-15CPU.c
@@ -146,6 +146,9 @@ int draw_diagram(int n, int m, const struct color_table_s *col_table, int y_offs
 	       (ruler_tick * i)/tim_width);
 	i++;
     } while (ruler_tick * i < fig_width);
+    printf("4 1 0 50 0 16 9 0.0000 4 90 375 %d %d %s\\001\n",
+	   fig_base + ruler_tick * i - 150, bar_height * CPU_NUM + 400 + y_offset,
+	   "(tick)");
     /* label CPU */
     for (i = 0; i < CPU_NUM; i++) {
 	printf("4 2 0 50 0 16 8.5 0.0000 4 105 420 %d %d CPU %2d\\001\n",
-- 
2.7.4

Re: [PATCH 0/5] memorder: Update table layout

[Akira Yokosawa]

On 2017/09/25 07:00:53 +0900, Akira Yokosawa wrote:
>>From acefbb69d69562438d7a7568f671fc85528d5b5f Mon Sep 17 00:00:00 2001
> From: Akira Yokosawa <akiyks@gmail.com>
> Date: Mon, 25 Sep 2017 06:38:06 +0900
> Subject: [PATCH 0/5] memorder: Update table layout
> 
> Hi Paul,
> 
> My first thought was to update a few experimental tables to catch up
> the changes in memorder.tex.
> But these new tables are likely to change further.
> So I changed my mind and converted the 5 tables in memorder.tex using
> the new scheme of shading alternate rows. 3 of the 5 tables are already
> presented in the style guide.
> In the memorder chapter, we already converted code snippets to the
> "listing" environment. So using the new table layout in this chapter
> sounds reasonable to me.
> 
> Patch #1 updates already experimented tables and a similar one.
> Patch #2 is an attempt to apply new scheme to the remaining table.
> Patch #3 is an improvement of the table changed in Patch #2.
> Patch #4 removes experimental tables in style guide.

The order of #3 and #4 was reversed.

> Patch #5 is a separate patch to improve MoreThanOneValue and
> MoreThanOneValue-15CPU figures.
> 
> I'd like to know if the changes in Patches #2 and #3 work with you.

I mean "changes in Patches #2 and #4".

> 
>         Thanks, Akira
> --
> Akira Yokosawa (5):
>   memorder: Convert tables to alternate-row coloring scheme
>   memorder: Convert 'Summary of Memory Ordering' table to new scheme
>   styleguide: Remove experimental tables updated in memorder chapter
>   memorder: Add multi-column headers to 'Summary of Memory Ordering'
>     table
>   memorder: Reduce color saturation of MoreThanOneValue figure
> 
>  appendix/styleguide/styleguide.tex  | 113 +---------------------
>  memorder/MoreThanOneValue-15CPU.fig |   2 +
>  memorder/MoreThanOneValue.fig       |  26 ++---
>  memorder/memorder.tex               | 183 ++++++++++++++++--------------------
>  perfbook.tex                        |   1 +
>  utilities/MoreThanOneValue-15CPU.c  |   3 +
>  6 files changed, 107 insertions(+), 221 deletions(-)
> 

Re: [PATCH 0/5] memorder: Update table layout

[Paul E. McKenney]

On Mon, Sep 25, 2017 at 07:10:39AM +0900, Akira Yokosawa wrote:
> On 2017/09/25 07:00:53 +0900, Akira Yokosawa wrote:
> >>From acefbb69d69562438d7a7568f671fc85528d5b5f Mon Sep 17 00:00:00 2001
> > From: Akira Yokosawa <akiyks@gmail.com>
> > Date: Mon, 25 Sep 2017 06:38:06 +0900
> > Subject: [PATCH 0/5] memorder: Update table layout
> > 
> > Hi Paul,
> > 
> > My first thought was to update a few experimental tables to catch up
> > the changes in memorder.tex.
> > But these new tables are likely to change further.
> > So I changed my mind and converted the 5 tables in memorder.tex using
> > the new scheme of shading alternate rows. 3 of the 5 tables are already
> > presented in the style guide.
> > In the memorder chapter, we already converted code snippets to the
> > "listing" environment. So using the new table layout in this chapter
> > sounds reasonable to me.
> > 
> > Patch #1 updates already experimented tables and a similar one.
> > Patch #2 is an attempt to apply new scheme to the remaining table.
> > Patch #3 is an improvement of the table changed in Patch #2.
> > Patch #4 removes experimental tables in style guide.
> 
> The order of #3 and #4 was reversed.
> 
> > Patch #5 is a separate patch to improve MoreThanOneValue and
> > MoreThanOneValue-15CPU figures.
> > 
> > I'd like to know if the changes in Patches #2 and #3 work with you.
> 
> I mean "changes in Patches #2 and #4".

Got it.  They look good, so applied, thank you!

							Thanx, Paul

> >         Thanks, Akira
> > --
> > Akira Yokosawa (5):
> >   memorder: Convert tables to alternate-row coloring scheme
> >   memorder: Convert 'Summary of Memory Ordering' table to new scheme
> >   styleguide: Remove experimental tables updated in memorder chapter
> >   memorder: Add multi-column headers to 'Summary of Memory Ordering'
> >     table
> >   memorder: Reduce color saturation of MoreThanOneValue figure
> > 
> >  appendix/styleguide/styleguide.tex  | 113 +---------------------
> >  memorder/MoreThanOneValue-15CPU.fig |   2 +
> >  memorder/MoreThanOneValue.fig       |  26 ++---
> >  memorder/memorder.tex               | 183 ++++++++++++++++--------------------
> >  perfbook.tex                        |   1 +
> >  utilities/MoreThanOneValue-15CPU.c  |   3 +
> >  6 files changed, 107 insertions(+), 221 deletions(-)
> > 
>