[Intel-wired-lan] [PATCH net-next 1/2] ice: Add GPIO pin support for E823 products

[Intel-wired-lan] [PATCH net-next 1/2] ice: Add GPIO pin support for E823 products

[Karol Kolacinski]

Add GPIO pin setup for E823, which is only 1PPS input and output.

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_common.c | 25 ++++++++
 drivers/net/ethernet/intel/ice/ice_common.h |  1 +
 drivers/net/ethernet/intel/ice/ice_ptp.c    | 64 +++++++++++++++++++++
 3 files changed, 90 insertions(+)

diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
index 2a4b68ef7d55..11cc17372b74 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.c
+++ b/drivers/net/ethernet/intel/ice/ice_common.c
@@ -193,6 +193,31 @@ bool ice_is_e810t(struct ice_hw *hw)
 	return false;
 }
 
+/**
+ * ice_is_e823
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E823-L or E823-C based, false if not.
+ */
+bool ice_is_e823(struct ice_hw *hw)
+{
+	switch (hw->device_id) {
+	case ICE_DEV_ID_E823L_BACKPLANE:
+	case ICE_DEV_ID_E823L_SFP:
+	case ICE_DEV_ID_E823L_10G_BASE_T:
+	case ICE_DEV_ID_E823L_1GBE:
+	case ICE_DEV_ID_E823L_QSFP:
+	case ICE_DEV_ID_E823C_BACKPLANE:
+	case ICE_DEV_ID_E823C_QSFP:
+	case ICE_DEV_ID_E823C_SFP:
+	case ICE_DEV_ID_E823C_10G_BASE_T:
+	case ICE_DEV_ID_E823C_SGMII:
+		return true;
+	default:
+		return false;
+	}
+}
+
 /**
  * ice_clear_pf_cfg - Clear PF configuration
  * @hw: pointer to the hardware structure
diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
index f339bdc48062..858b89a39cb6 100644
--- a/drivers/net/ethernet/intel/ice/ice_common.h
+++ b/drivers/net/ethernet/intel/ice/ice_common.h
@@ -198,6 +198,7 @@ void
 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
 		  u64 *prev_stat, u64 *cur_stat);
 bool ice_is_e810t(struct ice_hw *hw);
+bool ice_is_e823(struct ice_hw *hw);
 int
 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
 		     struct ice_aqc_txsched_elem_data *buf);
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 011b727ab190..408beddc1210 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -1788,6 +1788,38 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
 	return err;
 }
 
+/**
+ * ice_ptp_gpio_enable_e823 - Enable/disable ancillary features of PHC
+ * @info: the driver's PTP info structure
+ * @rq: The requested feature to change
+ * @on: Enable/disable flag
+ */
+static int ice_ptp_gpio_enable_e823(struct ptp_clock_info *info,
+				    struct ptp_clock_request *rq, int on)
+{
+	struct ice_pf *pf = ptp_info_to_pf(info);
+	struct ice_perout_channel clk_cfg = {0};
+	int err;
+
+	switch (rq->type) {
+	case PTP_CLK_REQ_PPS:
+		clk_cfg.gpio_pin = PPS_PIN_INDEX;
+		clk_cfg.period = NSEC_PER_SEC;
+		clk_cfg.ena = !!on;
+
+		err = ice_ptp_cfg_clkout(pf, PPS_CLK_GEN_CHAN, &clk_cfg, true);
+		break;
+	case PTP_CLK_REQ_EXTTS:
+		err = ice_ptp_cfg_extts(pf, !!on, rq->extts.index,
+					TIME_SYNC_PIN_INDEX, rq->extts.flags);
+		break;
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	return err;
+}
+
 /**
  * ice_ptp_gettimex64 - Get the time of the clock
  * @info: the driver's PTP info structure
@@ -2239,6 +2271,19 @@ ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
 	}
 }
 
+/**
+ * ice_ptp_setup_pins_e823 - Setup PTP pins in sysfs
+ * @pf: pointer to the PF instance
+ * @info: PTP clock capabilities
+ */
+static void
+ice_ptp_setup_pins_e823(struct ice_pf *pf, struct ptp_clock_info *info)
+{
+	info->pps = 1;
+	info->n_per_out = 0;
+	info->n_ext_ts = 1;
+}
+
 /**
  * ice_ptp_set_funcs_e822 - Set specialized functions for E822 support
  * @pf: Board private structure
@@ -2276,6 +2321,23 @@ ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
 	ice_ptp_setup_pins_e810(pf, info);
 }
 
+/**
+ * ice_ptp_set_funcs_e823 - Set specialized functions for E823 support
+ * @pf: Board private structure
+ * @info: PTP info to fill
+ *
+ * Assign functions to the PTP capabiltiies structure for E823 devices.
+ * Functions which operate across all device families should be set directly
+ * in ice_ptp_set_caps. Only add functions here which are distinct for e823
+ * devices.
+ */
+static void
+ice_ptp_set_funcs_e823(struct ice_pf *pf, struct ptp_clock_info *info)
+{
+	info->enable = ice_ptp_gpio_enable_e823;
+	ice_ptp_setup_pins_e823(pf, info);
+}
+
 /**
  * ice_ptp_set_caps - Set PTP capabilities
  * @pf: Board private structure
@@ -2296,6 +2358,8 @@ static void ice_ptp_set_caps(struct ice_pf *pf)
 
 	if (ice_is_e810(&pf->hw))
 		ice_ptp_set_funcs_e810(pf, info);
+	else if (ice_is_e823(&pf->hw))
+		ice_ptp_set_funcs_e823(pf, info);
 	else
 		ice_ptp_set_funcs_e822(pf, info);
 }
-- 
2.34.1

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[Intel-wired-lan] [PATCH net-next 2/2] ice: Add crosstimestamping on E823 devices

[Karol Kolacinski]

E823 devices on supported platforms can generate a cross timestamp
between the platform ART and the device time. This process allows for
very precise measurement of the difference between the PTP hardware
clock and the platform time.

This is only supported if we know the TSC frequency relative to ART, so
we do not enable this unless the boot CPU has a known TSC frequency (as
required by convert_art_ns_to_tsc).

Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_ptp.c | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
index 408beddc1210..0b37e3d1ef68 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
@@ -2036,7 +2036,7 @@ ice_ptp_get_syncdevicetime(ktime_t *device,
 }
 
 /**
- * ice_ptp_getcrosststamp_e822 - Capture a device cross timestamp
+ * ice_ptp_getcrosststamp_generic - Capture a device cross timestamp
  * @info: the driver's PTP info structure
  * @cts: The memory to fill the cross timestamp info
  *
@@ -2044,15 +2044,15 @@ ice_ptp_get_syncdevicetime(ktime_t *device,
  * clock. Fill the cross timestamp information and report it back to the
  * caller.
  *
- * This is only valid for E822 devices which have support for generating the
- * cross timestamp via PCIe PTM.
+ * This is only valid for E822 and E823 devices which have support for
+ * generating the cross timestamp via PCIe PTM.
  *
  * In order to correctly correlate the ART timestamp back to the TSC time, the
  * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
  */
 static int
-ice_ptp_getcrosststamp_e822(struct ptp_clock_info *info,
-			    struct system_device_crosststamp *cts)
+ice_ptp_getcrosststamp_generic(struct ptp_clock_info *info,
+			       struct system_device_crosststamp *cts)
 {
 	struct ice_pf *pf = ptp_info_to_pf(info);
 
@@ -2300,7 +2300,7 @@ ice_ptp_set_funcs_e822(struct ice_pf *pf, struct ptp_clock_info *info)
 #ifdef CONFIG_ICE_HWTS
 	if (boot_cpu_has(X86_FEATURE_ART) &&
 	    boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
-		info->getcrosststamp = ice_ptp_getcrosststamp_e822;
+		info->getcrosststamp = ice_ptp_getcrosststamp_generic;
 #endif /* CONFIG_ICE_HWTS */
 }
 
@@ -2334,6 +2334,12 @@ ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
 static void
 ice_ptp_set_funcs_e823(struct ice_pf *pf, struct ptp_clock_info *info)
 {
+#ifdef CONFIG_ICE_HWTS
+	if (boot_cpu_has(X86_FEATURE_ART) &&
+	    boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
+		info->getcrosststamp = ice_ptp_getcrosststamp_generic;
+#endif /* CONFIG_ICE_HWTS */
+
 	info->enable = ice_ptp_gpio_enable_e823;
 	ice_ptp_setup_pins_e823(pf, info);
 }
-- 
2.34.1

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Re: [Intel-wired-lan] [PATCH net-next 2/2] ice: Add crosstimestamping on E823 devices

[Tony Nguyen]

On 9/16/2022 6:14 AM, Karol Kolacinski wrote:
> E823 devices on supported platforms can generate a cross timestamp
> between the platform ART and the device time. This process allows for
> very precise measurement of the difference between the PTP hardware
> clock and the platform time.
> 
> This is only supported if we know the TSC frequency relative to ART, so
> we do not enable this unless the boot CPU has a known TSC frequency (as
> required by convert_art_ns_to_tsc).
> 
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
>   drivers/net/ethernet/intel/ice/ice_ptp.c | 18 ++++++++++++------
>   1 file changed, 12 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
> index 408beddc1210..0b37e3d1ef68 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
> @@ -2036,7 +2036,7 @@ ice_ptp_get_syncdevicetime(ktime_t *device,
>   }
>   
>   /**
> - * ice_ptp_getcrosststamp_e822 - Capture a device cross timestamp
> + * ice_ptp_getcrosststamp_generic - Capture a device cross timestamp

IMO generic is implied if there is not a specific device put to it. I 
don't think we need to specifically call it generic...

>    * @info: the driver's PTP info structure
>    * @cts: The memory to fill the cross timestamp info
>    *
> @@ -2044,15 +2044,15 @@ ice_ptp_get_syncdevicetime(ktime_t *device,
>    * clock. Fill the cross timestamp information and report it back to the
>    * caller.
>    *
> - * This is only valid for E822 devices which have support for generating the
> - * cross timestamp via PCIe PTM.
> + * This is only valid for E822 and E823 devices which have support for

... however it's still kind of device specific as it's for E822 and 
E823. Seems like E822 functions are used for both E822 and E823 so I 
think leaving the name as is or, perhaps, calling it '_e82x'?

> + * generating the cross timestamp via PCIe PTM.
>    *
>    * In order to correctly correlate the ART timestamp back to the TSC time, the
>    * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
>    */
>   static int
> -ice_ptp_getcrosststamp_e822(struct ptp_clock_info *info,
> -			    struct system_device_crosststamp *cts)
> +ice_ptp_getcrosststamp_generic(struct ptp_clock_info *info,
> +			       struct system_device_crosststamp *cts)
>   {
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Re: [Intel-wired-lan] [PATCH net-next 1/2] ice: Add GPIO pin support for E823 products

[Tony Nguyen]

On 9/16/2022 6:14 AM, Karol Kolacinski wrote:
> Add GPIO pin setup for E823, which is only 1PPS input and output.

Is this different than this patch [1] which is already applied?

If yes, this should be a v2 with a change log. If no, can you please 
clarify why it's being resent. There's no additional information and/or 
cover letter so I'm not sure what the intention is.

> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
>   drivers/net/ethernet/intel/ice/ice_common.c | 25 ++++++++
>   drivers/net/ethernet/intel/ice/ice_common.h |  1 +
>   drivers/net/ethernet/intel/ice/ice_ptp.c    | 64 +++++++++++++++++++++
>   3 files changed, 90 insertions(+)
> 
> diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c
> index 2a4b68ef7d55..11cc17372b74 100644
> --- a/drivers/net/ethernet/intel/ice/ice_common.c
> +++ b/drivers/net/ethernet/intel/ice/ice_common.c
> @@ -193,6 +193,31 @@ bool ice_is_e810t(struct ice_hw *hw)
>   	return false;
>   }
>   
> +/**
> + * ice_is_e823
> + * @hw: pointer to the hardware structure
> + *
> + * returns true if the device is E823-L or E823-C based, false if not.
> + */
> +bool ice_is_e823(struct ice_hw *hw)
> +{
> +	switch (hw->device_id) {
> +	case ICE_DEV_ID_E823L_BACKPLANE:
> +	case ICE_DEV_ID_E823L_SFP:
> +	case ICE_DEV_ID_E823L_10G_BASE_T:
> +	case ICE_DEV_ID_E823L_1GBE:
> +	case ICE_DEV_ID_E823L_QSFP:
> +	case ICE_DEV_ID_E823C_BACKPLANE:
> +	case ICE_DEV_ID_E823C_QSFP:
> +	case ICE_DEV_ID_E823C_SFP:
> +	case ICE_DEV_ID_E823C_10G_BASE_T:
> +	case ICE_DEV_ID_E823C_SGMII:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
>   /**
>    * ice_clear_pf_cfg - Clear PF configuration
>    * @hw: pointer to the hardware structure
> diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h
> index f339bdc48062..858b89a39cb6 100644
> --- a/drivers/net/ethernet/intel/ice/ice_common.h
> +++ b/drivers/net/ethernet/intel/ice/ice_common.h
> @@ -198,6 +198,7 @@ void
>   ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
>   		  u64 *prev_stat, u64 *cur_stat);
>   bool ice_is_e810t(struct ice_hw *hw);
> +bool ice_is_e823(struct ice_hw *hw);
>   int
>   ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
>   		     struct ice_aqc_txsched_elem_data *buf);
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c
> index 011b727ab190..408beddc1210 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c
> @@ -1788,6 +1788,38 @@ ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
>   	return err;
>   }
>   
> +/**
> + * ice_ptp_gpio_enable_e823 - Enable/disable ancillary features of PHC
> + * @info: the driver's PTP info structure
> + * @rq: The requested feature to change
> + * @on: Enable/disable flag
> + */
> +static int ice_ptp_gpio_enable_e823(struct ptp_clock_info *info,
> +				    struct ptp_clock_request *rq, int on)
> +{
> +	struct ice_pf *pf = ptp_info_to_pf(info);
> +	struct ice_perout_channel clk_cfg = {0};
> +	int err;
> +
> +	switch (rq->type) {
> +	case PTP_CLK_REQ_PPS:
> +		clk_cfg.gpio_pin = PPS_PIN_INDEX;
> +		clk_cfg.period = NSEC_PER_SEC;
> +		clk_cfg.ena = !!on;
> +
> +		err = ice_ptp_cfg_clkout(pf, PPS_CLK_GEN_CHAN, &clk_cfg, true);
> +		break;
> +	case PTP_CLK_REQ_EXTTS:
> +		err = ice_ptp_cfg_extts(pf, !!on, rq->extts.index,
> +					TIME_SYNC_PIN_INDEX, rq->extts.flags);
> +		break;
> +	default:
> +		return -EOPNOTSUPP;
> +	}
> +
> +	return err;
> +}
> +
>   /**
>    * ice_ptp_gettimex64 - Get the time of the clock
>    * @info: the driver's PTP info structure
> @@ -2239,6 +2271,19 @@ ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
>   	}
>   }
>   
> +/**
> + * ice_ptp_setup_pins_e823 - Setup PTP pins in sysfs
> + * @pf: pointer to the PF instance
> + * @info: PTP clock capabilities
> + */
> +static void
> +ice_ptp_setup_pins_e823(struct ice_pf *pf, struct ptp_clock_info *info)
> +{
> +	info->pps = 1;
> +	info->n_per_out = 0;
> +	info->n_ext_ts = 1;
> +}
> +
>   /**
>    * ice_ptp_set_funcs_e822 - Set specialized functions for E822 support
>    * @pf: Board private structure
> @@ -2276,6 +2321,23 @@ ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
>   	ice_ptp_setup_pins_e810(pf, info);
>   }
>   
> +/**
> + * ice_ptp_set_funcs_e823 - Set specialized functions for E823 support
> + * @pf: Board private structure
> + * @info: PTP info to fill
> + *
> + * Assign functions to the PTP capabiltiies structure for E823 devices.
> + * Functions which operate across all device families should be set directly
> + * in ice_ptp_set_caps. Only add functions here which are distinct for e823
> + * devices.
> + */
> +static void
> +ice_ptp_set_funcs_e823(struct ice_pf *pf, struct ptp_clock_info *info)
> +{
> +	info->enable = ice_ptp_gpio_enable_e823;
> +	ice_ptp_setup_pins_e823(pf, info);
> +}
> +
>   /**
>    * ice_ptp_set_caps - Set PTP capabilities
>    * @pf: Board private structure
> @@ -2296,6 +2358,8 @@ static void ice_ptp_set_caps(struct ice_pf *pf)
>   
>   	if (ice_is_e810(&pf->hw))
>   		ice_ptp_set_funcs_e810(pf, info);
> +	else if (ice_is_e823(&pf->hw))
> +		ice_ptp_set_funcs_e823(pf, info);
>   	else
>   		ice_ptp_set_funcs_e822(pf, info);
>   }

[1] 
https://patchwork.ozlabs.org/project/intel-wired-lan/patch/20220914100429.261290-1-karol.kolacinski@intel.com/
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Re: [Intel-wired-lan] [PATCH net-next 1/2] ice: Add GPIO pin support for E823 products

[Kolacinski, Karol]

Hi Tony,

> Is this different than this patch [1] which is already applied?
The patch is the same. I submitted the second one in a series with this one by mistake.

Thanks,
Karol
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