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From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 6/9] ARM: socfpga: Set default DTB address on A10
Date: Wed, 21 Nov 2018 15:22:58 +0100	[thread overview]
Message-ID: <bad8cf2b-7c47-6083-004f-945202f3ee67@denx.de> (raw)
In-Reply-To: <1542796908-7947-7-git-send-email-tien.fong.chee@intel.com>

On 11/21/2018 11:41 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>

Again, not your patch, please don't change authorship.

http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=commit;h=eb32e568869b5f91fe34efb2642875a8da5f0ebd

> Set default DT blob address on A10 SoCDK, since this SoC uses OF
> separate configuration. The 0xf0000 address is just below the text
> base and still leaves enough room for the DT to grow.

Why is this needed ?

> Signed-off-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/mach-socfpga/board.c |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
> index 7c8c05c..436a8a8 100644
> --- a/arch/arm/mach-socfpga/board.c
> +++ b/arch/arm/mach-socfpga/board.c
> @@ -86,3 +86,11 @@ int g_dnl_board_usb_cable_connected(void)
>  	return 1;
>  }
>  #endif
> +
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) && \
> +!defined(CONFIG_SPL_BUILD) && defined(CONFIG_OF_SEPARATE)
> +void *board_fdt_blob_setup(void)
> +{
> +	return (void *)0xf00000;
> +}
> +#endif
> 


-- 
Best regards,
Marek Vasut

  reply	other threads:[~2018-11-21 14:22 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-21 10:41 [U-Boot] [PATCH 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2018-11-21 10:41 ` [U-Boot] [PATCH 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2018-11-21 14:11   ` Marek Vasut
2018-11-23  9:19     ` Chee, Tien Fong
2018-11-23 12:23       ` Marek Vasut
2018-11-26  9:44         ` Chee, Tien Fong
2018-11-26 11:15           ` Marek Vasut
2018-11-27  8:45             ` Chee, Tien Fong
2018-11-27 12:07               ` Marek Vasut
2018-11-28 14:49                 ` Chee, Tien Fong
2018-11-28 15:10                   ` Marek Vasut
2018-11-28 15:36                     ` Chee, Tien Fong
2018-11-28 16:17                     ` Chee, Tien Fong
2018-11-28 17:55                       ` Marek Vasut
2018-12-14  8:07                         ` Chee, Tien Fong
2018-11-21 10:41 ` [U-Boot] [PATCH 2/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2018-11-21 14:18   ` Marek Vasut
2018-11-23  9:43     ` Chee, Tien Fong
2018-11-23 12:28       ` Marek Vasut
2018-11-26 10:09         ` Chee, Tien Fong
2018-11-26 11:18           ` Marek Vasut
2018-11-27  8:54             ` Chee, Tien Fong
2018-11-27 12:08               ` Marek Vasut
2018-11-28 14:53                 ` Chee, Tien Fong
2018-11-28 15:11                   ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 3/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2018-11-21 14:19   ` Marek Vasut
2018-11-23  9:51     ` Chee, Tien Fong
2018-11-23 12:31       ` Marek Vasut
2018-11-26 10:10         ` Chee, Tien Fong
2018-11-26 11:20           ` Marek Vasut
2018-11-27  8:55             ` Chee, Tien Fong
2018-11-27 12:08               ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 4/9] ARM: socfpga: Bundle U-Boot fitImage into SFP on Arria10 tien.fong.chee at intel.com
2018-11-21 14:21   ` Marek Vasut
2018-11-23  9:54     ` Chee, Tien Fong
2018-11-23 12:40       ` Marek Vasut
2018-11-26 10:30         ` Chee, Tien Fong
2018-11-26 11:22           ` Marek Vasut
2018-11-27  9:00             ` Chee, Tien Fong
2018-11-27 12:09               ` Marek Vasut
2018-11-28 14:43                 ` Chee, Tien Fong
2018-11-28 15:11                   ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 5/9] ARM: socfpga: Add SPL fitImage config match tien.fong.chee at intel.com
2018-11-21 14:21   ` Marek Vasut
2018-11-23 10:05     ` Chee, Tien Fong
2018-11-23 12:34       ` Marek Vasut
2018-11-26 10:11         ` Chee, Tien Fong
2018-11-21 10:41 ` [U-Boot] [PATCH 6/9] ARM: socfpga: Set default DTB address on A10 tien.fong.chee at intel.com
2018-11-21 14:22   ` Marek Vasut [this message]
2018-11-23 10:10     ` Chee, Tien Fong
2018-11-23 12:39       ` Marek Vasut
2018-11-21 10:41 ` [U-Boot] [PATCH 7/9] ARM: socfpga: Use custom header target buffer in SPL tien.fong.chee at intel.com
2018-11-21 10:41 ` [U-Boot] [PATCH 8/9] ARM: socfpga: Add default fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2018-11-21 10:41 ` [U-Boot] [PATCH 9/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com

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