* [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1
@ 2022-10-18 7:22 ` Eliav Farber
0 siblings, 0 replies; 4+ messages in thread
From: Eliav Farber @ 2022-10-18 7:22 UTC (permalink / raw)
To: tudor.ambarus, pratyush, michael, miquel.raynal, richard,
vigneshr, linux-mtd, linux-kernel
Cc: talel, jonnyc, hhhawa, hanochu, farbere, itamark, shellykz,
amitlavi, dkl
n25q256ax1 [1] uses the 4 bit Block Protection scheme and supports
Top/Bottom protection via the BP and TB bits of the Status Register.
BP3 is located in bit 6 of the Status Register.
Tested on n25q256ax1.
[1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
Signed-off-by: Eliav Farber <farbere@amazon.com>
---
drivers/mtd/spi-nor/micron-st.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3c9681a3f7a3..7cf5fbb28f99 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -206,6 +206,8 @@ static const struct flash_info st_nor_parts[] = {
MFR_FLAGS(USE_FSR)
},
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
+ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
MFR_FLAGS(USE_FSR)
},
--
2.37.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1
@ 2022-10-18 7:22 ` Eliav Farber
0 siblings, 0 replies; 4+ messages in thread
From: Eliav Farber @ 2022-10-18 7:22 UTC (permalink / raw)
To: tudor.ambarus, pratyush, michael, miquel.raynal, richard,
vigneshr, linux-mtd, linux-kernel
Cc: talel, jonnyc, hhhawa, hanochu, farbere, itamark, shellykz,
amitlavi, dkl
n25q256ax1 [1] uses the 4 bit Block Protection scheme and supports
Top/Bottom protection via the BP and TB bits of the Status Register.
BP3 is located in bit 6 of the Status Register.
Tested on n25q256ax1.
[1] https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
Signed-off-by: Eliav Farber <farbere@amazon.com>
---
drivers/mtd/spi-nor/micron-st.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3c9681a3f7a3..7cf5fbb28f99 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -206,6 +206,8 @@ static const struct flash_info st_nor_parts[] = {
MFR_FLAGS(USE_FSR)
},
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512)
+ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP |
+ SPI_NOR_BP3_SR_BIT6)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ)
MFR_FLAGS(USE_FSR)
},
--
2.37.1
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1
2022-10-18 7:22 ` Eliav Farber
@ 2022-10-18 7:45 ` Michael Walle
-1 siblings, 0 replies; 4+ messages in thread
From: Michael Walle @ 2022-10-18 7:45 UTC (permalink / raw)
To: Eliav Farber
Cc: tudor.ambarus, pratyush, miquel.raynal, richard, vigneshr,
linux-mtd, linux-kernel, talel, jonnyc, hhhawa, hanochu, itamark,
shellykz, amitlavi, dkl
Hi,
Am 2022-10-18 09:22, schrieb Eliav Farber:
> n25q256ax1 [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on n25q256ax1.
>
> [1]
> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
>
> Signed-off-by: Eliav Farber <farbere@amazon.com>
Looks good. But could you please dump the SFDP tables as
described in [1].
-michael
[1]
https://lore.kernel.org/linux-mtd/4304e19f3399a0a6e856119d01ccabe0@walle.cc/
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1
@ 2022-10-18 7:45 ` Michael Walle
0 siblings, 0 replies; 4+ messages in thread
From: Michael Walle @ 2022-10-18 7:45 UTC (permalink / raw)
To: Eliav Farber
Cc: tudor.ambarus, pratyush, miquel.raynal, richard, vigneshr,
linux-mtd, linux-kernel, talel, jonnyc, hhhawa, hanochu, itamark,
shellykz, amitlavi, dkl
Hi,
Am 2022-10-18 09:22, schrieb Eliav Farber:
> n25q256ax1 [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on n25q256ax1.
>
> [1]
> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
>
> Signed-off-by: Eliav Farber <farbere@amazon.com>
Looks good. But could you please dump the SFDP tables as
described in [1].
-michael
[1]
https://lore.kernel.org/linux-mtd/4304e19f3399a0a6e856119d01ccabe0@walle.cc/
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-10-18 7:46 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-10-18 7:22 [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1 Eliav Farber
2022-10-18 7:22 ` Eliav Farber
2022-10-18 7:45 ` Michael Walle
2022-10-18 7:45 ` Michael Walle
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