* [Qemu-devel] [PATCH target-arm v9 1/1] target-arm: Implements the ARM PMCCNTR register
@ 2014-02-27 23:15 Alistair Francis
2014-03-07 5:19 ` Alistair Francis
0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2014-02-27 23:15 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, peter.crosthwaite, alistair.francis
This patch implements the ARM PMCCNTR register including
the disable and reset components of the PMCR register.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
---
V9: Completely #ifndef out the PMCR and PMCCNTR registers. Also use
CONFIG_USER_ONLY instead of CONFIG_LINUX_USER
V8: Only implement the register in system mode to make sure it doesn't
break compilation of linux-user targets.
V7: Fixed a bug that caused the cycle count scaling to be determined
by the PMCRDP register instead of PMCRD. Also stopped PMCRDP from
disabling the counter. Thanks to Peter Maydell
V6: Rebase to include Peter Maydell's 'Convert performance monitor
reginfo to accesfn' patch. Remove the raw_fn's as the read/write
functions already do what is required.
V5: Implement the actual write function to make sure that
migration works correctly. Also includes the raw_read/write as
the normal read/write functions depend on the pmcr register. So
they don't allow for the pmccntr register to be written first.
V4: Some bug fixes pointed out by Peter Crosthwaite. Including
increasing the accuracy of the timer.
V3: Fixed up incorrect reset, disable and enable handling that
was submitted in V2. The patch should now also handle changing
of the clock scaling.
V2: Incorporated the comments that Peter Maydell and Peter
Crosthwaite had. Now the implementation only requires one
CPU state
target-arm/cpu.h | 4 ++
target-arm/helper.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 89 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3c8a2db..14fd1ae 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -215,6 +215,10 @@ typedef struct CPUARMState {
uint32_t c15_diagnostic; /* diagnostic register */
uint32_t c15_power_diagnostic;
uint32_t c15_power_control; /* power control */
+ /* If the counter is enabled, this stores the last time the counter
+ * was reset. Otherwise it stores the counter value
+ */
+ uint32_t c15_ccnt;
} cp15;
struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index b547f04..21d14c9 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -11,6 +11,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address,
int access_type, int is_user,
hwaddr *phys_ptr, int *prot,
target_ulong *page_size);
+
+/* Definitions for the PMCCNTR and PMCR registers */
+#define PMCRD 0x8
+#define PMCRC 0x4
+#define PMCRE 0x1
#endif
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
@@ -475,13 +480,84 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
return CP_ACCESS_OK;
}
+#ifndef CONFIG_USER_ONLY
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ /* Don't computer the number of ticks in user mode */
+ uint32_t temp_ticks;
+
+ temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
+ get_ticks_per_sec() / 1000000;
+
+ if (env->cp15.c9_pmcr & PMCRE) {
+ /* If the counter is enabled */
+ if (env->cp15.c9_pmcr & PMCRD) {
+ /* Increment once every 64 processor clock cycles */
+ env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
+ } else {
+ env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
+ }
+ }
+
+ if (value & PMCRC) {
+ /* The counter has been reset */
+ env->cp15.c15_ccnt = 0;
+ }
+
/* only the DP, X, D and E bits are writable */
env->cp15.c9_pmcr &= ~0x39;
env->cp15.c9_pmcr |= (value & 0x39);
+
+ if (env->cp15.c9_pmcr & PMCRE) {
+ if (env->cp15.c9_pmcr & PMCRD) {
+ /* Increment once every 64 processor clock cycles */
+ temp_ticks /= 64;
+ }
+ env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
+ }
+}
+
+static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ uint32_t total_ticks;
+
+ if (!(env->cp15.c9_pmcr & PMCRE)) {
+ /* Counter is disabled, do not change value */
+ return env->cp15.c15_ccnt;
+ }
+
+ total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
+ get_ticks_per_sec() / 1000000;
+
+ if (env->cp15.c9_pmcr & PMCRD) {
+ /* Increment once every 64 processor clock cycles */
+ total_ticks /= 64;
+ }
+ return total_ticks - env->cp15.c15_ccnt;
+}
+
+static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ uint32_t total_ticks;
+
+ if (!(env->cp15.c9_pmcr & PMCRE)) {
+ /* Counter is disabled, set the absolute value */
+ env->cp15.c15_ccnt = value;
+ return;
+ }
+
+ total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
+ get_ticks_per_sec() / 1000000;
+
+ if (env->cp15.c9_pmcr & PMCRD) {
+ /* Increment once every 64 processor clock cycles */
+ total_ticks /= 64;
+ }
+ env->cp15.c15_ccnt = total_ticks - value;
}
+#endif
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
@@ -595,10 +671,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
.access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
.accessfn = pmreg_access },
- /* Unimplemented, RAZ/WI. */
+ #ifndef CONFIG_USER_ONLY
{ .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
- .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
+ .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
+ .readfn = pmccntr_read, .writefn = pmccntr_write,
.accessfn = pmreg_access },
+ #endif
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
.access = PL0_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
@@ -1624,8 +1702,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (arm_feature(env, ARM_FEATURE_V7)) {
/* v7 performance monitor control register: same implementor
- * field as main ID register, and we implement no event counters.
+ * field as main ID register, and we implement only the cycle
+ * count register.
*/
+ #ifndef CONFIG_USER_ONLY
ARMCPRegInfo pmcr = {
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
.access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
@@ -1633,11 +1713,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = pmreg_access, .writefn = pmcr_write,
.raw_writefn = raw_write,
};
+ define_one_arm_cp_reg(cpu, &pmcr);
+ #endif
ARMCPRegInfo clidr = {
.name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
};
- define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &clidr);
define_arm_cp_regs(cpu, v7_cp_reginfo);
} else {
--
1.7.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH target-arm v9 1/1] target-arm: Implements the ARM PMCCNTR register
2014-02-27 23:15 [Qemu-devel] [PATCH target-arm v9 1/1] target-arm: Implements the ARM PMCCNTR register Alistair Francis
@ 2014-03-07 5:19 ` Alistair Francis
2014-03-10 12:49 ` Peter Maydell
0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2014-03-07 5:19 UTC (permalink / raw)
To: Alistair Francis
Cc: Peter Maydell, Peter Crosthwaite, qemu-devel@nongnu.org Developers
Ping
On Fri, Feb 28, 2014 at 9:15 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> This patch implements the ARM PMCCNTR register including
> the disable and reset components of the PMCR register.
>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V9: Completely #ifndef out the PMCR and PMCCNTR registers. Also use
> CONFIG_USER_ONLY instead of CONFIG_LINUX_USER
> V8: Only implement the register in system mode to make sure it doesn't
> break compilation of linux-user targets.
> V7: Fixed a bug that caused the cycle count scaling to be determined
> by the PMCRDP register instead of PMCRD. Also stopped PMCRDP from
> disabling the counter. Thanks to Peter Maydell
> V6: Rebase to include Peter Maydell's 'Convert performance monitor
> reginfo to accesfn' patch. Remove the raw_fn's as the read/write
> functions already do what is required.
> V5: Implement the actual write function to make sure that
> migration works correctly. Also includes the raw_read/write as
> the normal read/write functions depend on the pmcr register. So
> they don't allow for the pmccntr register to be written first.
> V4: Some bug fixes pointed out by Peter Crosthwaite. Including
> increasing the accuracy of the timer.
> V3: Fixed up incorrect reset, disable and enable handling that
> was submitted in V2. The patch should now also handle changing
> of the clock scaling.
> V2: Incorporated the comments that Peter Maydell and Peter
> Crosthwaite had. Now the implementation only requires one
> CPU state
>
> target-arm/cpu.h | 4 ++
> target-arm/helper.c | 89 ++++++++++++++++++++++++++++++++++++++++++++++++--
> 2 files changed, 89 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 3c8a2db..14fd1ae 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -215,6 +215,10 @@ typedef struct CPUARMState {
> uint32_t c15_diagnostic; /* diagnostic register */
> uint32_t c15_power_diagnostic;
> uint32_t c15_power_control; /* power control */
> + /* If the counter is enabled, this stores the last time the counter
> + * was reset. Otherwise it stores the counter value
> + */
> + uint32_t c15_ccnt;
> } cp15;
>
> struct {
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b547f04..21d14c9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -11,6 +11,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address,
> int access_type, int is_user,
> hwaddr *phys_ptr, int *prot,
> target_ulong *page_size);
> +
> +/* Definitions for the PMCCNTR and PMCR registers */
> +#define PMCRD 0x8
> +#define PMCRC 0x4
> +#define PMCRE 0x1
> #endif
>
> static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
> @@ -475,13 +480,84 @@ static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
> return CP_ACCESS_OK;
> }
>
> +#ifndef CONFIG_USER_ONLY
> static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + /* Don't computer the number of ticks in user mode */
> + uint32_t temp_ticks;
> +
> + temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
> + get_ticks_per_sec() / 1000000;
> +
> + if (env->cp15.c9_pmcr & PMCRE) {
> + /* If the counter is enabled */
> + if (env->cp15.c9_pmcr & PMCRD) {
> + /* Increment once every 64 processor clock cycles */
> + env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
> + } else {
> + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
> + }
> + }
> +
> + if (value & PMCRC) {
> + /* The counter has been reset */
> + env->cp15.c15_ccnt = 0;
> + }
> +
> /* only the DP, X, D and E bits are writable */
> env->cp15.c9_pmcr &= ~0x39;
> env->cp15.c9_pmcr |= (value & 0x39);
> +
> + if (env->cp15.c9_pmcr & PMCRE) {
> + if (env->cp15.c9_pmcr & PMCRD) {
> + /* Increment once every 64 processor clock cycles */
> + temp_ticks /= 64;
> + }
> + env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
> + }
> +}
> +
> +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
> +{
> + uint32_t total_ticks;
> +
> + if (!(env->cp15.c9_pmcr & PMCRE)) {
> + /* Counter is disabled, do not change value */
> + return env->cp15.c15_ccnt;
> + }
> +
> + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
> + get_ticks_per_sec() / 1000000;
> +
> + if (env->cp15.c9_pmcr & PMCRD) {
> + /* Increment once every 64 processor clock cycles */
> + total_ticks /= 64;
> + }
> + return total_ticks - env->cp15.c15_ccnt;
> +}
> +
> +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> + uint64_t value)
> +{
> + uint32_t total_ticks;
> +
> + if (!(env->cp15.c9_pmcr & PMCRE)) {
> + /* Counter is disabled, set the absolute value */
> + env->cp15.c15_ccnt = value;
> + return;
> + }
> +
> + total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
> + get_ticks_per_sec() / 1000000;
> +
> + if (env->cp15.c9_pmcr & PMCRD) {
> + /* Increment once every 64 processor clock cycles */
> + total_ticks /= 64;
> + }
> + env->cp15.c15_ccnt = total_ticks - value;
> }
> +#endif
>
> static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> @@ -595,10 +671,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
> { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
> .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
> .accessfn = pmreg_access },
> - /* Unimplemented, RAZ/WI. */
> + #ifndef CONFIG_USER_ONLY
> { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
> - .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
> + .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
> + .readfn = pmccntr_read, .writefn = pmccntr_write,
> .accessfn = pmreg_access },
> + #endif
> { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
> .access = PL0_RW,
> .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
> @@ -1624,8 +1702,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> }
> if (arm_feature(env, ARM_FEATURE_V7)) {
> /* v7 performance monitor control register: same implementor
> - * field as main ID register, and we implement no event counters.
> + * field as main ID register, and we implement only the cycle
> + * count register.
> */
> + #ifndef CONFIG_USER_ONLY
> ARMCPRegInfo pmcr = {
> .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
> .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
> @@ -1633,11 +1713,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .accessfn = pmreg_access, .writefn = pmcr_write,
> .raw_writefn = raw_write,
> };
> + define_one_arm_cp_reg(cpu, &pmcr);
> + #endif
> ARMCPRegInfo clidr = {
> .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
> };
> - define_one_arm_cp_reg(cpu, &pmcr);
> define_one_arm_cp_reg(cpu, &clidr);
> define_arm_cp_regs(cpu, v7_cp_reginfo);
> } else {
> --
> 1.7.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH target-arm v9 1/1] target-arm: Implements the ARM PMCCNTR register
2014-03-07 5:19 ` Alistair Francis
@ 2014-03-10 12:49 ` Peter Maydell
0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2014-03-10 12:49 UTC (permalink / raw)
To: Alistair Francis; +Cc: Peter Crosthwaite, qemu-devel@nongnu.org Developers
On 7 March 2014 05:19, Alistair Francis <alistair.francis@xilinx.com> wrote:
> Ping
>
> On Fri, Feb 28, 2014 at 9:15 AM, Alistair Francis
> <alistair.francis@xilinx.com> wrote:
>> This patch implements the ARM PMCCNTR register including
>> the disable and reset components of the PMCR register.
>>
>> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Applied to target-arm.next, thanks. (I fixed a minor
style nit where you weren't starting your #ifdef lines
in column 1.)
thanks
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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2014-02-27 23:15 [Qemu-devel] [PATCH target-arm v9 1/1] target-arm: Implements the ARM PMCCNTR register Alistair Francis
2014-03-07 5:19 ` Alistair Francis
2014-03-10 12:49 ` Peter Maydell
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