From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 12/13] clk: qcom: cpu-8996: change setup sequence to follow vendor kernel
Date: Thu, 12 Jan 2023 15:42:21 +0100 [thread overview]
Message-ID: <bc20f230-5ebc-676c-2165-031b82dca063@linaro.org> (raw)
In-Reply-To: <20230111192004.2509750-13-dmitry.baryshkov@linaro.org>
On 11.01.2023 20:20, Dmitry Baryshkov wrote:
> Add missing register writes to CPU clocks setup procedure. This makes it
> follow the setup procedure used in msm-3.18 kernel.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/clk/qcom/clk-cpu-8996.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
> index b53cddc4bca3..78a18b95c48b 100644
> --- a/drivers/clk/qcom/clk-cpu-8996.c
> +++ b/drivers/clk/qcom/clk-cpu-8996.c
> @@ -76,10 +76,16 @@ enum _pmux_input {
> #define PWRCL_REG_OFFSET 0x0
> #define PERFCL_REG_OFFSET 0x80000
> #define MUX_OFFSET 0x40
> +#define CLK_CTL_OFFSET 0x44
> +#define CLK_CTL_AUTO_CLK_SEL BIT(8)
> #define ALT_PLL_OFFSET 0x100
> #define SSSCTL_OFFSET 0x160
> +#define PSCTL_OFFSET 0x164
>
> #define PMUX_MASK 0x3
> +#define MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK GENMASK(5, 4)
> +#define MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL \
> + FIELD_PREP(MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK, 0x03)
>
> static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
> [PLL_OFF_L_VAL] = 0x04,
> @@ -439,6 +445,14 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
> /* Ensure write goes through before PLLs are reconfigured */
> udelay(5);
>
> + /* Set the auto clock sel always-on source to GPLL0/2 (300MHz) */
> + regmap_update_bits(regmap, PWRCL_REG_OFFSET + MUX_OFFSET,
> + MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
> + MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
> + regmap_update_bits(regmap, PERFCL_REG_OFFSET + MUX_OFFSET,
> + MUX_AUTO_CLK_SEL_ALWAYS_ON_MASK,
> + MUX_AUTO_CLK_SEL_ALWAYS_ON_GPLL0_SEL);
> +
> clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
> clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
> clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
> @@ -447,11 +461,24 @@ static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
> /* Wait for PLL(s) to lock */
> udelay(50);
>
> + /* Enable auto clock selection for both clusters */
> + regmap_update_bits(regmap, PWRCL_REG_OFFSET + CLK_CTL_OFFSET,
> + CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
> + regmap_update_bits(regmap, PERFCL_REG_OFFSET + CLK_CTL_OFFSET,
> + CLK_CTL_AUTO_CLK_SEL, CLK_CTL_AUTO_CLK_SEL);
> +
> + /* Ensure write goes through before muxes are switched */
> + udelay(5);
> +
> qcom_cpu_clk_msm8996_acd_init(regmap);
>
> + /* Pulse swallower and soft-start settings */
> + regmap_write(regmap, PWRCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
> + regmap_write(regmap, PERFCL_REG_OFFSET + PSCTL_OFFSET, 0x00030005);
> +
> /* Switch clusters to use the ACD leg */
> - regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x2);
> - regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x2);
> + regmap_write(regmap, PWRCL_REG_OFFSET + MUX_OFFSET, 0x32);
> + regmap_write(regmap, PERFCL_REG_OFFSET + MUX_OFFSET, 0x32);
>
> for (i = 0; i < ARRAY_SIZE(cpu_msm8996_hw_clks); i++) {
> ret = devm_clk_hw_register(dev, cpu_msm8996_hw_clks[i]);
next prev parent reply other threads:[~2023-01-12 14:56 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-11 19:19 [PATCH 00/13] clk: qcom: cpu-8996: stability fixes Dmitry Baryshkov
2023-01-11 19:19 ` [PATCH 01/13] clk: qcom: clk-alpha-pll: program PLL_TEST/PLL_TEST_U if required Dmitry Baryshkov
2023-01-11 19:19 ` [PATCH 02/13] clk: qcom: cpu-8996: correct PLL programming Dmitry Baryshkov
2023-01-11 20:57 ` Konrad Dybcio
2023-01-11 19:19 ` [PATCH 03/13] clk: qcom: cpu-8996: fix the init clock rate Dmitry Baryshkov
2023-01-11 20:58 ` Konrad Dybcio
2023-01-11 21:51 ` Dmitry Baryshkov
2023-01-12 12:12 ` Konrad Dybcio
2023-01-11 19:19 ` [PATCH 04/13] clk: qcom: cpu-8996: support using GPLL0 as SMUX input Dmitry Baryshkov
2023-01-11 19:26 ` Stephen Boyd
2023-01-11 20:00 ` Dmitry Baryshkov
2023-01-11 20:59 ` Konrad Dybcio
2023-01-11 21:52 ` Dmitry Baryshkov
2023-01-12 12:16 ` Konrad Dybcio
2023-01-11 19:19 ` [PATCH 05/13] clk: qcom: cpu-8996: skip ACD init if the setup is valid Dmitry Baryshkov
2023-01-11 21:00 ` Konrad Dybcio
2023-01-11 21:55 ` Dmitry Baryshkov
2023-01-12 12:17 ` Konrad Dybcio
2023-01-11 19:19 ` [PATCH 06/13] clk: qcom: cpu-8996: simplify the cpu_clk_notifier_cb Dmitry Baryshkov
2023-01-11 21:03 ` Konrad Dybcio
2023-01-11 22:01 ` Dmitry Baryshkov
2023-01-12 14:13 ` Konrad Dybcio
2023-01-11 19:19 ` [PATCH 07/13] clk: qcom: cpu-8996: setup PLLs before registering clocks Dmitry Baryshkov
2023-01-11 21:04 ` Konrad Dybcio
2023-01-11 19:19 ` [PATCH 08/13] clk: qcom: cpu-8996: move qcom_cpu_clk_msm8996_acd_init call Dmitry Baryshkov
2023-01-12 14:26 ` Konrad Dybcio
2023-01-11 19:20 ` [PATCH 09/13] clk: qcom: cpu-8996: fix PLL configuration sequence Dmitry Baryshkov
2023-01-11 21:08 ` Konrad Dybcio
2023-01-11 22:05 ` Dmitry Baryshkov
2023-01-12 14:32 ` Konrad Dybcio
2023-01-13 11:19 ` Dmitry Baryshkov
2023-01-13 13:43 ` Konrad Dybcio
2023-01-11 19:20 ` [PATCH 10/13] clk: qcom: cpu-8996: fix ACD initialization Dmitry Baryshkov
2023-01-12 14:35 ` Konrad Dybcio
2023-01-13 10:44 ` Dmitry Baryshkov
2023-01-13 14:00 ` Konrad Dybcio
2023-01-11 19:20 ` [PATCH 11/13] clk: qcom: cpu-8996: fix PLL clock ops Dmitry Baryshkov
2023-01-12 16:10 ` Konrad Dybcio
2023-01-13 11:35 ` Dmitry Baryshkov
2023-01-13 14:02 ` Konrad Dybcio
2023-01-11 19:20 ` [PATCH 12/13] clk: qcom: cpu-8996: change setup sequence to follow vendor kernel Dmitry Baryshkov
2023-01-12 14:42 ` Konrad Dybcio [this message]
2023-01-11 19:20 ` [PATCH 13/13] arm64: dts: qcom: msm8996: support using GPLL0 as kryocc input Dmitry Baryshkov
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