* [PATCH] mips: mt7628: fix ddr_type for MT7688KN
@ 2021-02-23 7:12 Weijie Gao
2021-02-26 11:23 ` Stefan Roese
2021-04-22 0:46 ` Daniel Schwierzeck
0 siblings, 2 replies; 4+ messages in thread
From: Weijie Gao @ 2021-02-23 7:12 UTC (permalink / raw)
To: u-boot
The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
from bootstrap register must be ignored, and always be assumed as DDR1.
This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
with a wrong ddr_type in MT7688KN.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
arch/mips/mach-mtmips/mt7628/ddr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c
index b091f2ecff..4e72459906 100644
--- a/arch/mips/mach-mtmips/mt7628/ddr.c
+++ b/arch/mips/mach-mtmips/mt7628/ddr.c
@@ -140,6 +140,9 @@ void mt7628_ddr_init(void)
lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
(CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
+ if (pkg_type == PKG_ID_KN)
+ ddr_type = DRAM_DDR1;
+
mt7628_memc_reset(1);
__udelay(200);
@@ -152,9 +155,6 @@ void mt7628_ddr_init(void)
param.memsize = 0;
param.bus_width = 0;
- if (pkg_type == PKG_ID_KN)
- ddr_type = DRAM_DDR1;
-
if (ddr_type == DRAM_DDR1) {
if (lspd)
param.cfgs = ddr1_cfgs_160mhz;
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] mips: mt7628: fix ddr_type for MT7688KN
2021-02-23 7:12 [PATCH] mips: mt7628: fix ddr_type for MT7688KN Weijie Gao
@ 2021-02-26 11:23 ` Stefan Roese
2021-03-05 3:30 ` Weijie Gao
2021-04-22 0:46 ` Daniel Schwierzeck
1 sibling, 1 reply; 4+ messages in thread
From: Stefan Roese @ 2021-02-26 11:23 UTC (permalink / raw)
To: u-boot
Hi Weijie,
On 23.02.21 08:12, Weijie Gao wrote:
> The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
> from bootstrap register must be ignored, and always be assumed as DDR1.
>
> This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
> with a wrong ddr_type in MT7688KN.
>
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
> arch/mips/mach-mtmips/mt7628/ddr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c
> index b091f2ecff..4e72459906 100644
> --- a/arch/mips/mach-mtmips/mt7628/ddr.c
> +++ b/arch/mips/mach-mtmips/mt7628/ddr.c
> @@ -140,6 +140,9 @@ void mt7628_ddr_init(void)
> lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
> (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
>
> + if (pkg_type == PKG_ID_KN)
> + ddr_type = DRAM_DDR1;
> +
> mt7628_memc_reset(1);
> __udelay(200);
>
> @@ -152,9 +155,6 @@ void mt7628_ddr_init(void)
> param.memsize = 0;
> param.bus_width = 0;
>
> - if (pkg_type == PKG_ID_KN)
> - ddr_type = DRAM_DDR1;
> -
> if (ddr_type == DRAM_DDR1) {
> if (lspd)
> param.cfgs = ddr1_cfgs_160mhz;
>
Reviewed-by: Stefan Roese <sr@denx.de>
Just out of interest. How did you spot this issue?
Thanks,
Stefan
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] mips: mt7628: fix ddr_type for MT7688KN
2021-02-26 11:23 ` Stefan Roese
@ 2021-03-05 3:30 ` Weijie Gao
0 siblings, 0 replies; 4+ messages in thread
From: Weijie Gao @ 2021-03-05 3:30 UTC (permalink / raw)
To: u-boot
On Fri, 2021-02-26 at 12:23 +0100, Stefan Roese wrote:
> Hi Weijie,
>
> On 23.02.21 08:12, Weijie Gao wrote:
> > The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR type
> > from bootstrap register must be ignored, and always be assumed as DDR1.
> >
> > This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be passed
> > with a wrong ddr_type in MT7688KN.
> >
> > Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> > ---
> > arch/mips/mach-mtmips/mt7628/ddr.c | 6 +++---
> > 1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/mips/mach-mtmips/mt7628/ddr.c b/arch/mips/mach-mtmips/mt7628/ddr.c
> > index b091f2ecff..4e72459906 100644
> > --- a/arch/mips/mach-mtmips/mt7628/ddr.c
> > +++ b/arch/mips/mach-mtmips/mt7628/ddr.c
> > @@ -140,6 +140,9 @@ void mt7628_ddr_init(void)
> > lspd = readl(sysc + SYSCTL_CLKCFG0_REG) &
> > (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL);
> >
> > + if (pkg_type == PKG_ID_KN)
> > + ddr_type = DRAM_DDR1;
> > +
> > mt7628_memc_reset(1);
> > __udelay(200);
> >
> > @@ -152,9 +155,6 @@ void mt7628_ddr_init(void)
> > param.memsize = 0;
> > param.bus_width = 0;
> >
> > - if (pkg_type == PKG_ID_KN)
> > - ddr_type = DRAM_DDR1;
> > -
> > if (ddr_type == DRAM_DDR1) {
> > if (lspd)
> > param.cfgs = ddr1_cfgs_160mhz;
> >
>
> Reviewed-by: Stefan Roese <sr@denx.de>
>
> Just out of interest. How did you spot this issue?
I was told by another developer.
>
> Thanks,
> Stefan
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] mips: mt7628: fix ddr_type for MT7688KN
2021-02-23 7:12 [PATCH] mips: mt7628: fix ddr_type for MT7688KN Weijie Gao
2021-02-26 11:23 ` Stefan Roese
@ 2021-04-22 0:46 ` Daniel Schwierzeck
1 sibling, 0 replies; 4+ messages in thread
From: Daniel Schwierzeck @ 2021-04-22 0:46 UTC (permalink / raw)
To: u-boot
Am Dienstag, den 23.02.2021, 15:12 +0800 schrieb Weijie Gao:
> The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR
> type
> from bootstrap register must be ignored, and always be assumed as
> DDR1.
>
> This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be
> passed
> with a wrong ddr_type in MT7688KN.
>
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
> arch/mips/mach-mtmips/mt7628/ddr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
applied to u-boot-mips, thanks.
--
- Daniel
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-04-22 0:46 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-02-23 7:12 [PATCH] mips: mt7628: fix ddr_type for MT7688KN Weijie Gao
2021-02-26 11:23 ` Stefan Roese
2021-03-05 3:30 ` Weijie Gao
2021-04-22 0:46 ` Daniel Schwierzeck
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