* [PATCH v1 0/3] target/microblaze: Plug tcg temp leaks
@ 2019-11-06 14:14 Edgar E. Iglesias
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
` (2 more replies)
0 siblings, 3 replies; 17+ messages in thread
From: Edgar E. Iglesias @ 2019-11-06 14:14 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
On some workloads we've seen TCG run out of temps due to leakage
in the MicroBlaze translator. This series fixes the leaks.
Cheers,
Edgar
Edgar E. Iglesias (3):
target/microblaze: Plug temp leaks for loads/stores
target/microblaze: Plug temp leaks with delay slot setup
target/microblaze: Plug temp leak around eval_cond_jmp()
target/microblaze/translate.c | 61 ++++++++++++++++++++++++-----------
1 file changed, 42 insertions(+), 19 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores
2019-11-06 14:14 [PATCH v1 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
@ 2019-11-06 14:14 ` Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
` (3 more replies)
2019-11-06 14:14 ` [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
2019-11-06 14:14 ` [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
2 siblings, 4 replies; 17+ messages in thread
From: Edgar E. Iglesias @ 2019-11-06 14:14 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Plug TCG temp leaks for loads/stores.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 30 ++++++++++++++++++++++++------
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 761f535357..ba143ede5f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc)
10 -> 10
11 -> 00 */
TCGv low = tcg_temp_new();
+ TCGv t3 = tcg_const_tl(3);
tcg_gen_andi_tl(low, addr, 3);
- tcg_gen_sub_tl(low, tcg_const_tl(3), low);
+ tcg_gen_sub_tl(low, t3, low);
tcg_gen_andi_tl(addr, addr, ~3);
tcg_gen_or_tl(addr, addr, low);
tcg_temp_free(low);
+ tcg_temp_free(t3);
break;
}
@@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc)
tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ TCGv_i32 t0 = tcg_const_i32(0);
+ TCGv_i32 treg = tcg_const_i32(dc->rd);
+ TCGv_i32 tsize = tcg_const_i32(size - 1);
+
tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
- gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
- tcg_const_i32(0), tcg_const_i32(size - 1));
+ gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
+
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(treg);
+ tcg_temp_free_i32(tsize);
}
if (ex) {
@@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc)
10 -> 10
11 -> 00 */
TCGv low = tcg_temp_new();
+ TCGv t3 = tcg_const_tl(3);
tcg_gen_andi_tl(low, addr, 3);
- tcg_gen_sub_tl(low, tcg_const_tl(3), low);
+ tcg_gen_sub_tl(low, t3, low);
tcg_gen_andi_tl(addr, addr, ~3);
tcg_gen_or_tl(addr, addr, low);
tcg_temp_free(low);
+ tcg_temp_free(t3);
break;
}
@@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc)
/* Verify alignment if needed. */
if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ TCGv_i32 t1 = tcg_const_i32(1);
+ TCGv_i32 treg = tcg_const_i32(dc->rd);
+ TCGv_i32 tsize = tcg_const_i32(size - 1);
+
tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
/* FIXME: if the alignment is wrong, we should restore the value
* in memory. One possible way to achieve this is to probe
@@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc)
* the alignment checks in between the probe and the mem
* access.
*/
- gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
- tcg_const_i32(1), tcg_const_i32(size - 1));
+ gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(treg);
+ tcg_temp_free_i32(tsize);
}
if (ex) {
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup
2019-11-06 14:14 [PATCH v1 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
@ 2019-11-06 14:14 ` Edgar E. Iglesias
2019-11-06 14:33 ` Philippe Mathieu-Daudé
` (3 more replies)
2019-11-06 14:14 ` [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
2 siblings, 4 replies; 17+ messages in thread
From: Edgar E. Iglesias @ 2019-11-06 14:14 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Plug temp leaks with delay slot setup.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index ba143ede5f..e9ff9e650d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1201,6 +1201,17 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false)
tcg_temp_free_i64(tmp_zero);
}
+static void dec_setup_dslot(DisasContext *dc)
+{
+ TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG));
+
+ dc->delayed_branch = 2;
+ dc->tb_flags |= D_FLAG;
+
+ tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm));
+ tcg_temp_free_i32(tmp);
+}
+
static void dec_bcc(DisasContext *dc)
{
unsigned int cc;
@@ -1212,10 +1223,7 @@ static void dec_bcc(DisasContext *dc)
dc->delayed_branch = 1;
if (dslot) {
- dc->delayed_branch = 2;
- dc->tb_flags |= D_FLAG;
- tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
- cpu_env, offsetof(CPUMBState, bimm));
+ dec_setup_dslot(dc);
}
if (dec_alu_op_b_is_small_imm(dc)) {
@@ -1274,10 +1282,7 @@ static void dec_br(DisasContext *dc)
dc->delayed_branch = 1;
if (dslot) {
- dc->delayed_branch = 2;
- dc->tb_flags |= D_FLAG;
- tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
- cpu_env, offsetof(CPUMBState, bimm));
+ dec_setup_dslot(dc);
}
if (link && dc->rd)
tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
@@ -1379,10 +1384,7 @@ static void dec_rts(DisasContext *dc)
return;
}
- dc->delayed_branch = 2;
- dc->tb_flags |= D_FLAG;
- tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
- cpu_env, offsetof(CPUMBState, bimm));
+ dec_setup_dslot(dc);
if (i_bit) {
LOG_DIS("rtid ir=%x\n", dc->ir);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp()
2019-11-06 14:14 [PATCH v1 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
2019-11-06 14:14 ` [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
@ 2019-11-06 14:14 ` Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
` (3 more replies)
2 siblings, 4 replies; 17+ messages in thread
From: Edgar E. Iglesias @ 2019-11-06 14:14 UTC (permalink / raw)
To: qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd, luc.michel
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Plug temp leak around eval_cond_jmp().
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index e9ff9e650d..93e22a89ac 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1705,7 +1705,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
dc->tb_flags &= ~D_FLAG;
/* If it is a direct jump, try direct chaining. */
if (dc->jmp == JMP_INDIRECT) {
- eval_cond_jmp(dc, env_btarget, tcg_const_i64(dc->pc));
+ TCGv_i64 tmp_pc = tcg_const_i64(dc->pc);
+ eval_cond_jmp(dc, env_btarget, tmp_pc);
+ tcg_temp_free_i64(tmp_pc);
+
dc->is_jmp = DISAS_JUMP;
} else if (dc->jmp == JMP_DIRECT) {
t_sync_flags(dc);
--
2.20.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
@ 2019-11-06 14:32 ` Philippe Mathieu-Daudé
2019-11-06 14:37 ` Luc Michel
` (2 subsequent siblings)
3 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-11-06 14:32 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, luc.michel
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug TCG temp leaks for loads/stores.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 30 ++++++++++++++++++++++++------
> 1 file changed, 24 insertions(+), 6 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 761f535357..ba143ede5f 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc)
> 10 -> 10
> 11 -> 00 */
> TCGv low = tcg_temp_new();
> + TCGv t3 = tcg_const_tl(3);
>
> tcg_gen_andi_tl(low, addr, 3);
> - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> + tcg_gen_sub_tl(low, t3, low);
> tcg_gen_andi_tl(addr, addr, ~3);
> tcg_gen_or_tl(addr, addr, low);
> tcg_temp_free(low);
> + tcg_temp_free(t3);
> break;
> }
>
> @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc)
> tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>
> if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + TCGv_i32 t0 = tcg_const_i32(0);
> + TCGv_i32 treg = tcg_const_i32(dc->rd);
> + TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
> tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> - tcg_const_i32(0), tcg_const_i32(size - 1));
> + gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
> +
> + tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(treg);
> + tcg_temp_free_i32(tsize);
> }
>
> if (ex) {
> @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc)
> 10 -> 10
> 11 -> 00 */
> TCGv low = tcg_temp_new();
> + TCGv t3 = tcg_const_tl(3);
>
> tcg_gen_andi_tl(low, addr, 3);
> - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> + tcg_gen_sub_tl(low, t3, low);
> tcg_gen_andi_tl(addr, addr, ~3);
> tcg_gen_or_tl(addr, addr, low);
> tcg_temp_free(low);
> + tcg_temp_free(t3);
> break;
> }
>
> @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc)
>
> /* Verify alignment if needed. */
> if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + TCGv_i32 t1 = tcg_const_i32(1);
> + TCGv_i32 treg = tcg_const_i32(dc->rd);
> + TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
> tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> /* FIXME: if the alignment is wrong, we should restore the value
> * in memory. One possible way to achieve this is to probe
> @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc)
> * the alignment checks in between the probe and the mem
> * access.
> */
> - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> - tcg_const_i32(1), tcg_const_i32(size - 1));
> + gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(treg);
> + tcg_temp_free_i32(tsize);
> }
>
> if (ex) {
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp()
2019-11-06 14:14 ` [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
@ 2019-11-06 14:32 ` Philippe Mathieu-Daudé
2019-11-06 14:42 ` Luc Michel
` (2 subsequent siblings)
3 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-11-06 14:32 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, luc.michel
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leak around eval_cond_jmp().
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index e9ff9e650d..93e22a89ac 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1705,7 +1705,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
> dc->tb_flags &= ~D_FLAG;
> /* If it is a direct jump, try direct chaining. */
> if (dc->jmp == JMP_INDIRECT) {
> - eval_cond_jmp(dc, env_btarget, tcg_const_i64(dc->pc));
> + TCGv_i64 tmp_pc = tcg_const_i64(dc->pc);
> + eval_cond_jmp(dc, env_btarget, tmp_pc);
> + tcg_temp_free_i64(tmp_pc);
> +
> dc->is_jmp = DISAS_JUMP;
> } else if (dc->jmp == JMP_DIRECT) {
> t_sync_flags(dc);
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup
2019-11-06 14:14 ` [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
@ 2019-11-06 14:33 ` Philippe Mathieu-Daudé
2019-11-06 14:41 ` Luc Michel
` (2 subsequent siblings)
3 siblings, 0 replies; 17+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-11-06 14:33 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, luc.michel
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leaks with delay slot setup.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index ba143ede5f..e9ff9e650d 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1201,6 +1201,17 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false)
> tcg_temp_free_i64(tmp_zero);
> }
>
> +static void dec_setup_dslot(DisasContext *dc)
> +{
> + TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG));
> +
> + dc->delayed_branch = 2;
> + dc->tb_flags |= D_FLAG;
> +
> + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm));
> + tcg_temp_free_i32(tmp);
> +}
> +
> static void dec_bcc(DisasContext *dc)
> {
> unsigned int cc;
> @@ -1212,10 +1223,7 @@ static void dec_bcc(DisasContext *dc)
>
> dc->delayed_branch = 1;
> if (dslot) {
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
> }
>
> if (dec_alu_op_b_is_small_imm(dc)) {
> @@ -1274,10 +1282,7 @@ static void dec_br(DisasContext *dc)
>
> dc->delayed_branch = 1;
> if (dslot) {
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
> }
> if (link && dc->rd)
> tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
> @@ -1379,10 +1384,7 @@ static void dec_rts(DisasContext *dc)
> return;
> }
>
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
>
> if (i_bit) {
> LOG_DIS("rtid ir=%x\n", dc->ir);
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
@ 2019-11-06 14:37 ` Luc Michel
2019-11-06 21:55 ` Alistair Francis
2019-11-07 14:19 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Luc Michel @ 2019-11-06 14:37 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug TCG temp leaks for loads/stores.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 30 ++++++++++++++++++++++++------
> 1 file changed, 24 insertions(+), 6 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 761f535357..ba143ede5f 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc)
> 10 -> 10
> 11 -> 00 */
> TCGv low = tcg_temp_new();
> + TCGv t3 = tcg_const_tl(3);
>
> tcg_gen_andi_tl(low, addr, 3);
> - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> + tcg_gen_sub_tl(low, t3, low);
For this one, I think you can use tcg_gen_subfi_tl(low, 3, low)
> tcg_gen_andi_tl(addr, addr, ~3);
> tcg_gen_or_tl(addr, addr, low);
> tcg_temp_free(low);
> + tcg_temp_free(t3);
> break;
> }
>
> @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc)
> tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>
> if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + TCGv_i32 t0 = tcg_const_i32(0);
> + TCGv_i32 treg = tcg_const_i32(dc->rd);
> + TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
> tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> - tcg_const_i32(0), tcg_const_i32(size - 1));
> + gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
> +
> + tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(treg);
> + tcg_temp_free_i32(tsize);
> }
>
> if (ex) {
> @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc)
> 10 -> 10
> 11 -> 00 */
> TCGv low = tcg_temp_new();
> + TCGv t3 = tcg_const_tl(3);
>
> tcg_gen_andi_tl(low, addr, 3);
> - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> + tcg_gen_sub_tl(low, t3, low);
Same here.
With or without those modifications:
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
> tcg_gen_andi_tl(addr, addr, ~3);
> tcg_gen_or_tl(addr, addr, low);
> tcg_temp_free(low);
> + tcg_temp_free(t3);
> break;
> }
>
> @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc)
>
> /* Verify alignment if needed. */
> if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + TCGv_i32 t1 = tcg_const_i32(1);
> + TCGv_i32 treg = tcg_const_i32(dc->rd);
> + TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
> tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> /* FIXME: if the alignment is wrong, we should restore the value
> * in memory. One possible way to achieve this is to probe
> @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc)
> * the alignment checks in between the probe and the mem
> * access.
> */
> - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> - tcg_const_i32(1), tcg_const_i32(size - 1));
> + gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(treg);
> + tcg_temp_free_i32(tsize);
> }
>
> if (ex) {
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup
2019-11-06 14:14 ` [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
2019-11-06 14:33 ` Philippe Mathieu-Daudé
@ 2019-11-06 14:41 ` Luc Michel
2019-11-06 21:56 ` Alistair Francis
2019-11-07 14:21 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Luc Michel @ 2019-11-06 14:41 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leaks with delay slot setup.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index ba143ede5f..e9ff9e650d 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1201,6 +1201,17 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false)
> tcg_temp_free_i64(tmp_zero);
> }
>
> +static void dec_setup_dslot(DisasContext *dc)
> +{
> + TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG));
> +
> + dc->delayed_branch = 2;
> + dc->tb_flags |= D_FLAG;
> +
> + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm));
> + tcg_temp_free_i32(tmp);
> +}
> +
> static void dec_bcc(DisasContext *dc)
> {
> unsigned int cc;
> @@ -1212,10 +1223,7 @@ static void dec_bcc(DisasContext *dc)
>
> dc->delayed_branch = 1;
> if (dslot) {
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
> }
>
> if (dec_alu_op_b_is_small_imm(dc)) {
> @@ -1274,10 +1282,7 @@ static void dec_br(DisasContext *dc)
>
> dc->delayed_branch = 1;
> if (dslot) {
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
> }
> if (link && dc->rd)
> tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
> @@ -1379,10 +1384,7 @@ static void dec_rts(DisasContext *dc)
> return;
> }
>
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
>
> if (i_bit) {
> LOG_DIS("rtid ir=%x\n", dc->ir);
>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp()
2019-11-06 14:14 ` [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
@ 2019-11-06 14:42 ` Luc Michel
2019-11-06 21:57 ` Alistair Francis
2019-11-07 14:22 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Luc Michel @ 2019-11-06 14:42 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
frederic.konrad, philmd
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leak around eval_cond_jmp().
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index e9ff9e650d..93e22a89ac 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1705,7 +1705,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
> dc->tb_flags &= ~D_FLAG;
> /* If it is a direct jump, try direct chaining. */
> if (dc->jmp == JMP_INDIRECT) {
> - eval_cond_jmp(dc, env_btarget, tcg_const_i64(dc->pc));
> + TCGv_i64 tmp_pc = tcg_const_i64(dc->pc);
> + eval_cond_jmp(dc, env_btarget, tmp_pc);
> + tcg_temp_free_i64(tmp_pc);
> +
> dc->is_jmp = DISAS_JUMP;
> } else if (dc->jmp == JMP_DIRECT) {
> t_sync_flags(dc);
>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
2019-11-06 14:37 ` Luc Michel
@ 2019-11-06 21:55 ` Alistair Francis
2019-11-07 14:19 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-11-06 21:55 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Wed, Nov 6, 2019 at 6:14 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug TCG temp leaks for loads/stores.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/translate.c | 30 ++++++++++++++++++++++++------
> 1 file changed, 24 insertions(+), 6 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 761f535357..ba143ede5f 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc)
> 10 -> 10
> 11 -> 00 */
> TCGv low = tcg_temp_new();
> + TCGv t3 = tcg_const_tl(3);
>
> tcg_gen_andi_tl(low, addr, 3);
> - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> + tcg_gen_sub_tl(low, t3, low);
> tcg_gen_andi_tl(addr, addr, ~3);
> tcg_gen_or_tl(addr, addr, low);
> tcg_temp_free(low);
> + tcg_temp_free(t3);
> break;
> }
>
> @@ -1006,9 +1008,16 @@ static void dec_load(DisasContext *dc)
> tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>
> if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + TCGv_i32 t0 = tcg_const_i32(0);
> + TCGv_i32 treg = tcg_const_i32(dc->rd);
> + TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
> tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> - tcg_const_i32(0), tcg_const_i32(size - 1));
> + gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
> +
> + tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(treg);
> + tcg_temp_free_i32(tsize);
> }
>
> if (ex) {
> @@ -1100,12 +1109,14 @@ static void dec_store(DisasContext *dc)
> 10 -> 10
> 11 -> 00 */
> TCGv low = tcg_temp_new();
> + TCGv t3 = tcg_const_tl(3);
>
> tcg_gen_andi_tl(low, addr, 3);
> - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> + tcg_gen_sub_tl(low, t3, low);
> tcg_gen_andi_tl(addr, addr, ~3);
> tcg_gen_or_tl(addr, addr, low);
> tcg_temp_free(low);
> + tcg_temp_free(t3);
> break;
> }
>
> @@ -1124,6 +1135,10 @@ static void dec_store(DisasContext *dc)
>
> /* Verify alignment if needed. */
> if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> + TCGv_i32 t1 = tcg_const_i32(1);
> + TCGv_i32 treg = tcg_const_i32(dc->rd);
> + TCGv_i32 tsize = tcg_const_i32(size - 1);
> +
> tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
> /* FIXME: if the alignment is wrong, we should restore the value
> * in memory. One possible way to achieve this is to probe
> @@ -1131,8 +1146,11 @@ static void dec_store(DisasContext *dc)
> * the alignment checks in between the probe and the mem
> * access.
> */
> - gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
> - tcg_const_i32(1), tcg_const_i32(size - 1));
> + gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(treg);
> + tcg_temp_free_i32(tsize);
> }
>
> if (ex) {
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup
2019-11-06 14:14 ` [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
2019-11-06 14:33 ` Philippe Mathieu-Daudé
2019-11-06 14:41 ` Luc Michel
@ 2019-11-06 21:56 ` Alistair Francis
2019-11-07 14:21 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-11-06 21:56 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Wed, Nov 6, 2019 at 6:17 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leaks with delay slot setup.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/translate.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index ba143ede5f..e9ff9e650d 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1201,6 +1201,17 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false)
> tcg_temp_free_i64(tmp_zero);
> }
>
> +static void dec_setup_dslot(DisasContext *dc)
> +{
> + TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG));
> +
> + dc->delayed_branch = 2;
> + dc->tb_flags |= D_FLAG;
> +
> + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm));
> + tcg_temp_free_i32(tmp);
> +}
> +
> static void dec_bcc(DisasContext *dc)
> {
> unsigned int cc;
> @@ -1212,10 +1223,7 @@ static void dec_bcc(DisasContext *dc)
>
> dc->delayed_branch = 1;
> if (dslot) {
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
> }
>
> if (dec_alu_op_b_is_small_imm(dc)) {
> @@ -1274,10 +1282,7 @@ static void dec_br(DisasContext *dc)
>
> dc->delayed_branch = 1;
> if (dslot) {
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
> }
> if (link && dc->rd)
> tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
> @@ -1379,10 +1384,7 @@ static void dec_rts(DisasContext *dc)
> return;
> }
>
> - dc->delayed_branch = 2;
> - dc->tb_flags |= D_FLAG;
> - tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)),
> - cpu_env, offsetof(CPUMBState, bimm));
> + dec_setup_dslot(dc);
>
> if (i_bit) {
> LOG_DIS("rtid ir=%x\n", dc->ir);
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp()
2019-11-06 14:14 ` [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
2019-11-06 14:42 ` Luc Michel
@ 2019-11-06 21:57 ` Alistair Francis
2019-11-07 14:22 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Alistair Francis @ 2019-11-06 21:57 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: figlesia, Peter Maydell, Edgar Iglesias, Sai Pavan Boddu,
Francisco Iglesias, Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, KONRAD Frederic,
Stefano Stabellini, Philippe Mathieu-Daudé,
Luc Michel
On Wed, Nov 6, 2019 at 6:17 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leak around eval_cond_jmp().
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/microblaze/translate.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index e9ff9e650d..93e22a89ac 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -1705,7 +1705,10 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
> dc->tb_flags &= ~D_FLAG;
> /* If it is a direct jump, try direct chaining. */
> if (dc->jmp == JMP_INDIRECT) {
> - eval_cond_jmp(dc, env_btarget, tcg_const_i64(dc->pc));
> + TCGv_i64 tmp_pc = tcg_const_i64(dc->pc);
> + eval_cond_jmp(dc, env_btarget, tmp_pc);
> + tcg_temp_free_i64(tmp_pc);
> +
> dc->is_jmp = DISAS_JUMP;
> } else if (dc->jmp == JMP_DIRECT) {
> t_sync_flags(dc);
> --
> 2.20.1
>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
` (2 preceding siblings ...)
2019-11-06 21:55 ` Alistair Francis
@ 2019-11-07 14:19 ` Richard Henderson
2019-11-08 12:36 ` Edgar E. Iglesias
3 siblings, 1 reply; 17+ messages in thread
From: Richard Henderson @ 2019-11-07 14:19 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, frederic.konrad,
philmd, luc.michel
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc)
> 10 -> 10
> 11 -> 00 */
> TCGv low = tcg_temp_new();
> + TCGv t3 = tcg_const_tl(3);
>
> tcg_gen_andi_tl(low, addr, 3);
> - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> + tcg_gen_sub_tl(low, t3, low);
> tcg_gen_andi_tl(addr, addr, ~3);
> tcg_gen_or_tl(addr, addr, low);
> tcg_temp_free(low);
> + tcg_temp_free(t3);
> break;
While Luc correctly notes that tcg_gen_subfi_tl() may be used here, I will note
(1) there's a typo in the comment (not 2->2, but 2->1), and (2) that this whole
section can be done with
tcg_gen_xori_tl(addr, addr, 3);
Similarly in dec_store.
The other changes in this patch around gen_helper_memalign are ok.
r~
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup
2019-11-06 14:14 ` [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
` (2 preceding siblings ...)
2019-11-06 21:56 ` Alistair Francis
@ 2019-11-07 14:21 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2019-11-07 14:21 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, frederic.konrad,
philmd, luc.michel
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leaks with delay slot setup.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 26 ++++++++++++++------------
> 1 file changed, 14 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp()
2019-11-06 14:14 ` [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
` (2 preceding siblings ...)
2019-11-06 21:57 ` Alistair Francis
@ 2019-11-07 14:22 ` Richard Henderson
3 siblings, 0 replies; 17+ messages in thread
From: Richard Henderson @ 2019-11-07 14:22 UTC (permalink / raw)
To: Edgar E. Iglesias, qemu-devel
Cc: figlesia, peter.maydell, sstabellini, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, frederic.konrad,
philmd, luc.michel
On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Plug temp leak around eval_cond_jmp().
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/microblaze/translate.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores
2019-11-07 14:19 ` Richard Henderson
@ 2019-11-08 12:36 ` Edgar E. Iglesias
0 siblings, 0 replies; 17+ messages in thread
From: Edgar E. Iglesias @ 2019-11-08 12:36 UTC (permalink / raw)
To: Richard Henderson
Cc: figlesia, peter.maydell, sstabellini, sai.pavan.boddu,
frasse.iglesias, alistair, qemu-devel, frederic.konrad,
Edgar E. Iglesias, philmd, luc.michel
On Thu, Nov 07, 2019 at 03:19:20PM +0100, Richard Henderson wrote:
> On 11/6/19 3:14 PM, Edgar E. Iglesias wrote:
> > @@ -967,12 +967,14 @@ static void dec_load(DisasContext *dc)
> > 10 -> 10
> > 11 -> 00 */
> > TCGv low = tcg_temp_new();
> > + TCGv t3 = tcg_const_tl(3);
> >
> > tcg_gen_andi_tl(low, addr, 3);
> > - tcg_gen_sub_tl(low, tcg_const_tl(3), low);
> > + tcg_gen_sub_tl(low, t3, low);
> > tcg_gen_andi_tl(addr, addr, ~3);
> > tcg_gen_or_tl(addr, addr, low);
> > tcg_temp_free(low);
> > + tcg_temp_free(t3);
> > break;
>
> While Luc correctly notes that tcg_gen_subfi_tl() may be used here, I will note
> (1) there's a typo in the comment (not 2->2, but 2->1), and (2) that this whole
> section can be done with
>
> tcg_gen_xori_tl(addr, addr, 3);
Nice!
I'll send out a new version shortly.
Best regards,
Edgar
>
> Similarly in dec_store.
>
> The other changes in this patch around gen_helper_memalign are ok.
>
>
> r~
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2019-11-08 12:39 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-06 14:14 [PATCH v1 0/3] target/microblaze: Plug tcg temp leaks Edgar E. Iglesias
2019-11-06 14:14 ` [PATCH v1 1/3] target/microblaze: Plug temp leaks for loads/stores Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
2019-11-06 14:37 ` Luc Michel
2019-11-06 21:55 ` Alistair Francis
2019-11-07 14:19 ` Richard Henderson
2019-11-08 12:36 ` Edgar E. Iglesias
2019-11-06 14:14 ` [PATCH v1 2/3] target/microblaze: Plug temp leaks with delay slot setup Edgar E. Iglesias
2019-11-06 14:33 ` Philippe Mathieu-Daudé
2019-11-06 14:41 ` Luc Michel
2019-11-06 21:56 ` Alistair Francis
2019-11-07 14:21 ` Richard Henderson
2019-11-06 14:14 ` [PATCH v1 3/3] target/microblaze: Plug temp leak around eval_cond_jmp() Edgar E. Iglesias
2019-11-06 14:32 ` Philippe Mathieu-Daudé
2019-11-06 14:42 ` Luc Michel
2019-11-06 21:57 ` Alistair Francis
2019-11-07 14:22 ` Richard Henderson
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