From: Conor Dooley <conor@kernel.org> To: Stephen Boyd <sboyd@kernel.org> Cc: Jesse Taube <mr.bossman075@gmail.com>, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Yimin Gu <ustcymgu@gmail.com>, Damien Le Moal <damien.lemoal@wdc.com>, Michael Turquette <mturquette@baylibre.com>, Waldemar Brodkorb <wbx@openadk.org>, Albert Ou <aou@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Conor Dooley <conor.dooley@microchip.com>, kernel test robot <lkp@intel.com> Subject: Re: [PATCH v3 1/3] clk: k210: remove an implicit 64-bit division Date: Mon, 6 Mar 2023 22:35:01 +0000 [thread overview] Message-ID: <be589843-dfc1-47dc-a488-a4fad645c638@spud> (raw) In-Reply-To: <3b0a1481873a2a7c26015fcedcc673b3.sboyd@kernel.org> [-- Attachment #1: Type: text/plain, Size: 914 bytes --] On Mon, Mar 06, 2023 at 02:31:00PM -0800, Stephen Boyd wrote: > Quoting Jesse Taube (2023-02-28 16:26:55) > > diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c > > index 67a7cb3503c3..4eed667eddaf 100644 > > --- a/drivers/clk/clk-k210.c > > +++ b/drivers/clk/clk-k210.c > > @@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw, > > f = FIELD_GET(K210_PLL_CLKF, reg) + 1; > > od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; > > > > - return (u64)parent_rate * f / (r * od); > > + return div_u64((u64)parent_rate * f, r * od); > > The equation 'r * od' can't overflow 32-bits, right? Yah, I checked that when writing the patch. They're 4-bit fields: > /* > * PLL control register bits. > */ > #define K210_PLL_CLKR GENMASK(3, 0) > #define K210_PLL_CLKF GENMASK(9, 4) > #define K210_PLL_CLKOD GENMASK(13, 10) Cheers, Conor. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org> To: Stephen Boyd <sboyd@kernel.org> Cc: Jesse Taube <mr.bossman075@gmail.com>, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Yimin Gu <ustcymgu@gmail.com>, Damien Le Moal <damien.lemoal@wdc.com>, Michael Turquette <mturquette@baylibre.com>, Waldemar Brodkorb <wbx@openadk.org>, Albert Ou <aou@eecs.berkeley.edu>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Conor Dooley <conor.dooley@microchip.com>, kernel test robot <lkp@intel.com> Subject: Re: [PATCH v3 1/3] clk: k210: remove an implicit 64-bit division Date: Mon, 6 Mar 2023 22:35:01 +0000 [thread overview] Message-ID: <be589843-dfc1-47dc-a488-a4fad645c638@spud> (raw) In-Reply-To: <3b0a1481873a2a7c26015fcedcc673b3.sboyd@kernel.org> [-- Attachment #1.1: Type: text/plain, Size: 914 bytes --] On Mon, Mar 06, 2023 at 02:31:00PM -0800, Stephen Boyd wrote: > Quoting Jesse Taube (2023-02-28 16:26:55) > > diff --git a/drivers/clk/clk-k210.c b/drivers/clk/clk-k210.c > > index 67a7cb3503c3..4eed667eddaf 100644 > > --- a/drivers/clk/clk-k210.c > > +++ b/drivers/clk/clk-k210.c > > @@ -495,7 +495,7 @@ static unsigned long k210_pll_get_rate(struct clk_hw *hw, > > f = FIELD_GET(K210_PLL_CLKF, reg) + 1; > > od = FIELD_GET(K210_PLL_CLKOD, reg) + 1; > > > > - return (u64)parent_rate * f / (r * od); > > + return div_u64((u64)parent_rate * f, r * od); > > The equation 'r * od' can't overflow 32-bits, right? Yah, I checked that when writing the patch. They're 4-bit fields: > /* > * PLL control register bits. > */ > #define K210_PLL_CLKR GENMASK(3, 0) > #define K210_PLL_CLKF GENMASK(9, 4) > #define K210_PLL_CLKOD GENMASK(13, 10) Cheers, Conor. [-- Attachment #1.2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] [-- Attachment #2: Type: text/plain, Size: 161 bytes --] _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-03-06 22:35 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-03-01 0:26 [PATCH v3 0/3] Add RISC-V 32 NOMMU support Jesse Taube 2023-03-01 0:26 ` Jesse Taube 2023-03-01 0:26 ` [PATCH v3 1/3] clk: k210: remove an implicit 64-bit division Jesse Taube 2023-03-01 0:26 ` Jesse Taube 2023-03-01 1:19 ` Damien Le Moal 2023-03-01 1:19 ` Damien Le Moal 2023-03-06 22:31 ` Stephen Boyd 2023-03-06 22:31 ` Stephen Boyd 2023-03-06 22:35 ` Conor Dooley [this message] 2023-03-06 22:35 ` Conor Dooley 2023-03-06 22:37 ` Stephen Boyd 2023-03-06 22:37 ` Stephen Boyd 2023-03-06 22:41 ` Stephen Boyd 2023-03-06 22:41 ` Stephen Boyd 2023-03-06 22:48 ` Palmer Dabbelt 2023-03-06 22:48 ` Palmer Dabbelt 2023-03-01 0:26 ` [PATCH v3 2/3] riscv: Kconfig: Allow RV32 to build with no MMU Jesse Taube 2023-03-01 0:26 ` Jesse Taube 2023-03-01 1:22 ` Damien Le Moal 2023-03-01 1:22 ` Damien Le Moal 2023-03-01 0:26 ` [PATCH v3 3/3] riscv: configs: Add nommu PHONY defconfig for RV32 Jesse Taube 2023-03-01 0:26 ` Jesse Taube 2023-03-01 4:07 ` [PATCH v3 0/3] Add RISC-V 32 NOMMU support Randy Dunlap 2023-03-01 4:07 ` Randy Dunlap 2023-03-01 4:42 ` Damien Le Moal 2023-03-01 4:42 ` Damien Le Moal 2023-03-08 1:26 ` Jesse Taube 2023-03-08 1:26 ` Jesse Taube 2023-03-08 2:16 ` Randy Dunlap 2023-03-08 2:16 ` Randy Dunlap 2023-03-08 2:30 ` Jesse Taube 2023-03-08 2:30 ` Jesse Taube 2023-03-08 2:33 ` Randy Dunlap 2023-03-08 2:33 ` Randy Dunlap 2023-03-08 2:51 ` Randy Dunlap 2023-03-08 2:51 ` Randy Dunlap 2023-03-08 2:54 ` Jesse Taube 2023-03-08 2:54 ` Jesse Taube 2023-03-08 3:23 ` Randy Dunlap 2023-03-08 3:23 ` Randy Dunlap 2023-03-08 3:42 ` Damien Le Moal 2023-03-08 3:42 ` Damien Le Moal 2023-03-08 3:46 ` Jesse Taube 2023-03-08 3:46 ` Jesse Taube 2023-03-08 4:11 ` Damien Le Moal 2023-03-08 4:11 ` Damien Le Moal 2023-03-14 18:35 ` Jesse Taube 2023-03-14 18:35 ` Jesse Taube 2023-03-14 19:16 ` Conor Dooley 2023-03-14 19:16 ` Conor Dooley 2023-03-08 3:51 ` Randy Dunlap 2023-03-08 3:51 ` Randy Dunlap 2023-03-25 11:57 ` Conor Dooley 2023-03-25 11:57 ` Conor Dooley 2023-03-28 18:50 ` (subset) " Palmer Dabbelt 2023-03-28 18:50 ` Palmer Dabbelt
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