* [PATCH v4 0/4] RISC-V: Remove deprecated ISA, CPUs and machines
@ 2020-05-28 22:16 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23, bmeng.cn
v4:
- Remove all of the < PRIV_VERSION_1_10_0 checks
- Move the documentation to the "Recently removed features" section
- Document the OpenSBI deprecation
v3:
- Don't use SiFive CPUs for Spike machine
v2:
- Remove the CPUs and ISA seperatley
Alistair Francis (4):
hw/riscv: spike: Remove deprecated ISA specific machines
target/riscv: Remove the deprecated CPUs
target/riscv: Drop support for ISA spec version 1.09.1
docs: deprecated: Update the -bios documentation
docs/system/deprecated.rst | 98 ++++----
include/hw/riscv/spike.h | 6 +-
target/riscv/cpu.h | 8 -
hw/riscv/spike.c | 217 ------------------
target/riscv/cpu.c | 30 ---
target/riscv/cpu_helper.c | 82 +++----
target/riscv/csr.c | 138 ++---------
.../riscv/insn_trans/trans_privileged.inc.c | 18 +-
target/riscv/monitor.c | 5 -
target/riscv/op_helper.c | 17 +-
tests/qtest/machine-none-test.c | 4 +-
11 files changed, 118 insertions(+), 505 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 1/4] hw/riscv: spike: Remove deprecated ISA specific machines
2020-05-28 22:16 ` Alistair Francis
@ 2020-05-28 22:16 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
The ISA specific Spike machines have been deprecated in QEMU since 4.1,
let's finally remove them.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
docs/system/deprecated.rst | 17 +--
include/hw/riscv/spike.h | 6 +-
hw/riscv/spike.c | 217 -------------------------------------
3 files changed, 12 insertions(+), 228 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index f0061f94aa..50927bad74 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -379,13 +379,6 @@ This machine has been renamed ``fuloong2e``.
These machine types are very old and likely can not be used for live migration
from old QEMU versions anymore. A newer machine type should be used instead.
-``spike_v1.9.1`` and ``spike_v1.10`` (since 4.1)
-''''''''''''''''''''''''''''''''''''''''''''''''
-
-The version specific Spike machines have been deprecated in favour of the
-generic ``spike`` machine. If you need to specify an older version of the RISC-V
-spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument.
-
Device options
--------------
@@ -493,6 +486,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
+System emulator machines
+------------------------
+
+``spike_v1.9.1`` and ``spike_v1.10`` (removed in 5.1)
+'''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The version specific Spike machines have been removed in favour of the
+generic ``spike`` machine. If you need to specify an older version of the RISC-V
+spec you can use the ``-cpu rv64gcsu,priv_spec=v1.10.0`` command line argument.
+
Related binaries
----------------
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index dc770421bc..1cd72b85d6 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -39,11 +39,9 @@ enum {
};
#if defined(TARGET_RISCV32)
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
#endif
#endif
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index d0c4843712..7bbbdb5036 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -257,221 +257,6 @@ static void spike_board_init(MachineState *machine)
false);
}
-static void spike_v1_10_0_board_init(MachineState *machine)
-{
- const struct MemmapEntry *memmap = spike_memmap;
-
- SpikeState *s = g_new0(SpikeState, 1);
- MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- int i;
- unsigned int smp_cpus = machine->smp.cpus;
-
- if (!qtest_enabled()) {
- info_report("The Spike v1.10.0 machine has been deprecated. "
- "Please use the generic spike machine and specify the ISA "
- "versions using -cpu.");
- }
-
- /* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
- &error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
- &error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
-
- /* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
- machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
- main_mem);
-
- /* create device tree */
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
-
- /* boot rom */
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
- memmap[SPIKE_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
- mask_rom);
-
- if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
- }
-
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
- 0xf1402573, /* csrr a0, mhartid */
-#if defined(TARGET_RISCV32)
- 0x0182a283, /* lw t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
- 0x0182b283, /* ld t0, 24(t0) */
-#endif
- 0x00028067, /* jr t0 */
- 0x00000000,
- memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
- 0x00000000,
- /* dtb: */
- };
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SPIKE_MROM].base, &address_space_memory);
-
- /* copy in the device tree */
- if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
- memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
- error_report("not enough space to store device-tree");
- exit(1);
- }
- qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
- rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
- &address_space_memory);
-
- /* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
-
- /* Core Local Interruptor (timer and IPI) */
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- false);
-}
-
-static void spike_v1_09_1_board_init(MachineState *machine)
-{
- const struct MemmapEntry *memmap = spike_memmap;
-
- SpikeState *s = g_new0(SpikeState, 1);
- MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- int i;
- unsigned int smp_cpus = machine->smp.cpus;
-
- if (!qtest_enabled()) {
- info_report("The Spike v1.09.1 machine has been deprecated. "
- "Please use the generic spike machine and specify the ISA "
- "versions using -cpu.");
- }
-
- /* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
- &error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
- &error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
-
- /* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
- machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
- main_mem);
-
- /* boot rom */
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
- memmap[SPIKE_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
- mask_rom);
-
- if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
- }
-
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
- 0x00028067, /* jump to DRAM_BASE */
- 0x00000000, /* reserved */
- memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
- 0, 0, 0, 0 /* trap vector */
- };
-
- /* part one of config string - before memory size specified */
- const char *config_string_tmpl =
- "platform {\n"
- " vendor ucb;\n"
- " arch spike;\n"
- "};\n"
- "rtc {\n"
- " addr 0x%" PRIx64 "x;\n"
- "};\n"
- "ram {\n"
- " 0 {\n"
- " addr 0x%" PRIx64 "x;\n"
- " size 0x%" PRIx64 "x;\n"
- " };\n"
- "};\n"
- "core {\n"
- " 0" " {\n"
- " " "0 {\n"
- " isa %s;\n"
- " timecmp 0x%" PRIx64 "x;\n"
- " ipi 0x%" PRIx64 "x;\n"
- " };\n"
- " };\n"
- "};\n";
-
- /* build config string with supplied memory size */
- char *isa = riscv_isa_string(&s->soc.harts[0]);
- char *config_string = g_strdup_printf(config_string_tmpl,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
- (uint64_t)memmap[SPIKE_DRAM].base,
- (uint64_t)ram_size, isa,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
- g_free(isa);
- size_t config_string_len = strlen(config_string);
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SPIKE_MROM].base, &address_space_memory);
-
- /* copy in the config string */
- rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
- &address_space_memory);
-
- /* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
-
- /* Core Local Interruptor (timer and IPI) */
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- false);
-
- g_free(config_string);
-}
-
-static void spike_v1_09_1_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
- mc->init = spike_v1_09_1_board_init;
- mc->max_cpus = 1;
-}
-
-static void spike_v1_10_0_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
- mc->init = spike_v1_10_0_board_init;
- mc->max_cpus = 1;
-}
-
static void spike_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Spike Board";
@@ -481,6 +266,4 @@ static void spike_machine_init(MachineClass *mc)
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}
-DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
-DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
DEFINE_MACHINE("spike", spike_machine_init)
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 1/4] hw/riscv: spike: Remove deprecated ISA specific machines
@ 2020-05-28 22:16 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23, bmeng.cn
The ISA specific Spike machines have been deprecated in QEMU since 4.1,
let's finally remove them.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
docs/system/deprecated.rst | 17 +--
include/hw/riscv/spike.h | 6 +-
hw/riscv/spike.c | 217 -------------------------------------
3 files changed, 12 insertions(+), 228 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index f0061f94aa..50927bad74 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -379,13 +379,6 @@ This machine has been renamed ``fuloong2e``.
These machine types are very old and likely can not be used for live migration
from old QEMU versions anymore. A newer machine type should be used instead.
-``spike_v1.9.1`` and ``spike_v1.10`` (since 4.1)
-''''''''''''''''''''''''''''''''''''''''''''''''
-
-The version specific Spike machines have been deprecated in favour of the
-generic ``spike`` machine. If you need to specify an older version of the RISC-V
-spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument.
-
Device options
--------------
@@ -493,6 +486,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
+System emulator machines
+------------------------
+
+``spike_v1.9.1`` and ``spike_v1.10`` (removed in 5.1)
+'''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The version specific Spike machines have been removed in favour of the
+generic ``spike`` machine. If you need to specify an older version of the RISC-V
+spec you can use the ``-cpu rv64gcsu,priv_spec=v1.10.0`` command line argument.
+
Related binaries
----------------
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index dc770421bc..1cd72b85d6 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -39,11 +39,9 @@ enum {
};
#if defined(TARGET_RISCV32)
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
#endif
#endif
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index d0c4843712..7bbbdb5036 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -257,221 +257,6 @@ static void spike_board_init(MachineState *machine)
false);
}
-static void spike_v1_10_0_board_init(MachineState *machine)
-{
- const struct MemmapEntry *memmap = spike_memmap;
-
- SpikeState *s = g_new0(SpikeState, 1);
- MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- int i;
- unsigned int smp_cpus = machine->smp.cpus;
-
- if (!qtest_enabled()) {
- info_report("The Spike v1.10.0 machine has been deprecated. "
- "Please use the generic spike machine and specify the ISA "
- "versions using -cpu.");
- }
-
- /* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
- &error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
- &error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
-
- /* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
- machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
- main_mem);
-
- /* create device tree */
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
-
- /* boot rom */
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
- memmap[SPIKE_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
- mask_rom);
-
- if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
- }
-
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
- 0xf1402573, /* csrr a0, mhartid */
-#if defined(TARGET_RISCV32)
- 0x0182a283, /* lw t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
- 0x0182b283, /* ld t0, 24(t0) */
-#endif
- 0x00028067, /* jr t0 */
- 0x00000000,
- memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
- 0x00000000,
- /* dtb: */
- };
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SPIKE_MROM].base, &address_space_memory);
-
- /* copy in the device tree */
- if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
- memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
- error_report("not enough space to store device-tree");
- exit(1);
- }
- qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
- rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
- &address_space_memory);
-
- /* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
-
- /* Core Local Interruptor (timer and IPI) */
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- false);
-}
-
-static void spike_v1_09_1_board_init(MachineState *machine)
-{
- const struct MemmapEntry *memmap = spike_memmap;
-
- SpikeState *s = g_new0(SpikeState, 1);
- MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- int i;
- unsigned int smp_cpus = machine->smp.cpus;
-
- if (!qtest_enabled()) {
- info_report("The Spike v1.09.1 machine has been deprecated. "
- "Please use the generic spike machine and specify the ISA "
- "versions using -cpu.");
- }
-
- /* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
- &error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
- &error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
-
- /* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
- machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
- main_mem);
-
- /* boot rom */
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
- memmap[SPIKE_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
- mask_rom);
-
- if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
- }
-
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
- 0x00028067, /* jump to DRAM_BASE */
- 0x00000000, /* reserved */
- memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
- 0, 0, 0, 0 /* trap vector */
- };
-
- /* part one of config string - before memory size specified */
- const char *config_string_tmpl =
- "platform {\n"
- " vendor ucb;\n"
- " arch spike;\n"
- "};\n"
- "rtc {\n"
- " addr 0x%" PRIx64 "x;\n"
- "};\n"
- "ram {\n"
- " 0 {\n"
- " addr 0x%" PRIx64 "x;\n"
- " size 0x%" PRIx64 "x;\n"
- " };\n"
- "};\n"
- "core {\n"
- " 0" " {\n"
- " " "0 {\n"
- " isa %s;\n"
- " timecmp 0x%" PRIx64 "x;\n"
- " ipi 0x%" PRIx64 "x;\n"
- " };\n"
- " };\n"
- "};\n";
-
- /* build config string with supplied memory size */
- char *isa = riscv_isa_string(&s->soc.harts[0]);
- char *config_string = g_strdup_printf(config_string_tmpl,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
- (uint64_t)memmap[SPIKE_DRAM].base,
- (uint64_t)ram_size, isa,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
- g_free(isa);
- size_t config_string_len = strlen(config_string);
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SPIKE_MROM].base, &address_space_memory);
-
- /* copy in the config string */
- rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
- &address_space_memory);
-
- /* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
-
- /* Core Local Interruptor (timer and IPI) */
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- false);
-
- g_free(config_string);
-}
-
-static void spike_v1_09_1_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
- mc->init = spike_v1_09_1_board_init;
- mc->max_cpus = 1;
-}
-
-static void spike_v1_10_0_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
- mc->init = spike_v1_10_0_board_init;
- mc->max_cpus = 1;
-}
-
static void spike_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Spike Board";
@@ -481,6 +266,4 @@ static void spike_machine_init(MachineClass *mc)
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}
-DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
-DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
DEFINE_MACHINE("spike", spike_machine_init)
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 1/4] hw/riscv: spike: Remove deprecated ISA specific machines
2020-05-28 22:16 ` Alistair Francis
@ 2020-05-29 5:34 ` Thomas Huth
-1 siblings, 0 replies; 20+ messages in thread
From: Thomas Huth @ 2020-05-29 5:34 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: alistair23, bmeng.cn, palmer
On 29/05/2020 00.16, Alistair Francis wrote:
> The ISA specific Spike machines have been deprecated in QEMU since 4.1,
> let's finally remove them.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
> docs/system/deprecated.rst | 17 +--
> include/hw/riscv/spike.h | 6 +-
> hw/riscv/spike.c | 217 -------------------------------------
> 3 files changed, 12 insertions(+), 228 deletions(-)
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 1/4] hw/riscv: spike: Remove deprecated ISA specific machines
@ 2020-05-29 5:34 ` Thomas Huth
0 siblings, 0 replies; 20+ messages in thread
From: Thomas Huth @ 2020-05-29 5:34 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: bmeng.cn, palmer, alistair23
On 29/05/2020 00.16, Alistair Francis wrote:
> The ISA specific Spike machines have been deprecated in QEMU since 4.1,
> let's finally remove them.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
> docs/system/deprecated.rst | 17 +--
> include/hw/riscv/spike.h | 6 +-
> hw/riscv/spike.c | 217 -------------------------------------
> 3 files changed, 12 insertions(+), 228 deletions(-)
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
2020-05-28 22:16 ` Alistair Francis
@ 2020-05-28 22:16 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
target/riscv/cpu.h | 7 -------
target/riscv/cpu.c | 28 ----------------------------
tests/qtest/machine-none-test.c | 4 ++--
4 files changed, 20 insertions(+), 52 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index 50927bad74..a6664bfca9 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version.
System emulator CPUS
--------------------
-RISC-V ISA CPUs (since 4.1)
-'''''''''''''''''''''''''''
-
-The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
-four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
-``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
-option when using the ``rv32`` or ``rv64`` CPUs.
-
-RISC-V ISA CPUs (since 4.1)
-'''''''''''''''''''''''''''
-
-The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
-``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
-via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
-
``compat`` property of server class POWER CPUs (since 5.0)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
@@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
+System emulator CPUS
+--------------------
+
+RISC-V ISA CPUs (removed in 5.1)
+''''''''''''''''''''''''''''''''
+
+The RISC-V cpus with the ISA version in the CPU name have been removed. The
+four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
+``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
+option when using the ``rv32`` or ``rv64`` CPUs.
+
+RISC-V ISA CPUs (removed in 5.1)
+''''''''''''''''''''''''''''''''
+
+The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
+``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
+via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
+
System emulator machines
------------------------
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0e7f5b9c5..76b98d7a33 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -40,13 +40,6 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
-/* Deprecated */
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..112f2e3a2f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
set_misa(env, 0);
}
-static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_09_1);
- set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_MMU);
- set_feature(env, RISCV_FEATURE_PMP);
-}
-
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
set_misa(env, 0);
}
-static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_09_1);
- set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_MMU);
- set_feature(env, RISCV_FEATURE_PMP);
-}
-
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
- /* Depreacted */
- DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
- /* Deprecated */
- DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
#endif
};
diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
index 8bb54a6360..b52311ec2e 100644
--- a/tests/qtest/machine-none-test.c
+++ b/tests/qtest/machine-none-test.c
@@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = {
{ "xtensa", "dc233c" },
{ "xtensaeb", "fsf" },
{ "hppa", "hppa" },
- { "riscv64", "rv64gcsu-v1.10.0" },
- { "riscv32", "rv32gcsu-v1.9.1" },
+ { "riscv64", "sifive-u54" },
+ { "riscv32", "sifive-u34" },
{ "rx", "rx62n" },
};
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
@ 2020-05-28 22:16 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23, bmeng.cn
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---
docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
target/riscv/cpu.h | 7 -------
target/riscv/cpu.c | 28 ----------------------------
tests/qtest/machine-none-test.c | 4 ++--
4 files changed, 20 insertions(+), 52 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index 50927bad74..a6664bfca9 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version.
System emulator CPUS
--------------------
-RISC-V ISA CPUs (since 4.1)
-'''''''''''''''''''''''''''
-
-The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
-four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
-``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
-option when using the ``rv32`` or ``rv64`` CPUs.
-
-RISC-V ISA CPUs (since 4.1)
-'''''''''''''''''''''''''''
-
-The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
-``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
-via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
-
``compat`` property of server class POWER CPUs (since 5.0)
''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
@@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
+System emulator CPUS
+--------------------
+
+RISC-V ISA CPUs (removed in 5.1)
+''''''''''''''''''''''''''''''''
+
+The RISC-V cpus with the ISA version in the CPU name have been removed. The
+four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
+``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
+option when using the ``rv32`` or ``rv64`` CPUs.
+
+RISC-V ISA CPUs (removed in 5.1)
+''''''''''''''''''''''''''''''''
+
+The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
+``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
+via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
+
System emulator machines
------------------------
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0e7f5b9c5..76b98d7a33 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -40,13 +40,6 @@
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
-/* Deprecated */
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
-#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 059d71f2c7..112f2e3a2f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
set_misa(env, 0);
}
-static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_09_1);
- set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_MMU);
- set_feature(env, RISCV_FEATURE_PMP);
-}
-
static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
set_misa(env, 0);
}
-static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
- set_priv_version(env, PRIV_VERSION_1_09_1);
- set_resetvec(env, DEFAULT_RSTVEC);
- set_feature(env, RISCV_FEATURE_MMU);
- set_feature(env, RISCV_FEATURE_PMP);
-}
-
static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
- /* Depreacted */
- DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
- /* Deprecated */
- DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
#endif
};
diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
index 8bb54a6360..b52311ec2e 100644
--- a/tests/qtest/machine-none-test.c
+++ b/tests/qtest/machine-none-test.c
@@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = {
{ "xtensa", "dc233c" },
{ "xtensaeb", "fsf" },
{ "hppa", "hppa" },
- { "riscv64", "rv64gcsu-v1.10.0" },
- { "riscv32", "rv32gcsu-v1.9.1" },
+ { "riscv64", "sifive-u54" },
+ { "riscv32", "sifive-u34" },
{ "rx", "rx62n" },
};
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
2020-05-28 22:16 ` Alistair Francis
@ 2020-06-01 4:51 ` Bin Meng
-1 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2020-06-01 4:51 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, May 29, 2020 at 6:24 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
> docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
> target/riscv/cpu.h | 7 -------
> target/riscv/cpu.c | 28 ----------------------------
> tests/qtest/machine-none-test.c | 4 ++--
> 4 files changed, 20 insertions(+), 52 deletions(-)
>
> diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
> index 50927bad74..a6664bfca9 100644
> --- a/docs/system/deprecated.rst
> +++ b/docs/system/deprecated.rst
> @@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version.
> System emulator CPUS
> --------------------
>
> -RISC-V ISA CPUs (since 4.1)
> -'''''''''''''''''''''''''''
> -
> -The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
> -four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> -``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> -option when using the ``rv32`` or ``rv64`` CPUs.
> -
> -RISC-V ISA CPUs (since 4.1)
Not sure if this is a typo. Should we say: RISC-V no MMU CPUs ? If
not, since the subsection titles are the same, should we merge the
following description to above?
> -'''''''''''''''''''''''''''
> -
> -The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
> -``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
> -via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> -
> ``compat`` property of server class POWER CPUs (since 5.0)
> ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
>
> @@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
> The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
> 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
>
> +System emulator CPUS
> +--------------------
> +
> +RISC-V ISA CPUs (removed in 5.1)
> +''''''''''''''''''''''''''''''''
> +
> +The RISC-V cpus with the ISA version in the CPU name have been removed. The
> +four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> +``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> +option when using the ``rv32`` or ``rv64`` CPUs.
> +
> +RISC-V ISA CPUs (removed in 5.1)
> +''''''''''''''''''''''''''''''''
> +
> +The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
> +``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
> +via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> +
> System emulator machines
> ------------------------
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d0e7f5b9c5..76b98d7a33 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -40,13 +40,6 @@
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> -/* Deprecated */
> -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
>
> #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 059d71f2c7..112f2e3a2f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
> set_misa(env, 0);
> }
>
> -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_09_1);
> - set_resetvec(env, DEFAULT_RSTVEC);
> - set_feature(env, RISCV_FEATURE_MMU);
> - set_feature(env, RISCV_FEATURE_PMP);
> -}
> -
> static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
> set_misa(env, 0);
> }
>
> -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_09_1);
> - set_resetvec(env, DEFAULT_RSTVEC);
> - set_feature(env, RISCV_FEATURE_MMU);
> - set_feature(env, RISCV_FEATURE_PMP);
> -}
> -
> static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> - /* Depreacted */
> - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> - /* Deprecated */
> - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
> #endif
> };
>
> diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
> index 8bb54a6360..b52311ec2e 100644
> --- a/tests/qtest/machine-none-test.c
> +++ b/tests/qtest/machine-none-test.c
> @@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = {
> { "xtensa", "dc233c" },
> { "xtensaeb", "fsf" },
> { "hppa", "hppa" },
> - { "riscv64", "rv64gcsu-v1.10.0" },
> - { "riscv32", "rv32gcsu-v1.9.1" },
> + { "riscv64", "sifive-u54" },
> + { "riscv32", "sifive-u34" },
I believe we should use "rv32" and "rv64" here.
> { "rx", "rx62n" },
> };
Regards,
Bin
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
@ 2020-06-01 4:51 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2020-06-01 4:51 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis
On Fri, May 29, 2020 at 6:24 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
> docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
> target/riscv/cpu.h | 7 -------
> target/riscv/cpu.c | 28 ----------------------------
> tests/qtest/machine-none-test.c | 4 ++--
> 4 files changed, 20 insertions(+), 52 deletions(-)
>
> diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
> index 50927bad74..a6664bfca9 100644
> --- a/docs/system/deprecated.rst
> +++ b/docs/system/deprecated.rst
> @@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version.
> System emulator CPUS
> --------------------
>
> -RISC-V ISA CPUs (since 4.1)
> -'''''''''''''''''''''''''''
> -
> -The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
> -four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> -``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> -option when using the ``rv32`` or ``rv64`` CPUs.
> -
> -RISC-V ISA CPUs (since 4.1)
Not sure if this is a typo. Should we say: RISC-V no MMU CPUs ? If
not, since the subsection titles are the same, should we merge the
following description to above?
> -'''''''''''''''''''''''''''
> -
> -The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
> -``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
> -via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> -
> ``compat`` property of server class POWER CPUs (since 5.0)
> ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
>
> @@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
> The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
> 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
>
> +System emulator CPUS
> +--------------------
> +
> +RISC-V ISA CPUs (removed in 5.1)
> +''''''''''''''''''''''''''''''''
> +
> +The RISC-V cpus with the ISA version in the CPU name have been removed. The
> +four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> +``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> +option when using the ``rv32`` or ``rv64`` CPUs.
> +
> +RISC-V ISA CPUs (removed in 5.1)
> +''''''''''''''''''''''''''''''''
> +
> +The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
> +``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
> +via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> +
> System emulator machines
> ------------------------
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d0e7f5b9c5..76b98d7a33 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -40,13 +40,6 @@
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> -/* Deprecated */
> -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
>
> #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 059d71f2c7..112f2e3a2f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
> set_misa(env, 0);
> }
>
> -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_09_1);
> - set_resetvec(env, DEFAULT_RSTVEC);
> - set_feature(env, RISCV_FEATURE_MMU);
> - set_feature(env, RISCV_FEATURE_PMP);
> -}
> -
> static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
> set_misa(env, 0);
> }
>
> -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
> -{
> - CPURISCVState *env = &RISCV_CPU(obj)->env;
> - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_09_1);
> - set_resetvec(env, DEFAULT_RSTVEC);
> - set_feature(env, RISCV_FEATURE_MMU);
> - set_feature(env, RISCV_FEATURE_PMP);
> -}
> -
> static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> - /* Depreacted */
> - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
> #elif defined(TARGET_RISCV64)
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> - /* Deprecated */
> - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
> #endif
> };
>
> diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
> index 8bb54a6360..b52311ec2e 100644
> --- a/tests/qtest/machine-none-test.c
> +++ b/tests/qtest/machine-none-test.c
> @@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = {
> { "xtensa", "dc233c" },
> { "xtensaeb", "fsf" },
> { "hppa", "hppa" },
> - { "riscv64", "rv64gcsu-v1.10.0" },
> - { "riscv32", "rv32gcsu-v1.9.1" },
> + { "riscv64", "sifive-u54" },
> + { "riscv32", "sifive-u34" },
I believe we should use "rv32" and "rv64" here.
> { "rx", "rx62n" },
> };
Regards,
Bin
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
2020-06-01 4:51 ` Bin Meng
@ 2020-06-01 21:22 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-06-01 21:22 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Palmer Dabbelt, Alistair Francis,
qemu-devel@nongnu.org Developers
On Sun, May 31, 2020 at 9:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, May 29, 2020 at 6:24 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Bin Meng <bin.meng@windriver.com>
> > ---
> > docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
> > target/riscv/cpu.h | 7 -------
> > target/riscv/cpu.c | 28 ----------------------------
> > tests/qtest/machine-none-test.c | 4 ++--
> > 4 files changed, 20 insertions(+), 52 deletions(-)
> >
> > diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
> > index 50927bad74..a6664bfca9 100644
> > --- a/docs/system/deprecated.rst
> > +++ b/docs/system/deprecated.rst
> > @@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version.
> > System emulator CPUS
> > --------------------
> >
> > -RISC-V ISA CPUs (since 4.1)
> > -'''''''''''''''''''''''''''
> > -
> > -The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
> > -four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> > -``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> > -option when using the ``rv32`` or ``rv64`` CPUs.
> > -
> > -RISC-V ISA CPUs (since 4.1)
>
> Not sure if this is a typo. Should we say: RISC-V no MMU CPUs ? If
> not, since the subsection titles are the same, should we merge the
> following description to above?
Good point.
To be more clear I have changed this to:
RISC-V ISA Specific CPUs (removed in 5.1)
...
RISC-V no MMU CPUs (removed in 5.1)
>
> > -'''''''''''''''''''''''''''
> > -
> > -The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
> > -``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
> > -via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> > -
> > ``compat`` property of server class POWER CPUs (since 5.0)
> > ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
> >
> > @@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
> > The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
> > 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
> >
> > +System emulator CPUS
> > +--------------------
> > +
> > +RISC-V ISA CPUs (removed in 5.1)
> > +''''''''''''''''''''''''''''''''
> > +
> > +The RISC-V cpus with the ISA version in the CPU name have been removed. The
> > +four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> > +``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> > +option when using the ``rv32`` or ``rv64`` CPUs.
> > +
> > +RISC-V ISA CPUs (removed in 5.1)
> > +''''''''''''''''''''''''''''''''
> > +
> > +The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
> > +``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
> > +via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> > +
> > System emulator machines
> > ------------------------
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index d0e7f5b9c5..76b98d7a33 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -40,13 +40,6 @@
> > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> > -/* Deprecated */
> > -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> > -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
> >
> > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 059d71f2c7..112f2e3a2f 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
> > set_misa(env, 0);
> > }
> >
> > -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > - CPURISCVState *env = &RISCV_CPU(obj)->env;
> > - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > - set_priv_version(env, PRIV_VERSION_1_09_1);
> > - set_resetvec(env, DEFAULT_RSTVEC);
> > - set_feature(env, RISCV_FEATURE_MMU);
> > - set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> > static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
> > set_misa(env, 0);
> > }
> >
> > -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > - CPURISCVState *env = &RISCV_CPU(obj)->env;
> > - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > - set_priv_version(env, PRIV_VERSION_1_09_1);
> > - set_resetvec(env, DEFAULT_RSTVEC);
> > - set_feature(env, RISCV_FEATURE_MMU);
> > - set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> > static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > @@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> > - /* Depreacted */
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
> > #elif defined(TARGET_RISCV64)
> > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> > - /* Deprecated */
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
> > #endif
> > };
> >
> > diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
> > index 8bb54a6360..b52311ec2e 100644
> > --- a/tests/qtest/machine-none-test.c
> > +++ b/tests/qtest/machine-none-test.c
> > @@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = {
> > { "xtensa", "dc233c" },
> > { "xtensaeb", "fsf" },
> > { "hppa", "hppa" },
> > - { "riscv64", "rv64gcsu-v1.10.0" },
> > - { "riscv32", "rv32gcsu-v1.9.1" },
> > + { "riscv64", "sifive-u54" },
> > + { "riscv32", "sifive-u34" },
>
> I believe we should use "rv32" and "rv64" here.
Done.
Alistair
>
> > { "rx", "rx62n" },
> > };
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v4 2/4] target/riscv: Remove the deprecated CPUs
@ 2020-06-01 21:22 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-06-01 21:22 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, qemu-devel@nongnu.org Developers,
open list:RISC-V, Palmer Dabbelt
On Sun, May 31, 2020 at 9:51 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Fri, May 29, 2020 at 6:24 AM Alistair Francis
> <alistair.francis@wdc.com> wrote:
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Bin Meng <bin.meng@windriver.com>
> > ---
> > docs/system/deprecated.rst | 33 ++++++++++++++++++---------------
> > target/riscv/cpu.h | 7 -------
> > target/riscv/cpu.c | 28 ----------------------------
> > tests/qtest/machine-none-test.c | 4 ++--
> > 4 files changed, 20 insertions(+), 52 deletions(-)
> >
> > diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
> > index 50927bad74..a6664bfca9 100644
> > --- a/docs/system/deprecated.rst
> > +++ b/docs/system/deprecated.rst
> > @@ -314,21 +314,6 @@ should be used instead of the 1.09.1 version.
> > System emulator CPUS
> > --------------------
> >
> > -RISC-V ISA CPUs (since 4.1)
> > -'''''''''''''''''''''''''''
> > -
> > -The RISC-V cpus with the ISA version in the CPU name have been depcreated. The
> > -four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> > -``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> > -option when using the ``rv32`` or ``rv64`` CPUs.
> > -
> > -RISC-V ISA CPUs (since 4.1)
>
> Not sure if this is a typo. Should we say: RISC-V no MMU CPUs ? If
> not, since the subsection titles are the same, should we merge the
> following description to above?
Good point.
To be more clear I have changed this to:
RISC-V ISA Specific CPUs (removed in 5.1)
...
RISC-V no MMU CPUs (removed in 5.1)
>
> > -'''''''''''''''''''''''''''
> > -
> > -The RISC-V no MMU cpus have been depcreated. The two CPUs: ``rv32imacu-nommu`` and
> > -``rv64imacu-nommu`` should no longer be used. Instead the MMU status can be specified
> > -via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> > -
> > ``compat`` property of server class POWER CPUs (since 5.0)
> > ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
> >
> > @@ -486,6 +471,24 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
> > The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
> > 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
> >
> > +System emulator CPUS
> > +--------------------
> > +
> > +RISC-V ISA CPUs (removed in 5.1)
> > +''''''''''''''''''''''''''''''''
> > +
> > +The RISC-V cpus with the ISA version in the CPU name have been removed. The
> > +four CPUs are: ``rv32gcsu-v1.9.1``, ``rv32gcsu-v1.10.0``, ``rv64gcsu-v1.9.1`` and
> > +``rv64gcsu-v1.10.0``. Instead the version can be specified via the CPU ``priv_spec``
> > +option when using the ``rv32`` or ``rv64`` CPUs.
> > +
> > +RISC-V ISA CPUs (removed in 5.1)
> > +''''''''''''''''''''''''''''''''
> > +
> > +The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and
> > +``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified
> > +via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
> > +
> > System emulator machines
> > ------------------------
> >
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index d0e7f5b9c5..76b98d7a33 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -40,13 +40,6 @@
> > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
> > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
> > -/* Deprecated */
> > -#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
> > -#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
> > -#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
> >
> > #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
> > #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 059d71f2c7..112f2e3a2f 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -135,16 +135,6 @@ static void riscv_base32_cpu_init(Object *obj)
> > set_misa(env, 0);
> > }
> >
> > -static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > - CPURISCVState *env = &RISCV_CPU(obj)->env;
> > - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > - set_priv_version(env, PRIV_VERSION_1_09_1);
> > - set_resetvec(env, DEFAULT_RSTVEC);
> > - set_feature(env, RISCV_FEATURE_MMU);
> > - set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> > static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > @@ -182,16 +172,6 @@ static void riscv_base64_cpu_init(Object *obj)
> > set_misa(env, 0);
> > }
> >
> > -static void rv64gcsu_priv1_09_1_cpu_init(Object *obj)
> > -{
> > - CPURISCVState *env = &RISCV_CPU(obj)->env;
> > - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> > - set_priv_version(env, PRIV_VERSION_1_09_1);
> > - set_resetvec(env, DEFAULT_RSTVEC);
> > - set_feature(env, RISCV_FEATURE_MMU);
> > - set_feature(env, RISCV_FEATURE_PMP);
> > -}
> > -
> > static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
> > {
> > CPURISCVState *env = &RISCV_CPU(obj)->env;
> > @@ -621,18 +601,10 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
> > - /* Depreacted */
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init)
> > #elif defined(TARGET_RISCV64)
> > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
> > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init),
> > - /* Deprecated */
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
> > - DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init)
> > #endif
> > };
> >
> > diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-test.c
> > index 8bb54a6360..b52311ec2e 100644
> > --- a/tests/qtest/machine-none-test.c
> > +++ b/tests/qtest/machine-none-test.c
> > @@ -54,8 +54,8 @@ static struct arch2cpu cpus_map[] = {
> > { "xtensa", "dc233c" },
> > { "xtensaeb", "fsf" },
> > { "hppa", "hppa" },
> > - { "riscv64", "rv64gcsu-v1.10.0" },
> > - { "riscv32", "rv32gcsu-v1.9.1" },
> > + { "riscv64", "sifive-u54" },
> > + { "riscv32", "sifive-u34" },
>
> I believe we should use "rv32" and "rv64" here.
Done.
Alistair
>
> > { "rx", "rx62n" },
> > };
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 3/4] target/riscv: Drop support for ISA spec version 1.09.1
2020-05-28 22:16 ` Alistair Francis
@ 2020-05-28 22:16 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/deprecated.rst | 20 +--
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 2 -
target/riscv/cpu_helper.c | 82 ++++-------
target/riscv/csr.c | 138 ++++--------------
.../riscv/insn_trans/trans_privileged.inc.c | 18 +--
target/riscv/monitor.c | 5 -
target/riscv/op_helper.c | 17 +--
8 files changed, 73 insertions(+), 210 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index a6664bfca9..38865daafc 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -301,16 +301,6 @@ The ``acl_show``, ``acl_reset``, ``acl_policy``, ``acl_add``, and
``acl_remove`` commands are deprecated with no replacement. Authorization
for VNC should be performed using the pluggable QAuthZ objects.
-Guest Emulator ISAs
--------------------
-
-RISC-V ISA privledge specification version 1.09.1 (since 4.1)
-'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
-
-The RISC-V ISA privledge specification version 1.09.1 has been deprecated.
-QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
-should be used instead of the 1.09.1 version.
-
System emulator CPUS
--------------------
@@ -471,6 +461,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
+Guest Emulator ISAs
+-------------------
+
+RISC-V ISA privledge specification version 1.09.1 (removed in 5.1)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The RISC-V ISA privledge specification version 1.09.1 has been removed.
+QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
+should be used instead of the 1.09.1 version.
+
System emulator CPUS
--------------------
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 76b98d7a33..c022539012 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -73,7 +73,6 @@ enum {
RISCV_FEATURE_MISA
};
-#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 112f2e3a2f..eeb91f8513 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -368,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
priv_version = PRIV_VERSION_1_11_0;
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
priv_version = PRIV_VERSION_1_10_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
- priv_version = PRIV_VERSION_1_09_1;
} else {
error_setg(errp,
"Unsupported privilege spec version '%s'",
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bc80aa87cf..62fe1ecc8f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -364,57 +364,36 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
mxr = get_field(env->vsstatus, MSTATUS_MXR);
}
- if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if (first_stage == true) {
- if (use_background) {
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->vsatp, SATP_MODE);
- } else {
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->satp, SATP_MODE);
- }
- widened = 0;
+ if (first_stage == true) {
+ if (use_background) {
+ base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP_MODE);
} else {
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
- vm = get_field(env->hgatp, HGATP_MODE);
- widened = 2;
- }
- sum = get_field(env->mstatus, MSTATUS_SUM);
- switch (vm) {
- case VM_1_10_SV32:
- levels = 2; ptidxbits = 10; ptesize = 4; break;
- case VM_1_10_SV39:
- levels = 3; ptidxbits = 9; ptesize = 8; break;
- case VM_1_10_SV48:
- levels = 4; ptidxbits = 9; ptesize = 8; break;
- case VM_1_10_SV57:
- levels = 5; ptidxbits = 9; ptesize = 8; break;
- case VM_1_10_MBARE:
- *physical = addr;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- return TRANSLATE_SUCCESS;
- default:
- g_assert_not_reached();
+ base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP_MODE);
}
- } else {
widened = 0;
- base = (hwaddr)(env->sptbr) << PGSHIFT;
- sum = !get_field(env->mstatus, MSTATUS_PUM);
- vm = get_field(env->mstatus, MSTATUS_VM);
- switch (vm) {
- case VM_1_09_SV32:
- levels = 2; ptidxbits = 10; ptesize = 4; break;
- case VM_1_09_SV39:
- levels = 3; ptidxbits = 9; ptesize = 8; break;
- case VM_1_09_SV48:
- levels = 4; ptidxbits = 9; ptesize = 8; break;
- case VM_1_09_MBARE:
- *physical = addr;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- return TRANSLATE_SUCCESS;
- default:
- g_assert_not_reached();
- }
+ } else {
+ base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, HGATP_MODE);
+ widened = 2;
+ }
+ sum = get_field(env->mstatus, MSTATUS_SUM);
+ switch (vm) {
+ case VM_1_10_SV32:
+ levels = 2; ptidxbits = 10; ptesize = 4; break;
+ case VM_1_10_SV39:
+ levels = 3; ptidxbits = 9; ptesize = 8; break;
+ case VM_1_10_SV48:
+ levels = 4; ptidxbits = 9; ptesize = 8; break;
+ case VM_1_10_SV57:
+ levels = 5; ptidxbits = 9; ptesize = 8; break;
+ case VM_1_10_MBARE:
+ *physical = addr;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return TRANSLATE_SUCCESS;
+ default:
+ g_assert_not_reached();
}
CPUState *cs = env_cpu(env);
@@ -588,7 +567,6 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
int page_fault_exceptions;
if (first_stage) {
page_fault_exceptions =
- (env->priv_ver >= PRIV_VERSION_1_10_0) &&
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
!pmp_violation;
} else {
@@ -941,8 +919,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
s = env->mstatus;
- s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
- get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
+ s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
@@ -979,8 +956,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
s = env->mstatus;
- s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
- get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
+ s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..383be0a955 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -58,31 +58,11 @@ static int ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
- uint32_t ctr_en = ~0u;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
return -1;
}
-
- /*
- * The counters are always enabled at run time on newer priv specs, as the
- * CSR has changed from controlling that the counters can be read to
- * controlling that the counters increment.
- */
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
- return 0;
- }
-
- if (env->priv < PRV_M) {
- ctr_en &= env->mcounteren;
- }
- if (env->priv < PRV_S) {
- ctr_en &= env->scounteren;
- }
- if (!(ctr_en & (1u << (csrno & 31)))) {
- return -1;
- }
#endif
return 0;
}
@@ -293,9 +273,6 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
-static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE |
- SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_SD;
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
@@ -304,20 +281,11 @@ static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
#if defined(TARGET_RISCV32)
-static const char valid_vm_1_09[16] = {
- [VM_1_09_MBARE] = 1,
- [VM_1_09_SV32] = 1,
-};
static const char valid_vm_1_10[16] = {
[VM_1_10_MBARE] = 1,
[VM_1_10_SV32] = 1
};
#elif defined(TARGET_RISCV64)
-static const char valid_vm_1_09[16] = {
- [VM_1_09_MBARE] = 1,
- [VM_1_09_SV39] = 1,
- [VM_1_09_SV48] = 1,
-};
static const char valid_vm_1_10[16] = {
[VM_1_10_MBARE] = 1,
[VM_1_10_SV39] = 1,
@@ -347,8 +315,7 @@ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
static int validate_vm(CPURISCVState *env, target_ulong vm)
{
- return (env->priv_ver >= PRIV_VERSION_1_10_0) ?
- valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf];
+ return valid_vm_1_10[vm & 0xf];
}
static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
@@ -358,34 +325,21 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
int dirty;
/* flush tlb on mstatus fields that affect VM */
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
- MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
- tlb_flush(env_cpu(env));
- }
- mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
- MSTATUS_MPP | MSTATUS_MXR |
- (validate_vm(env, get_field(val, MSTATUS_VM)) ?
- MSTATUS_VM : 0);
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
+ MSTATUS_MPRV | MSTATUS_SUM)) {
+ tlb_flush(env_cpu(env));
}
- if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
- MSTATUS_MPRV | MSTATUS_SUM)) {
- tlb_flush(env_cpu(env));
- }
- mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
- MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
- MSTATUS_TW;
+ mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
+ MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+ MSTATUS_TW;
#if defined(TARGET_RISCV64)
- /*
- * RV32: MPV and MTL are not in mstatus. The current plan is to
- * add them to mstatush. For now, we just don't support it.
- */
- mask |= MSTATUS_MTL | MSTATUS_MPV;
+ /*
+ * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * add them to mstatush. For now, we just don't support it.
+ */
+ mask |= MSTATUS_MTL | MSTATUS_MPV;
#endif
- }
mstatus = (mstatus & ~mask) | (val & mask);
@@ -534,18 +488,12 @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
*val = env->mcounteren;
return 0;
}
static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
env->mcounteren = val;
return 0;
}
@@ -553,8 +501,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
- if (env->priv_ver > PRIV_VERSION_1_09_1
- && env->priv_ver < PRIV_VERSION_1_11_0) {
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -1;
}
*val = env->mcounteren;
@@ -564,32 +511,13 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
- if (env->priv_ver > PRIV_VERSION_1_09_1
- && env->priv_ver < PRIV_VERSION_1_11_0) {
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -1;
}
env->mcounteren = val;
return 0;
}
-static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val)
-{
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
- return -1;
- }
- *val = env->scounteren;
- return 0;
-}
-
-static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val)
-{
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
- return -1;
- }
- env->scounteren = val;
- return 0;
-}
-
/* Machine Trap Handling */
static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -663,16 +591,14 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
/* Supervisor Trap Setup */
static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
{
- target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
- sstatus_v1_10_mask : sstatus_v1_9_mask);
+ target_ulong mask = (sstatus_v1_10_mask);
*val = env->mstatus & mask;
return 0;
}
static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
{
- target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
- sstatus_v1_10_mask : sstatus_v1_9_mask);
+ target_ulong mask = (sstatus_v1_10_mask);
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
return write_mstatus(env, CSR_MSTATUS, newval);
}
@@ -722,18 +648,12 @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
*val = env->scounteren;
return 0;
}
static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
env->scounteren = val;
return 0;
}
@@ -812,15 +732,15 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
*val = 0;
- } else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
- } else {
- *val = env->satp;
- }
+ return 0;
+ }
+
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
} else {
- *val = env->sptbr;
+ *val = env->satp;
}
+
return 0;
}
@@ -829,13 +749,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return 0;
}
- if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
- tlb_flush(env_cpu(env));
- env->sptbr = val & (((target_ulong)
- 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
- }
- if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
- validate_vm(env, get_field(val, SATP_MODE)) &&
+ if (validate_vm(env, get_field(val, SATP_MODE)) &&
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
@@ -1313,8 +1227,6 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
#endif
- /* Legacy Counter Setup (priv v1.9.1) */
- [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
/* Machine Trap Handling */
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
index 76c2fad71c..5f26e0f5ea 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -85,30 +85,21 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
- gen_helper_tlb_flush(cpu_env);
- return true;
- }
+ gen_helper_tlb_flush(cpu_env);
+ return true;
#endif
return false;
}
static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
{
-#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
- gen_helper_tlb_flush(cpu_env);
- return true;
- }
-#endif
return false;
}
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
+ if (has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
@@ -127,8 +118,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
+ if (has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index d725a7a36e..b569f08387 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -215,11 +215,6 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- monitor_printf(mon, "Privileged mode < 1.10 unsupported\n");
- return;
- }
-
if (!(env->satp & SATP_MODE)) {
monitor_printf(mon, "No translation or protection\n");
return;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index c6412f680c..b0c49efc4a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -84,8 +84,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
- if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
+ if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
@@ -119,10 +118,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
} else {
prev_priv = get_field(mstatus, MSTATUS_SPP);
- mstatus = set_field(mstatus,
- env->priv_ver >= PRIV_VERSION_1_10_0 ?
- MSTATUS_SIE : MSTATUS_UIE << prev_priv,
- get_field(mstatus, MSTATUS_SPIE));
+ mstatus = set_field(mstatus, MSTATUS_SIE,
+ get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
env->mstatus = mstatus;
@@ -147,10 +144,8 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
- mstatus = set_field(mstatus,
- env->priv_ver >= PRIV_VERSION_1_10_0 ?
- MSTATUS_MIE : MSTATUS_UIE << prev_priv,
- get_field(mstatus, MSTATUS_MPIE));
+ mstatus = set_field(mstatus, MSTATUS_MIE,
+ get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
#ifdef TARGET_RISCV32
@@ -177,7 +172,6 @@ void helper_wfi(CPURISCVState *env)
CPUState *cs = env_cpu(env);
if ((env->priv == PRV_S &&
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TW)) ||
riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
@@ -193,7 +187,6 @@ void helper_tlb_flush(CPURISCVState *env)
CPUState *cs = env_cpu(env);
if (!(env->priv >= PRV_S) ||
(env->priv == PRV_S &&
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 3/4] target/riscv: Drop support for ISA spec version 1.09.1
@ 2020-05-28 22:16 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23, bmeng.cn
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
4.1. It's not commonly used so let's remove support for it.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/deprecated.rst | 20 +--
target/riscv/cpu.h | 1 -
target/riscv/cpu.c | 2 -
target/riscv/cpu_helper.c | 82 ++++-------
target/riscv/csr.c | 138 ++++--------------
.../riscv/insn_trans/trans_privileged.inc.c | 18 +--
target/riscv/monitor.c | 5 -
target/riscv/op_helper.c | 17 +--
8 files changed, 73 insertions(+), 210 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index a6664bfca9..38865daafc 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -301,16 +301,6 @@ The ``acl_show``, ``acl_reset``, ``acl_policy``, ``acl_add``, and
``acl_remove`` commands are deprecated with no replacement. Authorization
for VNC should be performed using the pluggable QAuthZ objects.
-Guest Emulator ISAs
--------------------
-
-RISC-V ISA privledge specification version 1.09.1 (since 4.1)
-'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
-
-The RISC-V ISA privledge specification version 1.09.1 has been deprecated.
-QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
-should be used instead of the 1.09.1 version.
-
System emulator CPUS
--------------------
@@ -471,6 +461,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
+Guest Emulator ISAs
+-------------------
+
+RISC-V ISA privledge specification version 1.09.1 (removed in 5.1)
+''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The RISC-V ISA privledge specification version 1.09.1 has been removed.
+QEMU supports both the newer version 1.10.0 and the ratified version 1.11.0, these
+should be used instead of the 1.09.1 version.
+
System emulator CPUS
--------------------
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 76b98d7a33..c022539012 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -73,7 +73,6 @@ enum {
RISCV_FEATURE_MISA
};
-#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 112f2e3a2f..eeb91f8513 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -368,8 +368,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
priv_version = PRIV_VERSION_1_11_0;
} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
priv_version = PRIV_VERSION_1_10_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
- priv_version = PRIV_VERSION_1_09_1;
} else {
error_setg(errp,
"Unsupported privilege spec version '%s'",
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index bc80aa87cf..62fe1ecc8f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -364,57 +364,36 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
mxr = get_field(env->vsstatus, MSTATUS_MXR);
}
- if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if (first_stage == true) {
- if (use_background) {
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->vsatp, SATP_MODE);
- } else {
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->satp, SATP_MODE);
- }
- widened = 0;
+ if (first_stage == true) {
+ if (use_background) {
+ base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP_MODE);
} else {
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
- vm = get_field(env->hgatp, HGATP_MODE);
- widened = 2;
- }
- sum = get_field(env->mstatus, MSTATUS_SUM);
- switch (vm) {
- case VM_1_10_SV32:
- levels = 2; ptidxbits = 10; ptesize = 4; break;
- case VM_1_10_SV39:
- levels = 3; ptidxbits = 9; ptesize = 8; break;
- case VM_1_10_SV48:
- levels = 4; ptidxbits = 9; ptesize = 8; break;
- case VM_1_10_SV57:
- levels = 5; ptidxbits = 9; ptesize = 8; break;
- case VM_1_10_MBARE:
- *physical = addr;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- return TRANSLATE_SUCCESS;
- default:
- g_assert_not_reached();
+ base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP_MODE);
}
- } else {
widened = 0;
- base = (hwaddr)(env->sptbr) << PGSHIFT;
- sum = !get_field(env->mstatus, MSTATUS_PUM);
- vm = get_field(env->mstatus, MSTATUS_VM);
- switch (vm) {
- case VM_1_09_SV32:
- levels = 2; ptidxbits = 10; ptesize = 4; break;
- case VM_1_09_SV39:
- levels = 3; ptidxbits = 9; ptesize = 8; break;
- case VM_1_09_SV48:
- levels = 4; ptidxbits = 9; ptesize = 8; break;
- case VM_1_09_MBARE:
- *physical = addr;
- *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- return TRANSLATE_SUCCESS;
- default:
- g_assert_not_reached();
- }
+ } else {
+ base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, HGATP_MODE);
+ widened = 2;
+ }
+ sum = get_field(env->mstatus, MSTATUS_SUM);
+ switch (vm) {
+ case VM_1_10_SV32:
+ levels = 2; ptidxbits = 10; ptesize = 4; break;
+ case VM_1_10_SV39:
+ levels = 3; ptidxbits = 9; ptesize = 8; break;
+ case VM_1_10_SV48:
+ levels = 4; ptidxbits = 9; ptesize = 8; break;
+ case VM_1_10_SV57:
+ levels = 5; ptidxbits = 9; ptesize = 8; break;
+ case VM_1_10_MBARE:
+ *physical = addr;
+ *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
+ return TRANSLATE_SUCCESS;
+ default:
+ g_assert_not_reached();
}
CPUState *cs = env_cpu(env);
@@ -588,7 +567,6 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
int page_fault_exceptions;
if (first_stage) {
page_fault_exceptions =
- (env->priv_ver >= PRIV_VERSION_1_10_0) &&
get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
!pmp_violation;
} else {
@@ -941,8 +919,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
s = env->mstatus;
- s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
- get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv));
+ s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
s = set_field(s, MSTATUS_SPP, env->priv);
s = set_field(s, MSTATUS_SIE, 0);
env->mstatus = s;
@@ -979,8 +956,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
}
s = env->mstatus;
- s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ?
- get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv));
+ s = set_field(s, MSTATUS_MPIE, get_field(s, MSTATUS_MIE));
s = set_field(s, MSTATUS_MPP, env->priv);
s = set_field(s, MSTATUS_MIE, 0);
env->mstatus = s;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 11d184cd16..383be0a955 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -58,31 +58,11 @@ static int ctr(CPURISCVState *env, int csrno)
#if !defined(CONFIG_USER_ONLY)
CPUState *cs = env_cpu(env);
RISCVCPU *cpu = RISCV_CPU(cs);
- uint32_t ctr_en = ~0u;
if (!cpu->cfg.ext_counters) {
/* The Counters extensions is not enabled */
return -1;
}
-
- /*
- * The counters are always enabled at run time on newer priv specs, as the
- * CSR has changed from controlling that the counters can be read to
- * controlling that the counters increment.
- */
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
- return 0;
- }
-
- if (env->priv < PRV_M) {
- ctr_en &= env->mcounteren;
- }
- if (env->priv < PRV_S) {
- ctr_en &= env->scounteren;
- }
- if (!(ctr_en & (1u << (csrno & 31)))) {
- return -1;
- }
#endif
return 0;
}
@@ -293,9 +273,6 @@ static const target_ulong delegable_excps =
(1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
(1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
-static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE |
- SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_SD;
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
@@ -304,20 +281,11 @@ static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
#if defined(TARGET_RISCV32)
-static const char valid_vm_1_09[16] = {
- [VM_1_09_MBARE] = 1,
- [VM_1_09_SV32] = 1,
-};
static const char valid_vm_1_10[16] = {
[VM_1_10_MBARE] = 1,
[VM_1_10_SV32] = 1
};
#elif defined(TARGET_RISCV64)
-static const char valid_vm_1_09[16] = {
- [VM_1_09_MBARE] = 1,
- [VM_1_09_SV39] = 1,
- [VM_1_09_SV48] = 1,
-};
static const char valid_vm_1_10[16] = {
[VM_1_10_MBARE] = 1,
[VM_1_10_SV39] = 1,
@@ -347,8 +315,7 @@ static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
static int validate_vm(CPURISCVState *env, target_ulong vm)
{
- return (env->priv_ver >= PRIV_VERSION_1_10_0) ?
- valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf];
+ return valid_vm_1_10[vm & 0xf];
}
static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
@@ -358,34 +325,21 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
int dirty;
/* flush tlb on mstatus fields that affect VM */
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
- MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
- tlb_flush(env_cpu(env));
- }
- mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
- MSTATUS_MPP | MSTATUS_MXR |
- (validate_vm(env, get_field(val, MSTATUS_VM)) ?
- MSTATUS_VM : 0);
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
+ MSTATUS_MPRV | MSTATUS_SUM)) {
+ tlb_flush(env_cpu(env));
}
- if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
- MSTATUS_MPRV | MSTATUS_SUM)) {
- tlb_flush(env_cpu(env));
- }
- mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
- MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
- MSTATUS_TW;
+ mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
+ MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+ MSTATUS_TW;
#if defined(TARGET_RISCV64)
- /*
- * RV32: MPV and MTL are not in mstatus. The current plan is to
- * add them to mstatush. For now, we just don't support it.
- */
- mask |= MSTATUS_MTL | MSTATUS_MPV;
+ /*
+ * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * add them to mstatush. For now, we just don't support it.
+ */
+ mask |= MSTATUS_MTL | MSTATUS_MPV;
#endif
- }
mstatus = (mstatus & ~mask) | (val & mask);
@@ -534,18 +488,12 @@ static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
*val = env->mcounteren;
return 0;
}
static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
env->mcounteren = val;
return 0;
}
@@ -553,8 +501,7 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
- if (env->priv_ver > PRIV_VERSION_1_09_1
- && env->priv_ver < PRIV_VERSION_1_11_0) {
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -1;
}
*val = env->mcounteren;
@@ -564,32 +511,13 @@ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
- if (env->priv_ver > PRIV_VERSION_1_09_1
- && env->priv_ver < PRIV_VERSION_1_11_0) {
+ if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -1;
}
env->mcounteren = val;
return 0;
}
-static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val)
-{
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
- return -1;
- }
- *val = env->scounteren;
- return 0;
-}
-
-static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val)
-{
- if (env->priv_ver > PRIV_VERSION_1_09_1) {
- return -1;
- }
- env->scounteren = val;
- return 0;
-}
-
/* Machine Trap Handling */
static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
{
@@ -663,16 +591,14 @@ static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
/* Supervisor Trap Setup */
static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
{
- target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
- sstatus_v1_10_mask : sstatus_v1_9_mask);
+ target_ulong mask = (sstatus_v1_10_mask);
*val = env->mstatus & mask;
return 0;
}
static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
{
- target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
- sstatus_v1_10_mask : sstatus_v1_9_mask);
+ target_ulong mask = (sstatus_v1_10_mask);
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
return write_mstatus(env, CSR_MSTATUS, newval);
}
@@ -722,18 +648,12 @@ static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
*val = env->scounteren;
return 0;
}
static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
{
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- return -1;
- }
env->scounteren = val;
return 0;
}
@@ -812,15 +732,15 @@ static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
*val = 0;
- } else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
- return -1;
- } else {
- *val = env->satp;
- }
+ return 0;
+ }
+
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
} else {
- *val = env->sptbr;
+ *val = env->satp;
}
+
return 0;
}
@@ -829,13 +749,7 @@ static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return 0;
}
- if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
- tlb_flush(env_cpu(env));
- env->sptbr = val & (((target_ulong)
- 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
- }
- if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
- validate_vm(env, get_field(val, SATP_MODE)) &&
+ if (validate_vm(env, get_field(val, SATP_MODE)) &&
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
@@ -1313,8 +1227,6 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
#endif
- /* Legacy Counter Setup (priv v1.9.1) */
- [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
[CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
/* Machine Trap Handling */
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.inc.c
index 76c2fad71c..5f26e0f5ea 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -85,30 +85,21 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
- gen_helper_tlb_flush(cpu_env);
- return true;
- }
+ gen_helper_tlb_flush(cpu_env);
+ return true;
#endif
return false;
}
static bool trans_sfence_vm(DisasContext *ctx, arg_sfence_vm *a)
{
-#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
- gen_helper_tlb_flush(cpu_env);
- return true;
- }
-#endif
return false;
}
static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
+ if (has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
@@ -127,8 +118,7 @@ static bool trans_hfence_gvma(DisasContext *ctx, arg_sfence_vma *a)
static bool trans_hfence_bvma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver >= PRIV_VERSION_1_10_0 &&
- has_ext(ctx, RVH)) {
+ if (has_ext(ctx, RVH)) {
/* Hpervisor extensions exist */
/*
* if (env->priv == PRV_M ||
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index d725a7a36e..b569f08387 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -215,11 +215,6 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (env->priv_ver < PRIV_VERSION_1_10_0) {
- monitor_printf(mon, "Privileged mode < 1.10 unsupported\n");
- return;
- }
-
if (!(env->satp & SATP_MODE)) {
monitor_printf(mon, "No translation or protection\n");
return;
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index c6412f680c..b0c49efc4a 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -84,8 +84,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
- if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
- get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
+ if (get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
@@ -119,10 +118,8 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
} else {
prev_priv = get_field(mstatus, MSTATUS_SPP);
- mstatus = set_field(mstatus,
- env->priv_ver >= PRIV_VERSION_1_10_0 ?
- MSTATUS_SIE : MSTATUS_UIE << prev_priv,
- get_field(mstatus, MSTATUS_SPIE));
+ mstatus = set_field(mstatus, MSTATUS_SIE,
+ get_field(mstatus, MSTATUS_SPIE));
mstatus = set_field(mstatus, MSTATUS_SPIE, 1);
mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U);
env->mstatus = mstatus;
@@ -147,10 +144,8 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
target_ulong prev_virt = MSTATUS_MPV_ISSET(env);
- mstatus = set_field(mstatus,
- env->priv_ver >= PRIV_VERSION_1_10_0 ?
- MSTATUS_MIE : MSTATUS_UIE << prev_priv,
- get_field(mstatus, MSTATUS_MPIE));
+ mstatus = set_field(mstatus, MSTATUS_MIE,
+ get_field(mstatus, MSTATUS_MPIE));
mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
#ifdef TARGET_RISCV32
@@ -177,7 +172,6 @@ void helper_wfi(CPURISCVState *env)
CPUState *cs = env_cpu(env);
if ((env->priv == PRV_S &&
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TW)) ||
riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
@@ -193,7 +187,6 @@ void helper_tlb_flush(CPURISCVState *env)
CPUState *cs = env_cpu(env);
if (!(env->priv >= PRV_S) ||
(env->priv == PRV_S &&
- env->priv_ver >= PRIV_VERSION_1_10_0 &&
get_field(env->mstatus, MSTATUS_TVM))) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
} else {
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 3/4] target/riscv: Drop support for ISA spec version 1.09.1
2020-05-28 22:16 ` Alistair Francis
@ 2020-06-01 4:55 ` Bin Meng
-1 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2020-06-01 4:55 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, May 29, 2020 at 6:24 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
> 4.1. It's not commonly used so let's remove support for it.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> docs/system/deprecated.rst | 20 +--
> target/riscv/cpu.h | 1 -
> target/riscv/cpu.c | 2 -
> target/riscv/cpu_helper.c | 82 ++++-------
> target/riscv/csr.c | 138 ++++--------------
> .../riscv/insn_trans/trans_privileged.inc.c | 18 +--
> target/riscv/monitor.c | 5 -
> target/riscv/op_helper.c | 17 +--
> 8 files changed, 73 insertions(+), 210 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/4] target/riscv: Drop support for ISA spec version 1.09.1
@ 2020-06-01 4:55 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2020-06-01 4:55 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis
On Fri, May 29, 2020 at 6:24 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since
> 4.1. It's not commonly used so let's remove support for it.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> docs/system/deprecated.rst | 20 +--
> target/riscv/cpu.h | 1 -
> target/riscv/cpu.c | 2 -
> target/riscv/cpu_helper.c | 82 ++++-------
> target/riscv/csr.c | 138 ++++--------------
> .../riscv/insn_trans/trans_privileged.inc.c | 18 +--
> target/riscv/monitor.c | 5 -
> target/riscv/op_helper.c | 17 +--
> 8 files changed, 73 insertions(+), 210 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 4/4] docs: deprecated: Update the -bios documentation
2020-05-28 22:16 ` Alistair Francis
@ 2020-05-28 22:16 ` Alistair Francis
-1 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: alistair.francis, bmeng.cn, palmer, alistair23
Update the -bios deprecation documentation to describe the new
behaviour.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/deprecated.rst | 28 +++++++++++++---------------
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index 38865daafc..8c445d4062 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -138,25 +138,23 @@ the backing storage specified with ``-mem-path`` can actually provide
the guest RAM configured with ``-m`` and QEMU will fail to start up if
RAM allocation is unsuccessful.
-RISC-V ``-bios`` (since 4.1)
+RISC-V ``-bios`` (since 5.1)
''''''''''''''''''''''''''''
QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the
-RISC-V virt machine and sifive_u machine.
-
-QEMU 4.1 has no changes to the default behaviour to avoid breakages. This
-default will change in a future QEMU release, so please prepare now. All users
-of the virt or sifive_u machine must change their command line usage.
-
-QEMU 4.1 has three options, please migrate to one of these three:
- 1. ``-bios none`` - This is the current default behavior if no -bios option
- is included. QEMU will not automatically load any firmware. It is up
+RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the
+default behaviour to avoid breakages.
+
+QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``.
+
+QEMU 5.1 has three options:
+ 1. ``-bios default`` - This is the current default behavior if no -bios option
+ is included. This option will load the default OpenSBI firmware automatically.
+ The firmware is included with the QEMU release and no user interaction is
+ required. All a user needs to do is specify the kernel they want to boot
+ with the -kernel option
+ 2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
to the user to load all the images they need.
- 2. ``-bios default`` - In a future QEMU release this will become the default
- behaviour if no -bios option is specified. This option will load the
- default OpenSBI firmware automatically. The firmware is included with
- the QEMU release and no user interaction is required. All a user needs
- to do is specify the kernel they want to boot with the -kernel option
3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmwrae.
``-tb-size`` option (since 5.0)
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v4 4/4] docs: deprecated: Update the -bios documentation
@ 2020-05-28 22:16 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2020-05-28 22:16 UTC (permalink / raw)
To: qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, alistair23, bmeng.cn
Update the -bios deprecation documentation to describe the new
behaviour.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/deprecated.rst | 28 +++++++++++++---------------
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index 38865daafc..8c445d4062 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -138,25 +138,23 @@ the backing storage specified with ``-mem-path`` can actually provide
the guest RAM configured with ``-m`` and QEMU will fail to start up if
RAM allocation is unsuccessful.
-RISC-V ``-bios`` (since 4.1)
+RISC-V ``-bios`` (since 5.1)
''''''''''''''''''''''''''''
QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the
-RISC-V virt machine and sifive_u machine.
-
-QEMU 4.1 has no changes to the default behaviour to avoid breakages. This
-default will change in a future QEMU release, so please prepare now. All users
-of the virt or sifive_u machine must change their command line usage.
-
-QEMU 4.1 has three options, please migrate to one of these three:
- 1. ``-bios none`` - This is the current default behavior if no -bios option
- is included. QEMU will not automatically load any firmware. It is up
+RISC-V virt machine and sifive_u machine. QEMU 4.1 had no changes to the
+default behaviour to avoid breakages.
+
+QEMU 5.1 changes the default behaviour from ``-bios none`` to ``-bios default``.
+
+QEMU 5.1 has three options:
+ 1. ``-bios default`` - This is the current default behavior if no -bios option
+ is included. This option will load the default OpenSBI firmware automatically.
+ The firmware is included with the QEMU release and no user interaction is
+ required. All a user needs to do is specify the kernel they want to boot
+ with the -kernel option
+ 2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
to the user to load all the images they need.
- 2. ``-bios default`` - In a future QEMU release this will become the default
- behaviour if no -bios option is specified. This option will load the
- default OpenSBI firmware automatically. The firmware is included with
- the QEMU release and no user interaction is required. All a user needs
- to do is specify the kernel they want to boot with the -kernel option
3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmwrae.
``-tb-size`` option (since 5.0)
--
2.26.2
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v4 4/4] docs: deprecated: Update the -bios documentation
2020-05-28 22:16 ` Alistair Francis
@ 2020-06-01 4:55 ` Bin Meng
-1 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2020-06-01 4:55 UTC (permalink / raw)
To: Alistair Francis
Cc: Palmer Dabbelt, open list:RISC-V,
qemu-devel@nongnu.org Developers, Alistair Francis
On Fri, May 29, 2020 at 6:24 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Update the -bios deprecation documentation to describe the new
> behaviour.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> docs/system/deprecated.rst | 28 +++++++++++++---------------
> 1 file changed, 13 insertions(+), 15 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 4/4] docs: deprecated: Update the -bios documentation
@ 2020-06-01 4:55 ` Bin Meng
0 siblings, 0 replies; 20+ messages in thread
From: Bin Meng @ 2020-06-01 4:55 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Palmer Dabbelt, Alistair Francis
On Fri, May 29, 2020 at 6:24 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Update the -bios deprecation documentation to describe the new
> behaviour.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> docs/system/deprecated.rst | 28 +++++++++++++---------------
> 1 file changed, 13 insertions(+), 15 deletions(-)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 20+ messages in thread